// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: ccu.bind.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef INC_CCU_BIND_VRI #define INC_CCU_BIND_VRI #include "ccu.port.vri" #include "ccu.if.vri" bind CCU_clk_port ccu_clk_bind { sys_clk ccu_pll_sys_clk_p_if.pll_sys_clk_p; cmp_pll_clk ccu_cmp_pll_clk_if.cmp_pll_clk; rst_ccu_pll_ ccu_rst_ccu_pll_if.rst_ccu_pll_; ccu_io2x_out ccu_io2x_out_if.ccu_io2x_out; #ifndef GATESIM ccu_rst_sys_clk ccu_rst_sys_clk_if.ccu_rst_sys_clk; gclk ccu_gclk_if.gclk; dr_pll_clk ccu_dr_pll_clk_if.dr_pll_clk; ccu_io_out ccu_io_out_if.ccu_io_out; ccu_cmp_io_sync_en ccu_cmp_io_sync_en_if.ccu_cmp_io_sync_en; ccu_io_cmp_sync_en ccu_io_cmp_sync_en_if.ccu_io_cmp_sync_en; ccu_dr_sync_en ccu_dr_sync_en_if.ccu_dr_sync_en; ccu_io2x_sync_en ccu_io2x_sync_en_if.ccu_io2x_sync_en; ccu_cmp_sys_sync_en ccu_cmp_sys_sync_en_if.ccu_cmp_sys_sync_en; ccu_sys_cmp_sync_en ccu_sys_cmp_sync_en_if.ccu_sys_cmp_sync_en; rst_ccu_ ccu_rst_ccu_if.rst_ccu_; ccu_rst_sync_stable ccu_rst_sync_stable_if.ccu_rst_sync_stable; ccu_rst_change ccu_rst_change_if.ccu_rst_change; ccu_vco_aligned ccu_vco_aligned_if.ccu_vco_aligned; gclk_aligned ccu_gclk_aligned_if.gclk_aligned; gl_ccu_clk_stop gl_ccu_clk_stop_if.gl_ccu_clk_stop; gl_ccu_io_clk_stop gl_ccu_io_clk_stop_if.gl_ccu_io_clk_stop; tcu_atpg_mode tcu_atpg_mode_if.tcu_atpg_mode; ref_clk ccu_ref_clk_if.ref_clk; #endif } #ifndef GATESIM bind CCU_mon_port ccu_mon_bind { cmp_pll_clk ccu_mon_if.cmp_pll_clk; ccu_cmp_io_sync_en ccu_mon_if.ccu_cmp_io_sync_en; ccu_cmp_sys_sync_en ccu_mon_if.ccu_cmp_sys_sync_en; ccu_dbg1_serdes_dtm ccu_mon_if.ccu_dbg1_serdes_dtm; ccu_dr_sync_en ccu_mon_if.ccu_dr_sync_en; ccu_io2x_out ccu_mon_if.ccu_io2x_out; ccu_io2x_sync_en ccu_mon_if.ccu_io2x_sync_en; ccu_io_cmp_sync_en ccu_mon_if.ccu_io_cmp_sync_en; ccu_io_out ccu_mon_if.ccu_io_out; ccu_mio_pll_char_out ccu_mon_if.ccu_mio_pll_char_out; ccu_mio_serdes_dtm ccu_mon_if.ccu_mio_serdes_dtm; ccu_rst_change ccu_mon_if.ccu_rst_change; ccu_rst_sync_stable ccu_mon_if.ccu_rst_sync_stable; ccu_rst_sys_clk ccu_mon_if.ccu_rst_sys_clk; ccu_serdes_dtm ccu_mon_if.ccu_serdes_dtm; ccu_sys_cmp_sync_en ccu_mon_if.ccu_sys_cmp_sync_en; ccu_vco_aligned ccu_mon_if.ccu_vco_aligned; cluster_arst_l ccu_mon_if.cluster_arst_l; gclk ccu_mon_if.gclk; dr_pll_clk ccu_mon_if.dr_pll_clk; gclk_aligned ccu_mon_if.gclk_aligned; gl_ccu_clk_stop ccu_mon_if.gl_ccu_clk_stop; gl_ccu_io_clk_stop ccu_mon_if.gl_ccu_io_clk_stop; gl_ccu_io_out ccu_mon_if.gl_ccu_io_out; mio_ccu_pll_char_in ccu_mon_if.mio_ccu_pll_char_in; mio_ccu_pll_clamp_fltr ccu_mon_if.mio_ccu_pll_clamp_fltr; mio_ccu_pll_div2 ccu_mon_if.mio_ccu_pll_div2; mio_ccu_pll_div4 ccu_mon_if.mio_ccu_pll_div4; mio_ccu_pll_trst_l ccu_mon_if.mio_ccu_pll_trst_l; mio_ccu_vreg_selbg_l ccu_mon_if.mio_ccu_vreg_selbg_l; mio_pll_testmode ccu_mon_if.mio_pll_testmode; pll_sys_clk_n ccu_mon_if.pll_sys_clk_n; pll_sys_clk_p ccu_mon_if.pll_sys_clk_p; pll_vdd ccu_mon_if.pll_vdd; rng_anlg_sel ccu_mon_if.rng_anlg_sel; rng_arst_l ccu_mon_if.rng_arst_l; rng_bypass ccu_mon_if.rng_bypass; rng_ch_sel ccu_mon_if.rng_ch_sel; rng_data ccu_mon_if.rng_data; rng_vcoctrl_sel ccu_mon_if.rng_vcoctrl_sel; rst_ccu_ ccu_mon_if.rst_ccu_; rst_ccu_pll_ ccu_mon_if.rst_ccu_pll_; rst_wmr_protect ccu_mon_if.rst_wmr_protect; scan_in ccu_mon_if.scan_in; scan_out ccu_mon_if.scan_out; tcu_aclk ccu_mon_if.tcu_aclk; tcu_atpg_mode ccu_mon_if.tcu_atpg_mode; tcu_bclk ccu_mon_if.tcu_bclk; tcu_ccu_clk_stretch ccu_mon_if.tcu_ccu_clk_stretch; tcu_ccu_ext_cmp_clk ccu_mon_if.tcu_ccu_ext_cmp_clk; tcu_ccu_ext_dr_clk ccu_mon_if.tcu_ccu_ext_dr_clk; tcu_ccu_mux_sel ccu_mon_if.tcu_ccu_mux_sel; tcu_pce_ov ccu_mon_if.tcu_pce_ov; tcu_scan_en ccu_mon_if.tcu_scan_en; ref_clk ccu_mon_if.ref_clk; pll_div1_at_csrblk ccu_mon_if.pll_div1; pll_div2_at_csrblk ccu_mon_if.pll_div2; pll_div3_at_csrblk ccu_mon_if.pll_div3; pll_div4_at_csrblk ccu_mon_if.pll_div4; serdes_dtm1_at_csrblk ccu_mon_if.serdes_dtm1; serdes_dtm2_at_csrblk ccu_mon_if.serdes_dtm2; } bind CCU_mon_ioclk_port ccu_mon_ioclk_bind { iol2clk ccu_mon_ioclk_if.iol2clk; csr_rd_req_vld ccu_mon_ioclk_if.rd_req_vld; csr_rd_ack_vld ccu_mon_ioclk_if.rd_ack_vld; csr_lfsr_data ccu_mon_ioclk_if.lfsr_data; } bind CCU_clks_internal_port ccu_clks_internal_bind { l2clk ccu_rst_sys_sync_en_if.l2clk; rst_ccu_cmp_sys_sync_en ccu_rst_sys_sync_en_if.ccu_cmp_sys_sync_en; rst_ccu_cmp_sys_sync_en3 ccu_rst_sys_sync_en_if.ccu_cmp_sys_sync_en3; rst_ccu_sys_cmp_sync_en ccu_rst_sys_sync_en_if.ccu_sys_cmp_sync_en; rst_ccu_sys_cmp_sync_en3 ccu_rst_sys_sync_en_if.ccu_sys_cmp_sync_en3; } #endif #endif