// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cluster_hdr.if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_CLUSTER_HDR_IF_VRI
#define INC_CLUSTER_HDR_IF_VRI

#include "fc_top_defines.vri"

//
// WARNING: this file is generated by script gen_cluster_hdr.pl. Do not modify.
//

//###########################################################
//### interfaces for DR and IO2X headers in ccu_mon module ##
//###########################################################
interface clkgen_ccumon_dr_l2clk_if {
  input  l2clk CLOCK verilog_node "`TOP.ccu_mon.clkgen_dr.l2clk";
}
interface clkgen_ccumon_io2x_l2clk_if {
  input  l2clk  CLOCK verilog_node "`TOP.ccu_mon.clkgen_io2x.l2clk";
}
//##########################################################
//### interfaces for cluster headers (blocks in TCU SAT) ###
//##########################################################

//----- VERA interfaces for clkgen_ccu_cmp -----

interface clkgen_ccu_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.ccu.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_protect";
}

interface clkgen_ccu_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.ccu.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_ccu_io -----

interface clkgen_ccu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.ccu.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_protect";
}

interface clkgen_ccu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.ccu.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccu.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_db0_cmp -----

interface clkgen_db0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_protect";
}

interface clkgen_db0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_cmp_clk.wmr_protect";
}

//----- VERA interfaces for clkgen_db0_io -----

interface clkgen_db0_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_protect";
}

interface clkgen_db0_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg0.db0_clk_header_iol2clk.wmr_protect";
}

//----- VERA interfaces for clkgen_db1_cmp -----

interface clkgen_db1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_protect";
}

interface clkgen_db1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_cmp_clk.wmr_protect";
}

//----- VERA interfaces for clkgen_db1_io -----

interface clkgen_db1_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_protect";
}

interface clkgen_db1_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dbg1.db1_clk_header_iol2clk.wmr_protect";
}

//----- VERA interfaces for clkgen_efu_io -----

interface clkgen_efu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.efu.efu_ioclk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_protect";
}

interface clkgen_efu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.efu.efu_ioclk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.efu.efu_ioclk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_efu_cmp -----

interface clkgen_efu_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.efu.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_protect";
}

interface clkgen_efu_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.efu.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.efu.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_mio_0_cmp -----

interface clkgen_mio_0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_protect";
}

interface clkgen_mio_0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_0.wmr_protect";
}

//----- VERA interfaces for clkgen_mio_1_cmp -----

interface clkgen_mio_1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_protect";
}

interface clkgen_mio_1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_1.wmr_protect";
}

//----- VERA interfaces for clkgen_mio_2_cmp -----

interface clkgen_mio_2_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_protect";
}

interface clkgen_mio_2_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_2.wmr_protect";
}

//----- VERA interfaces for clkgen_mio_3_cmp -----

interface clkgen_mio_3_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_protect";
}

interface clkgen_mio_3_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_cmp_clk_3.wmr_protect";
}

//----- VERA interfaces for clkgen_mio_io -----

interface clkgen_mio_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mio.mio_clk_header_iol2clk.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_protect";
}

interface clkgen_mio_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mio.mio_clk_header_iol2clk.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mio.mio_clk_header_iol2clk.wmr_protect";
}

//----- VERA interfaces for clkgen_ncu_cmp -----

interface clkgen_ncu_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.ncu.clkgen_ncu_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_protect";
}

interface clkgen_ncu_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.ncu.clkgen_ncu_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_ncu_io -----

interface clkgen_ncu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.ncu.clkgen_ncu_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_protect";
}

interface clkgen_ncu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.ncu.clkgen_ncu_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ncu.clkgen_ncu_io.wmr_protect";
}

//----- VERA interfaces for clkgen_rst_cmp -----

interface clkgen_rst_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rst.clkgen_rst_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_protect";
}

interface clkgen_rst_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rst.clkgen_rst_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_rst_io -----

interface clkgen_rst_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rst.clkgen_rst_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_protect";
}

interface clkgen_rst_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rst.clkgen_rst_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rst.clkgen_rst_io.wmr_protect";
}

//----- VERA interfaces for clkgen_tcu_cmp -----

interface clkgen_tcu_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.tcu.clkgen_tcu_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_protect";
}

interface clkgen_tcu_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.tcu.clkgen_tcu_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_tcu_io -----

interface clkgen_tcu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.tcu.clkgen_tcu_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_protect";
}

interface clkgen_tcu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.tcu.clkgen_tcu_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tcu.clkgen_tcu_io.wmr_protect";
}

//##############################################################
//### interfaces for cluster headers (blocks not in TCU SAT) ###
//##############################################################

#ifdef FC_BENCH

//----- VERA interfaces for clkgen_ccx_cmp -----

//--- gclk_left, tcu_clk_stop_left, tcu_div_bypass_left. Need to check them
//--- with 0-in assertions

interface clkgen_ccx_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.ccx.clk_ccx.gclk_right";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cluster_arst_l_right";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_clk_stop_right";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_div_bypass_right";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_protect";
}

interface clkgen_ccx_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.ccx.clk_ccx.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.ccx.clk_ccx.wmr_protect";
}

//----- VERA interfaces for clkgen_dmu_io -----

interface clkgen_dmu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.dmu.dmu_clkgen.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_protect";
}

interface clkgen_dmu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.dmu.dmu_clkgen.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.dmu.dmu_clkgen.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b0_cmp -----

interface clkgen_l2b0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b0.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_protect";
}

interface clkgen_l2b0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b0.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b0.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b1_cmp -----

interface clkgen_l2b1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b1.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_protect";
}

interface clkgen_l2b1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b1.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b1.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b2_cmp -----

interface clkgen_l2b2_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b2.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_protect";
}

interface clkgen_l2b2_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b2.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b2.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b3_cmp -----

interface clkgen_l2b3_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b3.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_protect";
}

interface clkgen_l2b3_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b3.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b3.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b4_cmp -----

interface clkgen_l2b4_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b4.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_protect";
}

interface clkgen_l2b4_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b4.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b4.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b5_cmp -----

interface clkgen_l2b5_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b5.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_protect";
}

interface clkgen_l2b5_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b5.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b5.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b6_cmp -----

interface clkgen_l2b6_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b6.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_protect";
}

interface clkgen_l2b6_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b6.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b6.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2b7_cmp -----

interface clkgen_l2b7_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2b7.clock_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_protect";
}

interface clkgen_l2b7_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2b7.clock_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2b7.clock_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2d0_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d0_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d0.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d0_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d0.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d0.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d1_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d1_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d1.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d1_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d1.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d1.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d2_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d2_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d2.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d2_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d2.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d2.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d3_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d3_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d3.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_protect";
  }
  
 interface clkgen_l2d3_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d3.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d3.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d4_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d4_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d4.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d4_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d4.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d4.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d5_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d5_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d5.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d5_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d5.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d5.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d6_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d6_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d6.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d6_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d6.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d6.l2d_clk_header.wmr_protect";
  }


//----- VERA interfaces for clkgen_l2d7_cmp -----
//----- warning: l2d<n> do NOT use  clkgen_l2d_cmp, but instantiates 
//-----   n2_clk_clstr_hdr_cust and pregrid drivers (ie. n2_clk_l2d_cmp_cust) directly
  
  interface clkgen_l2d7_cmp_gclk_if {
    input  gclk  CLOCK verilog_node "`CPU.l2d7.l2d_clk_header.gclk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.bclk";
    input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_cmp_slow_sync_en";
    input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_div_ph";
  //input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_serdes_dtm";       // does NOT have this port
    input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.ccu_slow_cmp_sync_en";
  //input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.clk_ext";              // does NOT have this port
    input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cluster_arst_l";
    input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cluster_div_en";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cmp_slow_sync_en";
    input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_pregrid_drv_bot.l2clk";          // warning: this is real l2clk
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.por_";
    input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_por_";
    input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_wmr_";
    input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.rst_wmr_protect";
    input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_en";
    input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_in";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.slow_cmp_sync_en";
    input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_aclk";
    input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_atpg_mode";
    input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_bclk";
    input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_clk_stop";
    input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_div_bypass";
    input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_pce_ov";
    input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.tcu_wr_inhibit";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_protect";
  }
  
  interface clkgen_l2d7_cmp_l2clk_if {
    input  l2clk  CLOCK verilog_node "`CPU.l2d7.l2d_pregrid_drv_bot.l2clk";  // Vera interface clock
  
    input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk";
    input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.aclk_wmr";
    input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.array_wr_inhibit";
    input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.bclk";
    input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.cmp_slow_sync_en";
    input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.pce_ov";
    input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.por_";
    input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.scan_out";
    input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.slow_cmp_sync_en";
    input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_";
    input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2d7.l2d_clk_header.wmr_protect";
  }

//----- VERA interfaces for clkgen_l2t0_cmp -----

interface clkgen_l2t0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t0.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t0.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t0.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t1_cmp -----

interface clkgen_l2t1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t1.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t1.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t1.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t2_cmp -----

interface clkgen_l2t2_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t2.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t2_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t2.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t2.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t3_cmp -----

interface clkgen_l2t3_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t3.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t3_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t3.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t3.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t4_cmp -----

interface clkgen_l2t4_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t4.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t4_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t4.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t4.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t5_cmp -----

interface clkgen_l2t5_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t5.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t5_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t5.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t5.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t6_cmp -----

interface clkgen_l2t6_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t6.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t6_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t6.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t6.l2t_clk_header.wmr_protect";
}

//----- VERA interfaces for clkgen_l2t7_cmp -----

interface clkgen_l2t7_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.l2t7.l2t_clk_header.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_protect";
}

interface clkgen_l2t7_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.l2t7.l2t_clk_header.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.l2t7.l2t_clk_header.wmr_protect";
}

#ifndef FC_NO_NIU_T2
#ifndef NIU_SYSTEMC_T2
//----- VERA interfaces for clkgen_mac_io -----

interface clkgen_mac_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_protect";
}

interface clkgen_mac_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mac.clkgen_mac.clkgen_mac_io.wmr_protect";
}
#endif
#endif

//----- VERA interfaces for clkgen_mcu0_cmp -----

interface clkgen_mcu0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu0.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_protect";
}

interface clkgen_mcu0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu0.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu0_dr -----

interface clkgen_mcu0_dr_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu0.clkgen_dr.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_protect";
}

interface clkgen_mcu0_dr_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu0.clkgen_dr.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_dr.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu0_io -----

interface clkgen_mcu0_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu0.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_protect";
}

interface clkgen_mcu0_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu0.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu0.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu1_cmp -----

interface clkgen_mcu1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu1.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_protect";
}

interface clkgen_mcu1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu1.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu1_dr -----

interface clkgen_mcu1_dr_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu1.clkgen_dr.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_protect";
}

interface clkgen_mcu1_dr_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu1.clkgen_dr.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_dr.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu1_io -----

interface clkgen_mcu1_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu1.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_protect";
}

interface clkgen_mcu1_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu1.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu1.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu2_cmp -----

interface clkgen_mcu2_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu2.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_protect";
}

interface clkgen_mcu2_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu2.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu2_dr -----

interface clkgen_mcu2_dr_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu2.clkgen_dr.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_protect";
}

interface clkgen_mcu2_dr_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu2.clkgen_dr.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_dr.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu2_io -----

interface clkgen_mcu2_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu2.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_protect";
}

interface clkgen_mcu2_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu2.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu2.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu3_cmp -----

interface clkgen_mcu3_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu3.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_div_ph";
  input  ccu_dr_sync_en        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_dr_sync_en";
  input  ccu_io2x_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_io2x_sync_en";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.io2x_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_protect";
}

interface clkgen_mcu3_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu3.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.cmp_slow_sync_en";
  input  dr_sync_en            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.dr_sync_en";
  input  io2x_sync_en          PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.io2x_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu3_dr -----

interface clkgen_mcu3_dr_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu3.clkgen_dr.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_protect";
}

interface clkgen_mcu3_dr_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu3.clkgen_dr.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_dr.wmr_protect";
}

//----- VERA interfaces for clkgen_mcu3_io -----

interface clkgen_mcu3_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.mcu3.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_protect";
}

interface clkgen_mcu3_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.mcu3.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.mcu3.clkgen_io.wmr_protect";
}

// added this:
#ifndef FC_NO_PEU_VERA
#ifndef PEU_SYSTEMC_T2
//----- VERA interfaces for clkgen_peu_io -----

interface clkgen_peu_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.peu.peu_iol2clk_gen.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_protect";
}

interface clkgen_peu_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.peu.peu_iol2clk_gen.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.peu.peu_iol2clk_gen.wmr_protect";
}

//----- VERA interfaces for clkgen_peu_pc -----

interface clkgen_peu_pc_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.peu.peu_pcl2clk_gen.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.bclk";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.ccu_div_ph";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.cluster_div_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_out";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_clk_stop";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_protect";
  input  pc_clk                PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pc_clk";
  input  pc_clk_sel            PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pc_clk_sel";
  input  test_clk              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.test_clk";
  input  test_clk_sel          PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.test_clk_sel";
}

interface clkgen_peu_pc_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.peu.peu_pcl2clk_gen.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.bclk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.scan_out";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.peu.peu_pcl2clk_gen.wmr_protect";
}
#endif
#endif

#ifndef FC_NO_NIU_T2
#ifndef NIU_SYSTEMC_T2
//----- VERA interfaces for clkgen_rdp_io -----

interface clkgen_rdp_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_protect";
}

interface clkgen_rdp_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io.clkgen_rdp_io.wmr_protect";
}

//----- VERA interfaces for clkgen_rdp_io2x -----

interface clkgen_rdp_io2x_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_protect";
}

interface clkgen_rdp_io2x_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rdp.rdp_clkgen_rdp_io2x.clkgen_rdp_io2x.wmr_protect";
}

//----- VERA interfaces for clkgen_rtx_io -----

interface clkgen_rtx_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_protect";
}

interface clkgen_rtx_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen_rtx.clkgen_rtx_io.wmr_protect";
}

//----- VERA interfaces for clkgen_rtx_io2x -----

interface clkgen_rtx_io2x_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.rtx.clkgen2x_rtx.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_protect";
}

interface clkgen_rtx_io2x_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.rtx.clkgen2x_rtx.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.rtx.clkgen2x_rtx.wmr_protect";
}
#endif
#endif

//----- VERA interfaces for clkgen_sii_cmp -----

interface clkgen_sii_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.sii.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_protect";
}

interface clkgen_sii_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.sii.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_sii_io -----

interface clkgen_sii_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.sii.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_protect";
}

interface clkgen_sii_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.sii.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sii.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_sio_cmp -----

interface clkgen_sio_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.sio.clkgen_cmp.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_protect";
}

interface clkgen_sio_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.sio.clkgen_cmp.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_cmp.wmr_protect";
}

//----- VERA interfaces for clkgen_sio_io -----

interface clkgen_sio_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.sio.clkgen_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_protect";
}

interface clkgen_sio_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.sio.clkgen_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.sio.clkgen_io.wmr_protect";
}

//----- VERA interfaces for clkgen_spc0_cmp -----

#ifndef RTL_NO_SPC0

interface clkgen_spc0_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc0.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_protect";
}

interface clkgen_spc0_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc0.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc0.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc1_cmp -----

#ifndef RTL_NO_SPC1

interface clkgen_spc1_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc1.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_protect";
}

interface clkgen_spc1_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc1.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc1.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc2_cmp -----

#ifndef RTL_NO_SPC2

interface clkgen_spc2_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc2.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_protect";
}

interface clkgen_spc2_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc2.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc2.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc3_cmp -----

#ifndef RTL_NO_SPC3

interface clkgen_spc3_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc3.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_protect";
}

interface clkgen_spc3_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc3.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc3.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc4_cmp -----

#ifndef RTL_NO_SPC4

interface clkgen_spc4_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc4.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_protect";
}

interface clkgen_spc4_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc4.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc4.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc5_cmp -----

#ifndef RTL_NO_SPC5

interface clkgen_spc5_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc5.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_protect";
}

interface clkgen_spc5_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc5.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc5.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc6_cmp -----

#ifndef RTL_NO_SPC6

interface clkgen_spc6_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc6.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_protect";
}

interface clkgen_spc6_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc6.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc6.clk_spc.wmr_protect";
}

#endif

//----- VERA interfaces for clkgen_spc7_cmp -----

#ifndef RTL_NO_SPC7

interface clkgen_spc7_cmp_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.spc7.clk_spc.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_protect";
}

interface clkgen_spc7_cmp_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.spc7.clk_spc.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.spc7.clk_spc.wmr_protect";
}

#endif

#ifndef FC_NO_NIU_T2
#ifndef NIU_SYSTEMC_T2
//----- VERA interfaces for clkgen_tds_io -----

interface clkgen_tds_io_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_protect";
}

interface clkgen_tds_io_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tds.clkgen_tds.clkgen_tds_io.wmr_protect";
}

//----- VERA interfaces for clkgen_tds_io2x -----

interface clkgen_tds_io2x_gclk_if {
  input  gclk  CLOCK verilog_node "`CPU.tds.clkgen2x_tds.gclk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.bclk";
  input  ccu_cmp_slow_sync_en  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_cmp_slow_sync_en";
  input  ccu_div_ph            PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_div_ph";
  input  ccu_serdes_dtm        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_serdes_dtm";
  input  ccu_slow_cmp_sync_en  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.ccu_slow_cmp_sync_en";
  input  clk_ext               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.clk_ext";
  input  cluster_arst_l        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cluster_arst_l";
  input  cluster_div_en        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cluster_div_en";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cmp_slow_sync_en";
  input  l2clk                 PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.l2clk";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.por_";
  input  rst_por_              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_por_";
  input  rst_wmr_              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_wmr_";
  input  rst_wmr_protect       PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.rst_wmr_protect";
  input  scan_en               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_en";
  input  scan_in               PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_in";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.slow_cmp_sync_en";
  input  tcu_aclk              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_aclk";
  input  tcu_atpg_mode         PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_atpg_mode";
  input  tcu_bclk              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_bclk";
  input  tcu_clk_stop          PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_clk_stop";
  input  tcu_div_bypass        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_div_bypass";
  input  tcu_pce_ov            PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_pce_ov";
  input  tcu_wr_inhibit        PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.tcu_wr_inhibit";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_protect";
}

interface clkgen_tds_io2x_l2clk_if {
  input  l2clk  CLOCK verilog_node "`CPU.tds.clkgen2x_tds.l2clk";  // Vera interface clock

  input  aclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk";
  input  aclk_wmr              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.aclk_wmr";
  input  array_wr_inhibit      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.array_wr_inhibit";
  input  bclk                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.bclk";
  input  cmp_slow_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.cmp_slow_sync_en";
  input  pce_ov                PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.pce_ov";
  input  por_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.por_";
  input  scan_out              PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.scan_out";
  input  slow_cmp_sync_en      PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.slow_cmp_sync_en";
  input  wmr_                  PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_";
  input  wmr_protect           PSAMPLE #-1 verilog_node "`CPU.tds.clkgen2x_tds.wmr_protect";
}
#endif
#endif

#endif // #ifdef FC_BENCH
#endif // #ifndef INC_CLUSTER_HDR_IF_VRI