// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ncu_defines.vri
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// ========== Copyright Header End ============================================
#ifndef INC_NCU_DEFINES_VRI      
#define INC_NCU_DEFINES_VRI

//------------------ Address Space (MSB 8-bits of Physical Address) ---------------------
#define NCU_PA                         8'h80
#define NIU_PA                         8'h81
// RESERVED                            8'h82
#define CCU_PA                         8'h83 // RNG+CCU
#define MCU_PA                         8'h84
// RESERVED                            8'h85
// RESERVED                            8'h86
// RESERVED                            8'h87
#define DMU_PA                         8'h88
#define RST_PA                         8'h89
#define ASI_PA                         8'h90 // CPU Shared Registers
#define SSI_PA                         8'hff // Boot ROM

//------------------ NCU Access Field ---------------------
#define NCU_CSR                         16'h0000
#define NCU_ASI_CMP                     16'h0104 // Multi-core access via ASI
#define NCU_ASI_INT                     16'h01cc // Interrupt access via ASI
#define NCU_ASI_RST                     16'h0000
#define NCU_ASI_CCU                     16'h0000

//------------------ NCU ASI registers (from NCU) ---------------------
#define NCU_ASI_CORE_AVAILABLE          16'h0000
#define NCU_ASI_CORE_ENABLE_STATUS      16'h0010 // CMP spec calls this ASI_CORE_ENABLED
#define NCU_ASI_CORE_ENABLE             16'h0020
#define NCU_ASI_XIR_STEERING            16'h0030
#define NCU_ASI_CORE_RUNNING_RW         16'h0050
#define NCU_ASI_CORE_RUNNING_STATUS     16'h0058
#define NCU_ASI_CORE_RUNNING_W1S        16'h0060
#define NCU_ASI_CORE_RUNNING_W1C        16'h0068
#define NCU_ASI_INT_VEC_DISP            16'h0800 // Design intends to support interrupt via TAP

//------------------ Local NCU CSR (from NCU) ---------------------
#define NCU_CSR_INT_MAN                 16'h0000
#define NCU_CSR_MONDO_INT_VEC           16'h0a00
#define NCU_CSR_SER_NUM                 16'h1000
#define NCU_CSR_EFU_STAT                16'h1008
#define NCU_CSR_CORE_AVAIL              16'h1010
#define NCU_CSR_BANK_AVAIL              16'h1018
#define NCU_CSR_BANK_ENABLE             16'h1020
#define NCU_CSR_BANK_ENABLE_STATUS      16'h1028
#define NCU_CSR_L2_IDX_HASH_EN          16'h1030
#define NCU_CSR_L2_IDX_HASH_EN_STATUS   16'h1038

//------------------ NCU Addresses ---------------------
#define NCU_INT_MAN_REG                     {NCU_PA,NCU_CSR,NCU_CSR_INT_MAN}
#define NCU_MONDO_INT_VEC_REG               {NCU_PA,NCU_CSR,NCU_CSR_MONDO_INT_VEC}
#define NCU_SER_NUM_REG                     {NCU_PA,NCU_CSR,NCU_CSR_SER_NUM}
#define NCU_EFU_STAT_REG                    {NCU_PA,NCU_CSR,NCU_CSR_EFU_STAT}
#define NCU_CORE_AVAIL_REG                  {NCU_PA,NCU_CSR,NCU_CSR_CORE_AVAIL}
#define NCU_BANK_AVAIL_REG                  {NCU_PA,NCU_CSR,NCU_CSR_BANK_AVAIL}
#define NCU_BANK_ENABLE_REG                 {NCU_PA,NCU_CSR,NCU_CSR_BANK_ENABLE}
#define NCU_BANK_ENABLE_STATUS_REG          {NCU_PA,NCU_CSR,NCU_CSR_BANK_ENABLE_STATUS}
#define NCU_L2_IDX_HASH_EN_REG              {NCU_PA,NCU_CSR,NCU_CSR_L2_IDX_HASH_EN}
#define NCU_L2_IDX_HASH_EN_STATUS_REG       {NCU_PA,NCU_CSR,NCU_CSR_L2_IDX_HASH_EN_STATUS}
#define NCU_ASI_CORE_AVAILABLE_REG          {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_AVAILABLE}
#define NCU_ASI_CORE_ENABLE_STATUS_REG      {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_ENABLE_STATUS}
#define NCU_ASI_CORE_ENABLE_REG             {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_ENABLE}
#define NCU_ASI_XIR_STEERING_REG            {ASI_PA,NCU_ASI_CMP,NCU_ASI_XIR_STEERING}
#define NCU_ASI_CORE_RUNNING_RW_REG         {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_RW}
#define NCU_ASI_CORE_RUNNING_STATUS_REG     {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_STATUS}
#define NCU_ASI_CORE_RUNNING_W1S_REG        {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_W1S}
#define NCU_ASI_CORE_RUNNING_W1C_REG        {ASI_PA,NCU_ASI_CMP,NCU_ASI_CORE_RUNNING_W1C}
#define NCU_ASI_INT_VEC_DISP_REG            {ASI_PA,NCU_ASI_INT,NCU_ASI_INT_VEC_DISP}

#endif INC_NCU_DEFINES_VRI