// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: rst_defines.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef INC_RST_DEFINES_VRI #define INC_RST_DEFINES_VRI #include "ncu_defines.vri" //------------------ RST ASI Registers --------------------- #define RST_ASI_RESET_GEN 16'h0808 #define RST_ASI_RESET_STAT 16'h0810 #define RST_ASI_RESET_SOURCE 16'h0818 // N2 PRM 08/11/2004 #define RST_ASI_RESET_SSYS 16'h0838 #define RST_ASI_LOCK_TIME 16'h0870 #define RST_ASI_PROP_TIME 16'h0880 // Added as per changed RST spec 1.06 #define RST_ASI_NIU_TIME 16'h0890 #define RST_ASI_CCU_TIME 16'h0860 #define RST_ASI_RESET_FEE 16'h0820 // Added as per changed RST spec 1.14 //------------------ RST Addresses --------------------- #define RST_ASI_RESET_GEN_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_GEN} #define RST_ASI_RESET_STAT_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_STAT} #define RST_ASI_RESET_SOURCE_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_SOURCE} #define RST_ASI_RESET_SSYS_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_SSYS} #define RST_ASI_LOCK_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_LOCK_TIME} #define RST_ASI_NIU_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_NIU_TIME} #define RST_ASI_CCU_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_CCU_TIME} #define RST_ASI_PROP_TIME_REG {RST_PA,NCU_ASI_RST,RST_ASI_PROP_TIME} // Added as per changed RST spec 1.06 #define RST_ASI_RESET_FEE_REG {RST_PA,NCU_ASI_RST,RST_ASI_RESET_FEE} // Added as per changed RST spec 1.14 //------------------ Deterministic reset wait times --------------------- #define RST_LOCK_INITIAL 16'd5120 // Test files use this (RST spec v0.9) #define RST_LOCK_COLD 0 #define RST_LOCK_WARM 1 #define RST_LOCK_ATTRIB_COUNT 2 #define RST_LOCK_POR_TCU 0 // Allow scan enable to reach destination #define RST_LOCK_BIST_TCU 1 #define RST_LOCK_BIST_RST 2 // Allow scan enable to reach destination #define RST_LOCK_ATTRIB_FIELD_COUNT 3 #define RST_LOCK { { 16, 1, 1 }, { 1 , 1 , 1 } } // Cold Warm // Reset lock warm, the POR 07/22 is to make these all the same // Reset lock cold, the POR 07/22 is to make these all the same //------------------ Knob and testbench wait times --------------------- // @@UPDATE@@ Need to update for N2 #define PLL_RST_CNT_NORM 128 #define PLL_RST_CNT_FAST 32 #define PLL_RST_NS_NORM 500 #define PLL_LCK_CNT_NORM 31488 #define PLL_LCK_CNT_FAST 256 #define PLL_LCK_NS_NORM 25000 #define EFC_READ_CNT_NORM 8000 #define EFC_READ_CNT_FAST 200 #define EFC_READ_NS_NORM 40000 #define TRST_SETUP_CMP_CYCLES 16 #define PLL_RST_NS_FAST (PLL_RST_NS_NORM / (PLL_RST_CNT_NORM / PLL_RST_CNT_FAST) ) #define PLL_LCK_NS_FAST (PLL_LCK_NS_NORM / (PLL_LCK_CNT_NORM / PLL_LCK_CNT_FAST) ) #define EFC_READ_NS_FAST (EFC_READ_NS_NORM / (EFC_READ_CNT_NORM / EFC_READ_CNT_FAST)) #define NORM_PLL_RST_R_CNT 128 #define FAST_PLL_RST_R_CNT 32 #define NORM_PLL_LCK_R_CNT 31488 #define FAST_PLL_LCK_R_CNT 256 #define NORM_PLL_BYP_R_CNT 16 #define FAST_PLL_BYP_R_CNT 16 #define NORM_PLL_LCK_SEQ_R_CNT 32000 #define NORM_PLL_BYP_SEQ_R_CNT 256 #define NORM_WRM_RST_R_CNT 2000 #define FAST_WRM_RST_R_CNT 128 #define NORM_TST_RST_R_CNT 256 #define FAST_TST_RST_R_CNT 64 #define NORM_DRM_RST_J_CNT 1600 #define FAST_DRM_RST_J_CNT 100 #define CKEN_C_CNT 4000 #define NORM_PLL_RST_LCK_R_CNT (NORM_PLL_RST_R_CNT+NORM_PLL_LCK_R_CNT) #define FAST_PLL_RST_LCK_R_CNT (FAST_PLL_RST_R_CNT+FAST_PLL_LCK_R_CNT) #define NORM_PLL_RST_BYP_R_CNT (NORM_PLL_RST_R_CNT+NORM_PLL_BYP_R_CNT) #define FAST_PLL_RST_BYP_R_CNT (FAST_PLL_RST_R_CNT+FAST_PLL_BYP_R_CNT) #define FAST_PLL_LCK_SEQ_R_CNT (NORM_PLL_LCK_SEQ_R_CNT-NORM_PLL_RST_LCK_R_CNT+FAST_PLL_RST_LCK_R_CNT ) #define FAST_PLL_BYP_SEQ_R_CNT (NORM_PLL_BYP_SEQ_R_CNT-NORM_PLL_RST_BYP_R_CNT+FAST_PLL_RST_BYP_R_CNT) #ifdef TCU_SAT #define TEST_RST_SEQUENCE_TIME 36000 // Used for timeout calculation #else #define TEST_RST_SEQUENCE_TIME 36000000 // Used for timeout calculation for FC_SCAN bench #endif //#ifdef TCU_SAT //------------------ Reset state machine --------------------- #define FLUSH_POR_1 12'h001 #define DEASSERT_SE_1 12'h002 #define DEASSERT_SE_PROP_1 12'h004 #define DEASSERT_CLOCK_STOP 12'h008 #define EFU_RUN_1 12'h010 #define REASSERT_CLOCK_STOP_1 12'h020 #define BISI_RUN_1 12'h040 #define FLUSH_POR_2 12'h080 #define DEASSERT_SE_PROP_2 12'h100 #define EFU_RUN_2 12'h200 #define REASSERT_CLOCK_STOP_2 12'h400 #define POR_UNPARK_THREAD 12'h800 // N1 #define PLL_SM_WAIT_POR 0 // N1 #define PLL_SM_RST_PLL 1 // N1 #define PLL_SM_WAIT_PLL_LCK 2 // N1 #define PLL_SM_PLL_LCK 3 // N1 #define CTL_SM_WAIT_LCK 0 // N1 #define CTL_SM_STR_CLK 1 // N1 #define CTL_SM_EN_CLK 2 // N1 #define CTL_SM_WAIT_J_RST 3 // N1 #define CTL_SM_DE_DLLRST 4 // N1 #define CTL_SM_DE_GRST 5 // N1 #define CTL_SM_EFC_RD 6 // N1 #define CTL_SM_WAIT_BISTDN 7 // N1 #define CTL_SM_IDLE 8 // N1 #define CTL_SM_A_GRST 9 // N1 #define CTL_SM_A_DGRST 10 // N1 #define CTL_SM_DIS_CLK 11 // N1 #define CTL_SM_CHNG_FRQ 12 // N1 #define CTL_SM_WAIT_RST 13 //------------------ Reset Source Register --------------------- // Modified the bit structure as per RST spec 1.06 // --------------------------------------------------------- - - - - - - - // 666655555555554444444444333333333322222222221111111111000 0 0 0 0 0 0 0 // 321098765432109876543210987654321098765432109876543210987 6 5 4 3 2 1 0 // --------------------------------------------------------- - - - - - - - #define RST_ASI_RESET_SOURCE_MASK 64'b000000000000000000000000000000000000000000000000_1_1_1_1_1_1_1_1_1_1_1_1_1_0_1_1 #define RST_ASI_RESET_SOURCE_DEF 64'b000000000000000000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_1_0_0_0 //------------------ Reset Generate Register ------------------- // Modified the bit structure as per RST spec 1.06 // ------------------------------------------------------------- - - - // 6666555555555544444444443333333333222222222211111111110000000 0 0 0 // 3210987654321098765432109876543210987654321098765432109876543 2 1 0 // ------------------------------------------------------------- - - - #define RST_ASI_RESET_GEN_MASK 64'b000000000000000000000000000000000000000000000000000000000000_1_1_1_1 #define RST_ASI_RESET_GEN_DEF 64'b000000000000000000000000000000000000000000000000000000000000_0_0_0_0 //------------------ Reset Status Register --------------------- // Modified the bit structure as per RST spec 1.06 // ---------------------------------------------------- - - - ----- - - - - // 6666555555555544444444443333333333222222222211111111 1 1 0 00000 0 0 0 0 // 3210987654321098765432109876543210987654321098765432 1 0 9 87654 3 2 1 0 // ---------------------------------------------------- - - - ----- - - - - #define RST_ASI_RESET_STAT_MASK 64'b0000000000000000000000000000000000000000000000000000_1_1_1_00000_1_1_1_0 #define RST_ASI_RESET_STAT_DEF 64'b0000000000000000000000000000000000000000000000000000_0_0_0_00000_0_0_0_0 //------------------ Reset fatal error enable register ------------------- // Modified the bit structure as per RST spec 1.14 // ------------------------------------------------------------- - - - // 6666555555555544444444443333333333222222222211111111110000000 0 0 0 // 3210987654321098765432109876543210987654321098765432109876543 2 1 0 // ------------------------------------------------------------- - - - #define RST_ASI_RESET_FEE_MASK 64'b000000000000000000000000000000000000000000000000_1_1_1_1_1_1_1_1_0_0_0_0_0_0_0_0 #define RST_ASI_RESET_FEE_DEF 64'b000000000000000000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 #define RST_ASI_RESET_STAT_FREQ_S 11 #define RST_ASI_RESET_STAT_POR_S 10 #define RST_ASI_RESET_STAT_WMR_S 9 #define RST_ASI_RESET_STAT_FREQ 3 #define RST_ASI_RESET_STAT_POR 2 #define RST_ASI_RESET_STAT_WMR 1 //------------------ Reset Subsystem Register --------------------- // Modified the bit structure as per RST spec 1.06 // -------------------------------------------------------------- - - // 66665555555555444444444433333333332222222222111111111100000000 0 0 // 32109876543210987654321098765432109876543210987654321098765432 1 0 // -------------------------------------------------------------- - - #define RST_ASI_RESET_SSYS_MASK 64'b0000000000000000000000000000000000000000000000000000000000_1_0_0_0_1_1 #define RST_ASI_RESET_SSYS_DEF 64'b0000000000000000000000000000000000000000000000000000000000_0_0_0_0_0_0 #define RST_ASI_PROP_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 #define RST_ASI_PROP_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 #define RST_ASI_LOCK_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 #define RST_ASI_LOCK_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 #define RST_ASI_NIU_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 #define RST_ASI_NIU_TIME_DEF 64'b000000000000000000000000000000000000000000000000000000000000_1_0_1_0 #define RST_ASI_CCU_TIME_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111 #define RST_ASI_CCU_TIME_DEF 64'b0000000000000000000000000000000000000000000000000000000000_1_0_0_0_0_0 #endif INC_RST_DEFINES_VRI