// -*- vera -*-

#ifndef INC_TCU_IF_VRI
#define INC_TCU_IF_VRI

#include "top_defines.vrh"

interface jtag {
  input   TCK                 CLOCK                      verilog_node "`TOP.tck";  
  input   TDO                 INPUT_EDGE INPUT_SKEW      verilog_node "`TOP.TDO";
  output  TEST_MODE           OUTPUT_EDGE OUTPUT_SKEW    verilog_node "`TOP.TEST_MODE";
  output  TDI                 OUTPUT_EDGE OUTPUT_SKEW    verilog_node "`TOP.TDI";
  output  TMS                 OUTPUT_EDGE OUTPUT_SKEW    verilog_node "`TOP.TMS";
  output  TRST_L              OUTPUT_EDGE OUTPUT_SKEW    verilog_node "`TOP.TRST_L";
}

interface bscan {
  input  TCK     	      CLOCK                      verilog_node "`TOP.tck" ;
  input  bs_scan_en           INPUT_EDGE INPUT_SKEW      verilog_node "`TCU.bs_scan_en" ;
  input  bs_clk               INPUT_EDGE INPUT_SKEW      verilog_node "`TCU.bs_clk" ;
  input  bs_aclk              INPUT_EDGE INPUT_SKEW      verilog_node "`TCU.bs_aclk" ;
  input  bs_bclk              INPUT_EDGE INPUT_SKEW      verilog_node "`TCU.bs_bclk" ;
  input  bs_uclk              INPUT_EDGE INPUT_SKEW      verilog_node "`TCU.bs_uclk" ;
}

interface mbist {
  input  TCK     	          CLOCK                   verilog_node "`TOP.tck";
  input  [65:0] mbist_bypass      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.mbist_bypass";
  input  mbist_parallel           INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.mbist_parallel";
  input  mbist_diag               INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.mbist_diag";
  input  mbist_start              INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.mbist_start"; // @@UPDATE@@
  input  tcu_spc0_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc0_mb_scan_en";
  input  tcu_spc1_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc1_mb_scan_en";
  input  tcu_spc2_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc2_mb_scan_en";
  input  tcu_spc3_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc3_mb_scan_en";
  input  tcu_spc4_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc4_mb_scan_en";
  input  tcu_spc5_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc5_mb_scan_en";
  input  tcu_spc6_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc6_mb_scan_en";
  input  tcu_spc7_mb_scan_en      INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc7_mb_scan_en";
  input  [23:0] tcu_spc_mb_start  INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_spc_mb_start";
  input  tcu_mbist_bisi_en        INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_mbist_bisi_en";
  output [65:0] mb_tcu_done       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.mb_tcu_done";
  output [65:0] mb_tcu_fail       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.mb_tcu_fail";
}

interface scan {
  input   TCK                     CLOCK                  verilog_node "`TOP.tck";  // Using pos/neg edge for AB clock
  input   tcu_scan_en             INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_scan_en";
  input   tcu_srdes_scancfg       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_srdes_scancfg";
  input   tcu_aclk                INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_aclk"; // For scan flush check
  input   tcu_bclk                INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_bclk"; // For scan flush check
  input   tcu_scan_cclk           INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_scan_cclk";
  input   tcu_pllbypass           INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_pllbypass";
  input   tcu_pce_ov              INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_pce_ov";
  input   [31:0] SCAN_OUT         INPUT_EDGE INPUT_SKEW  verilog_node "`TOP.SCAN_OUT";
  input   [2:0] tcu_spc0_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc0_scan_out";
  input   [2:0] tcu_spc1_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc1_scan_out";
  input   [2:0] tcu_spc2_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc2_scan_out";
  input   [2:0] tcu_spc3_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc3_scan_out";
  input   [2:0] tcu_spc4_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc4_scan_out";
  input   [2:0] tcu_spc5_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc5_scan_out";
  input   [2:0] tcu_spc6_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc6_scan_out";
  input   [2:0] tcu_spc7_scan_out INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_spc7_scan_out";
  input   tcu_soc0_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc0_scan_out";
  input   tcu_soc1_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc1_scan_out";
  input   tcu_soc2_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc2_scan_out";
  input   tcu_soc3_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc3_scan_out";
  input   tcu_soc4_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc4_scan_out";
  input   tcu_soc5_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc5_scan_out";
  input   tcu_soc6_scan_out       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_soc6_scan_out";
  input   tcu_srdes_scan_out      INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_srdes_scan_out";  
  input   tcu_se_scancollar_in    INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_se_scancollar_in";
  input   tcu_se_scancollar_out   INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_se_scancollar_out";
  input   tcu_array_wr_inhibit    INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_array_wr_inhibit";
  input   tcu_array_bypass        INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_array_bypass";
  input   tcu_dectest             INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_dectest";
  input   tcu_muxtest             INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_muxtest";

  output  AC_TEST_MODE           OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.AC_TEST_MODE";
  output  SCAN_EN                OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SCAN_EN";
  output  [31:0] SCAN_IN         OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SCAN_IN";
  output  SRDES_SCANCFG          OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.SRDES_SCANCFG";
  output  [2:0] spc0_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc0_tcu_scan_in";
  output  [2:0] spc1_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc1_tcu_scan_in";
  output  [2:0] spc2_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc2_tcu_scan_in";
  output  [2:0] spc3_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc3_tcu_scan_in";
  output  [2:0] spc4_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc4_tcu_scan_in";
  output  [2:0] spc5_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc5_tcu_scan_in";
  output  [2:0] spc6_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc6_tcu_scan_in";
  output  [2:0] spc7_tcu_scan_in OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.spc7_tcu_scan_in";
  output  soc0_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc0_tcu_scan_in";
  output  soc1_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc1_tcu_scan_in";
  output  soc2_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc2_tcu_scan_in";
  output  soc3_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc3_tcu_scan_in";
  output  soc4_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc4_tcu_scan_in";
  output  soc5_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc5_tcu_scan_in";
  output  soc6_tcu_scan_in       OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.soc6_tcu_scan_in";
  output  srdes_tcu_scan_in      OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TCU.srdes_tcu_scan_in";

}

interface efuse {
  input TCK                     CLOCK                  verilog_node "`TOP.tck";  
  input [6:0] tcu_efu_rowaddr   INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_rowaddr";
  input [4:0] tcu_efu_coladdr   INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_coladdr";
  input tcu_efu_read_en         INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_read_en";
  input [2:0] tcu_efu_read_mode INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_read_mode";
  input tcu_efu_read_start      INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_read_start";
  input tcu_efu_fuse_bypass     INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_fuse_bypass";
  input tcu_efu_dest_sample     INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_dest_sample";
  input tcu_efu_updatedr        INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_updatedr";
  input tcu_efu_shiftdr         INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_shiftdr";
  input tcu_efu_capturedr       INPUT_EDGE INPUT_SKEW  verilog_node "`TCU.tcu_efu_capturedr";
}

interface tcu_siu {
  input  CLK                  CLOCK                     verilog_node "`TOP.top_l2clk";
  input  tcu_sii_data         INPUT_EDGE INPUT_SKEW     verilog_node "`TCU.tcu_sii_data";
  input  tcu_sii_vld          INPUT_EDGE INPUT_SKEW     verilog_node "`TCU.tcu_sii_vld";
  output sio_tcu_data         OUTPUT_EDGE OUTPUT_SKEW   verilog_node "`TCU.sio_tcu_data";
  output sio_tcu_vld          OUTPUT_EDGE OUTPUT_SKEW   verilog_node "`TCU.sio_tcu_vld";  
}

interface clk_stop {
  input  CLK                  CLOCK                    verilog_node "`TOP.top_l2clk";
  input  tcu_spc0_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc0_clk_stop";
  input  tcu_spc1_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc1_clk_stop";
  input  tcu_spc2_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc2_clk_stop";
  input  tcu_spc3_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc3_clk_stop";
  input  tcu_spc4_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc4_clk_stop";
  input  tcu_spc5_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc5_clk_stop";
  input  tcu_spc6_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc6_clk_stop";
  input  tcu_spc7_clk_stop    INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc7_clk_stop";
  input  tcu_soc0cmp_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc0cmp_clk_stop";
  input  tcu_soc1cmp_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc1cmp_clk_stop";
  input  tcu_soc2cmp_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc2cmp_clk_stop";
  input  tcu_soc3cmp_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc3cmp_clk_stop";
  input  tcu_soc4cmp_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc4cmp_clk_stop";
  input  tcu_soc5ddr_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc5ddr_clk_stop";
  input  tcu_soc6io_clk_stop  INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc6io_clk_stop";
  input  tcu_soc7pc_clk_stop  INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc7pc_clk_stop";
  input  tcu_soc8en_clk_stop  INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_soc8en_clk_stop";
  input  tcu_spc0_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc0_mb_clk_stop";
  input  tcu_spc1_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc1_mb_clk_stop";
  input  tcu_spc2_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc2_mb_clk_stop";
  input  tcu_spc3_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc3_mb_clk_stop";
  input  tcu_spc4_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc4_mb_clk_stop";
  input  tcu_spc5_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc5_mb_clk_stop";
  input  tcu_spc6_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc6_mb_clk_stop";
  input  tcu_spc7_mb_clk_stop INPUT_EDGE INPUT_SKEW    verilog_node "`TCU.tcu_spc7_mb_clk_stop";

  // @@UPDATE@@ Move these to the correct clock domain and interface
  input   rst_tcu_flush_req      INPUT_EDGE INPUT_SKEW   verilog_node "`RST.rst_tcu_flush_req";
  //  output  tcu_rst_flush_done     OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.tcu_rst_flush_done"; // @@UPDATE@@ Remove when RST/TCU
  input   tcu_rst_flush_done     INPUT_EDGE INPUT_SKEW   verilog_node "`TCU.tcu_rst_flush_done";
  //  output  rst_tcu_flush_req      OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.rst_tcu_flush_req"; // @@UPDATE@@ Remove when RST/TCU
}
  
interface cmp_spc {
  input CLK     	         CLOCK                    verilog_node "`TOP.top_iol2clk";
.for($b=0; $b<8; $b++) {
  input core_available_${b}      INPUT_EDGE INPUT_SKEW    verilog_node "`NCU.ncu_spc${b}_core_available" ;
  input core_enable_status_${b}  INPUT_EDGE INPUT_SKEW    verilog_node "`NCU.ncu_spc${b}_core_enable_status" ;
  input core_running_${b}        INPUT_EDGE INPUT_SKEW    verilog_node "`NCU.ncu_spc${b}_core_running" ;
  input core_running_status_${b} INPUT_EDGE INPUT_SKEW    verilog_node "`NCU.spc${b}_ncu_core_running_status" ;
.}
  output [21:0] tb_fusedata_init OUTPUT_EDGE OUTPUT_SKEW  verilog_node "`MONTCU.tb_fusedata_init"; // Set core testbench core available
}



//// CLOCK is required in some global testbench files (ie: std_display_class.vr).
//// Deleting this causes the simulation to hang in std_display_class on all dispmon calls with the MON_ERR parameter
//// CLOCK below has no other purpose than this in the TCU testbench.
verilog_node CLOCK "`TOP.tck";
#endif