// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fflp_fcram_sched.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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/**********************************************************************/
/*project name:  NIU                                                  */
/*module name:   fflp_fcram_arb                                       */
/*description:   Aabitration between CPU access and flow              */
/*               classification                                       */
/*                                                                    */
/*child modules in:  none                                             */
/*interface modules:                                                  */
/*author name:       Jeanne Cai                                       */
/*date created:      16-03-2004                                       */
/*                                                                    */
/*              Copyright (c) 2004, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */
/*modifications:                                                      */
/**********************************************************************/

module fflp_fcram_sched
		(
		cclk,
		reset,
		fcram_lookup_ratio,
		cpu_fcram_req_sync,
		fc_fifo_empty_sync,
		fc_fifo_fc_lookup,
		srch_burst_done,
		cpu_burst_done_sm,

		srch_no_fc_done,
		fwd_sched,
		do_srch_cycle,
		do_cpu_cycle,
		fc_fifo_ren
		);

input		cclk;
input		reset;
input[3:0]	fcram_lookup_ratio;
input		cpu_fcram_req_sync;
input		fc_fifo_empty_sync;
input		fc_fifo_fc_lookup;
input		srch_burst_done;
input		cpu_burst_done_sm;

output		srch_no_fc_done;
output		fwd_sched;
output		do_srch_cycle;
output		do_cpu_cycle;
output		fc_fifo_ren;


wire		fc_lookup_req;
wire		fwd_no_fc_sched_sm;
wire		srch_no_fc_done;
wire		fwd_sched;
wire		do_srch_cycle;
wire		do_cpu_cycle;



fflp_fcram_fwd_arb	fflp_fcram_fwd_arb_inst (
				.cclk			(cclk),
				.reset			(reset),
				.fc_fifo_empty_sync	(fc_fifo_empty_sync),
				.fc_fifo_fc_lookup	(fc_fifo_fc_lookup),
				.srch_burst_done	(srch_burst_done),

				.fc_lookup_req		(fc_lookup_req),
				.fwd_no_fc_sched_sm	(fwd_no_fc_sched_sm),
				.srch_no_fc_done	(srch_no_fc_done)

				);


fflp_fcram_arb		fflp_fcram_arb_inst (
				.cclk			(cclk),
				.reset			(reset),
				.fcram_lookup_ratio	(fcram_lookup_ratio),
				.fc_lookup_req		(fc_lookup_req),
				.fwd_no_fc_sched_sm	(fwd_no_fc_sched_sm),
				.cpu_fcram_req_sync	(cpu_fcram_req_sync),
				.srch_burst_done	(srch_burst_done),
				.cpu_burst_done_sm	(cpu_burst_done_sm),

				.fwd_sched		(fwd_sched),
				.do_srch_cycle		(do_srch_cycle),
				.do_cpu_cycle		(do_cpu_cycle),
				.fc_fifo_ren		(fc_fifo_ren)
				
				);


endmodule