// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_peu_dp_256x138s_cust_array.v
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module n2_peu_dp_256x138s_cust_array	(

   wr_addr_array,
   wr_en_array,
   din_array, 

   clk,
   rd_addr_array,
   rd_en_array, 
   dout_array    

);


input	  [7:0]	wr_addr_array;			// write port address in
input		wr_en_array;			// write port enable
input	[137:0] din_array;			// data in

input 		clk;				// clk 
input	  [7:0]	rd_addr_array;			// read port address in
input		rd_en_array;			// read port enable
output	[137:0] dout_array;			// data out


// ----------------------------------------------------------------------------
// Zero In Checkers
// ----------------------------------------------------------------------------
// checker to verify on accesses's that no bits are x
// 0in kndr -var rd_addr_array
// 0in kndr -var wr_addr_array
// 0in kndr -var rd_en_array
// 0in kndr -var wr_en_array


reg	[137:0]	array_ram      [0:255];
reg	[137:0]	dout_array;

// Initialize the array
`ifndef NOINITMEM
integer i;

initial begin
  for (i=0; i<256; i=i+1) begin
    array_ram[i] = 138'b0;
  end
end
`endif

// ----------------------------------------------------------------------------
// Read the array
// ----------------------------------------------------------------------------
always @(clk or rd_en_array or rd_addr_array or wr_en_array or wr_addr_array ) begin
   if (clk) begin
      if (rd_en_array) begin
	 if (wr_en_array & (rd_addr_array == wr_addr_array))  // 0in < fire -severity 1 -message "Detected rd/wr collision in PEU RBUF RAM, dout driven as X's" -group mbist_mode
	    dout_array[137:0] <= {138{1'bx}} ;	
	 else
	    dout_array[137:0] <=  array_ram[rd_addr_array[7:0]];
      end
      else begin
	 dout_array[137:0] <= 138'b0 ;
      end
   end
end



// ----------------------------------------------------------------------------
// Write the array, note: it is written when the clock is low
// ----------------------------------------------------------------------------
always @(clk or wr_en_array or wr_addr_array or din_array ) begin
   if (~clk) begin
      if(wr_en_array ) begin
	  array_ram[wr_addr_array[7:0]] <= din_array[137:0];
      end
   end
end


endmodule	// n2_peu_dp_256x138s_cust_array