#ifndef THR_0_PARTID #define THR_0_PARTID 0 #endif #ifndef THR_1_PARTID #define THR_1_PARTID 0 #endif #ifndef THR_2_PARTID #define THR_2_PARTID 0 #endif #ifndef THR_3_PARTID #define THR_3_PARTID 0 #endif #ifndef THR_4_PARTID #define THR_4_PARTID 0 #endif #ifndef THR_5_PARTID #define THR_5_PARTID 0 #endif #ifndef THR_6_PARTID #define THR_6_PARTID 0 #endif #ifndef THR_7_PARTID #define THR_7_PARTID 0 #endif #ifndef THR_8_PARTID #define THR_8_PARTID 0 #endif #ifndef THR_9_PARTID #define THR_9_PARTID 0 #endif #ifndef THR_10_PARTID #define THR_10_PARTID 0 #endif #ifndef THR_11_PARTID #define THR_11_PARTID 0 #endif #ifndef THR_12_PARTID #define THR_12_PARTID 0 #endif #ifndef THR_13_PARTID #define THR_13_PARTID 0 #endif #ifndef THR_14_PARTID #define THR_14_PARTID 0 #endif #ifndef THR_15_PARTID #define THR_15_PARTID 0 #endif #ifndef THR_16_PARTID #define THR_16_PARTID 0 #endif #ifndef THR_17_PARTID #define THR_17_PARTID 0 #endif #ifndef THR_18_PARTID #define THR_18_PARTID 0 #endif #ifndef THR_19_PARTID #define THR_19_PARTID 0 #endif #ifndef THR_20_PARTID #define THR_20_PARTID 0 #endif #ifndef THR_21_PARTID #define THR_21_PARTID 0 #endif #ifndef THR_22_PARTID #define THR_22_PARTID 0 #endif #ifndef THR_23_PARTID #define THR_23_PARTID 0 #endif #ifndef THR_24_PARTID #define THR_24_PARTID 0 #endif #ifndef THR_25_PARTID #define THR_25_PARTID 0 #endif #ifndef THR_26_PARTID #define THR_26_PARTID 0 #endif #ifndef THR_27_PARTID #define THR_27_PARTID 0 #endif #ifndef THR_28_PARTID #define THR_28_PARTID 0 #endif #ifndef THR_29_PARTID #define THR_29_PARTID 0 #endif #ifndef THR_30_PARTID #define THR_30_PARTID 0 #endif #ifndef THR_31_PARTID #define THR_31_PARTID 0 #endif #ifndef THR_32_PARTID #define THR_32_PARTID 0 #endif #ifndef THR_33_PARTID #define THR_33_PARTID 0 #endif #ifndef THR_34_PARTID #define THR_34_PARTID 0 #endif #ifndef THR_35_PARTID #define THR_35_PARTID 0 #endif #ifndef THR_36_PARTID #define THR_36_PARTID 0 #endif #ifndef THR_37_PARTID #define THR_37_PARTID 0 #endif #ifndef THR_38_PARTID #define THR_38_PARTID 0 #endif #ifndef THR_39_PARTID #define THR_39_PARTID 0 #endif #ifndef THR_40_PARTID #define THR_40_PARTID 0 #endif #ifndef THR_41_PARTID #define THR_41_PARTID 0 #endif #ifndef THR_42_PARTID #define THR_42_PARTID 0 #endif #ifndef THR_43_PARTID #define THR_43_PARTID 0 #endif #ifndef THR_44_PARTID #define THR_44_PARTID 0 #endif #ifndef THR_45_PARTID #define THR_45_PARTID 0 #endif #ifndef THR_46_PARTID #define THR_46_PARTID 0 #endif #ifndef THR_47_PARTID #define THR_47_PARTID 0 #endif #ifndef THR_48_PARTID #define THR_48_PARTID 0 #endif #ifndef THR_49_PARTID #define THR_49_PARTID 0 #endif #ifndef THR_50_PARTID #define THR_50_PARTID 0 #endif #ifndef THR_51_PARTID #define THR_51_PARTID 0 #endif #ifndef THR_52_PARTID #define THR_52_PARTID 0 #endif #ifndef THR_53_PARTID #define THR_53_PARTID 0 #endif #ifndef THR_54_PARTID #define THR_54_PARTID 0 #endif #ifndef THR_55_PARTID #define THR_55_PARTID 0 #endif #ifndef THR_56_PARTID #define THR_56_PARTID 0 #endif #ifndef THR_57_PARTID #define THR_57_PARTID 0 #endif #ifndef THR_58_PARTID #define THR_58_PARTID 0 #endif #ifndef THR_59_PARTID #define THR_59_PARTID 0 #endif #ifndef THR_60_PARTID #define THR_60_PARTID 0 #endif #ifndef THR_61_PARTID #define THR_61_PARTID 0 #endif #ifndef THR_62_PARTID #define THR_62_PARTID 0 #endif #ifndef THR_63_PARTID #define THR_63_PARTID 0 #endif #if (THR_0_PARTID == 0) || \ (THR_1_PARTID == 0) || \ (THR_2_PARTID == 0) || \ (THR_3_PARTID == 0) || \ (THR_4_PARTID == 0) || \ (THR_5_PARTID == 0) || \ (THR_6_PARTID == 0) || \ (THR_7_PARTID == 0) || \ (THR_8_PARTID == 0) || \ (THR_9_PARTID == 0) || \ (THR_10_PARTID == 0) || \ (THR_11_PARTID == 0) || \ (THR_12_PARTID == 0) || \ (THR_13_PARTID == 0) || \ (THR_14_PARTID == 0) || \ (THR_15_PARTID == 0) || \ (THR_16_PARTID == 0) || \ (THR_17_PARTID == 0) || \ (THR_18_PARTID == 0) || \ (THR_19_PARTID == 0) || \ (THR_20_PARTID == 0) || \ (THR_21_PARTID == 0) || \ (THR_22_PARTID == 0) || \ (THR_23_PARTID == 0) || \ (THR_24_PARTID == 0) || \ (THR_25_PARTID == 0) || \ (THR_26_PARTID == 0) || \ (THR_27_PARTID == 0) || \ (THR_28_PARTID == 0) || \ (THR_29_PARTID == 0) || \ (THR_30_PARTID == 0) || \ (THR_31_PARTID == 0) || \ (THR_32_PARTID == 0) || \ (THR_33_PARTID == 0) || \ (THR_34_PARTID == 0) || \ (THR_35_PARTID == 0) || \ (THR_36_PARTID == 0) || \ (THR_37_PARTID == 0) || \ (THR_38_PARTID == 0) || \ (THR_39_PARTID == 0) || \ (THR_40_PARTID == 0) || \ (THR_41_PARTID == 0) || \ (THR_42_PARTID == 0) || \ (THR_43_PARTID == 0) || \ (THR_44_PARTID == 0) || \ (THR_45_PARTID == 0) || \ (THR_46_PARTID == 0) || \ (THR_47_PARTID == 0) || \ (THR_48_PARTID == 0) || \ (THR_49_PARTID == 0) || \ (THR_50_PARTID == 0) || \ (THR_51_PARTID == 0) || \ (THR_52_PARTID == 0) || \ (THR_53_PARTID == 0) || \ (THR_54_PARTID == 0) || \ (THR_55_PARTID == 0) || \ (THR_56_PARTID == 0) || \ (THR_57_PARTID == 0) || \ (THR_58_PARTID == 0) || \ (THR_59_PARTID == 0) || \ (THR_60_PARTID == 0) || \ (THR_61_PARTID == 0) || \ (THR_62_PARTID == 0) || \ (THR_63_PARTID == 0) #define PART_0_USED 1 define(part_0_used, 1) #endif #if (THR_0_PARTID == 1) || \ (THR_1_PARTID == 1) || \ (THR_2_PARTID == 1) || \ (THR_3_PARTID == 1) || \ (THR_4_PARTID == 1) || \ (THR_5_PARTID == 1) || \ (THR_6_PARTID == 1) || \ (THR_7_PARTID == 1) || \ (THR_8_PARTID == 1) || \ (THR_9_PARTID == 1) || \ (THR_10_PARTID == 1) || \ (THR_11_PARTID == 1) || \ (THR_12_PARTID == 1) || \ (THR_13_PARTID == 1) || \ (THR_14_PARTID == 1) || \ (THR_15_PARTID == 1) || \ (THR_16_PARTID == 1) || \ (THR_17_PARTID == 1) || \ (THR_18_PARTID == 1) || \ (THR_19_PARTID == 1) || \ (THR_20_PARTID == 1) || \ (THR_21_PARTID == 1) || \ (THR_22_PARTID == 1) || \ (THR_23_PARTID == 1) || \ (THR_24_PARTID == 1) || \ (THR_25_PARTID == 1) || \ (THR_26_PARTID == 1) || \ (THR_27_PARTID == 1) || \ (THR_28_PARTID == 1) || \ (THR_29_PARTID == 1) || \ (THR_30_PARTID == 1) || \ (THR_31_PARTID == 1) || \ (THR_32_PARTID == 1) || \ (THR_33_PARTID == 1) || \ (THR_34_PARTID == 1) || \ (THR_35_PARTID == 1) || \ (THR_36_PARTID == 1) || \ (THR_37_PARTID == 1) || \ (THR_38_PARTID == 1) || \ (THR_39_PARTID == 1) || \ (THR_40_PARTID == 1) || \ (THR_41_PARTID == 1) || \ (THR_42_PARTID == 1) || \ (THR_43_PARTID == 1) || \ (THR_44_PARTID == 1) || \ (THR_45_PARTID == 1) || \ (THR_46_PARTID == 1) || \ (THR_47_PARTID == 1) || \ (THR_48_PARTID == 1) || \ (THR_49_PARTID == 1) || \ (THR_50_PARTID == 1) || \ (THR_51_PARTID == 1) || \ (THR_52_PARTID == 1) || \ (THR_53_PARTID == 1) || \ (THR_54_PARTID == 1) || \ (THR_55_PARTID == 1) || \ (THR_56_PARTID == 1) || \ (THR_57_PARTID == 1) || \ (THR_58_PARTID == 1) || \ (THR_59_PARTID == 1) || \ (THR_60_PARTID == 1) || \ (THR_61_PARTID == 1) || \ (THR_62_PARTID == 1) || \ (THR_63_PARTID == 1) #define PART_1_USED 1 define(part_1_used, 1) #endif #if (THR_0_PARTID == 2) || \ (THR_1_PARTID == 2) || \ (THR_2_PARTID == 2) || \ (THR_3_PARTID == 2) || \ (THR_4_PARTID == 2) || \ (THR_5_PARTID == 2) || \ (THR_6_PARTID == 2) || \ (THR_7_PARTID == 2) || \ (THR_8_PARTID == 2) || \ (THR_9_PARTID == 2) || \ (THR_10_PARTID == 2) || \ (THR_11_PARTID == 2) || \ (THR_12_PARTID == 2) || \ (THR_13_PARTID == 2) || \ (THR_14_PARTID == 2) || \ (THR_15_PARTID == 2) || \ (THR_16_PARTID == 2) || \ (THR_17_PARTID == 2) || \ (THR_18_PARTID == 2) || \ (THR_19_PARTID == 2) || \ (THR_20_PARTID == 2) || \ (THR_21_PARTID == 2) || \ (THR_22_PARTID == 2) || \ (THR_23_PARTID == 2) || \ (THR_24_PARTID == 2) || \ (THR_25_PARTID == 2) || \ (THR_26_PARTID == 2) || \ (THR_27_PARTID == 2) || \ (THR_28_PARTID == 2) || \ (THR_29_PARTID == 2) || \ (THR_30_PARTID == 2) || \ (THR_31_PARTID == 2) || \ (THR_32_PARTID == 2) || \ (THR_33_PARTID == 2) || \ (THR_34_PARTID == 2) || \ (THR_35_PARTID == 2) || \ (THR_36_PARTID == 2) || \ (THR_37_PARTID == 2) || \ (THR_38_PARTID == 2) || \ (THR_39_PARTID == 2) || \ (THR_40_PARTID == 2) || \ (THR_41_PARTID == 2) || \ (THR_42_PARTID == 2) || \ (THR_43_PARTID == 2) || \ (THR_44_PARTID == 2) || \ (THR_45_PARTID == 2) || \ (THR_46_PARTID == 2) || \ (THR_47_PARTID == 2) || \ (THR_48_PARTID == 2) || \ (THR_49_PARTID == 2) || \ (THR_50_PARTID == 2) || \ (THR_51_PARTID == 2) || \ (THR_52_PARTID == 2) || \ (THR_53_PARTID == 2) || \ (THR_54_PARTID == 2) || \ (THR_55_PARTID == 2) || \ (THR_56_PARTID == 2) || \ (THR_57_PARTID == 2) || \ (THR_58_PARTID == 2) || \ (THR_59_PARTID == 2) || \ (THR_60_PARTID == 2) || \ (THR_61_PARTID == 2) || \ (THR_62_PARTID == 2) || \ (THR_63_PARTID == 2) #define PART_2_USED 1 define(part_2_used, 1) #endif #if (THR_0_PARTID == 3) || \ (THR_1_PARTID == 3) || \ (THR_2_PARTID == 3) || \ (THR_3_PARTID == 3) || \ (THR_4_PARTID == 3) || \ (THR_5_PARTID == 3) || \ (THR_6_PARTID == 3) || \ (THR_7_PARTID == 3) || \ (THR_8_PARTID == 3) || \ (THR_9_PARTID == 3) || \ (THR_10_PARTID == 3) || \ (THR_11_PARTID == 3) || \ (THR_12_PARTID == 3) || \ (THR_13_PARTID == 3) || \ (THR_14_PARTID == 3) || \ (THR_15_PARTID == 3) || \ (THR_16_PARTID == 3) || \ (THR_17_PARTID == 3) || \ (THR_18_PARTID == 3) || \ (THR_19_PARTID == 3) || \ (THR_20_PARTID == 3) || \ (THR_21_PARTID == 3) || \ (THR_22_PARTID == 3) || \ (THR_23_PARTID == 3) || \ (THR_24_PARTID == 3) || \ (THR_25_PARTID == 3) || \ (THR_26_PARTID == 3) || \ (THR_27_PARTID == 3) || \ (THR_28_PARTID == 3) || \ (THR_29_PARTID == 3) || \ (THR_30_PARTID == 3) || \ (THR_31_PARTID == 3) || \ (THR_32_PARTID == 3) || \ (THR_33_PARTID == 3) || \ (THR_34_PARTID == 3) || \ (THR_35_PARTID == 3) || \ (THR_36_PARTID == 3) || \ (THR_37_PARTID == 3) || \ (THR_38_PARTID == 3) || \ (THR_39_PARTID == 3) || \ (THR_40_PARTID == 3) || \ (THR_41_PARTID == 3) || \ (THR_42_PARTID == 3) || \ (THR_43_PARTID == 3) || \ (THR_44_PARTID == 3) || \ (THR_45_PARTID == 3) || \ (THR_46_PARTID == 3) || \ (THR_47_PARTID == 3) || \ (THR_48_PARTID == 3) || \ (THR_49_PARTID == 3) || \ (THR_50_PARTID == 3) || \ (THR_51_PARTID == 3) || \ (THR_52_PARTID == 3) || \ (THR_53_PARTID == 3) || \ (THR_54_PARTID == 3) || \ (THR_55_PARTID == 3) || \ (THR_56_PARTID == 3) || \ (THR_57_PARTID == 3) || \ (THR_58_PARTID == 3) || \ (THR_59_PARTID == 3) || \ (THR_60_PARTID == 3) || \ (THR_61_PARTID == 3) || \ (THR_62_PARTID == 3) || \ (THR_63_PARTID == 3) #define PART_3_USED 1 define(part_3_used, 1) #endif #if (THR_0_PARTID == 4) || \ (THR_1_PARTID == 4) || \ (THR_2_PARTID == 4) || \ (THR_3_PARTID == 4) || \ (THR_4_PARTID == 4) || \ (THR_5_PARTID == 4) || \ (THR_6_PARTID == 4) || \ (THR_7_PARTID == 4) || \ (THR_8_PARTID == 4) || \ (THR_9_PARTID == 4) || \ (THR_10_PARTID == 4) || \ (THR_11_PARTID == 4) || \ (THR_12_PARTID == 4) || \ (THR_13_PARTID == 4) || \ (THR_14_PARTID == 4) || \ (THR_15_PARTID == 4) || \ (THR_16_PARTID == 4) || \ (THR_17_PARTID == 4) || \ (THR_18_PARTID == 4) || \ (THR_19_PARTID == 4) || \ (THR_20_PARTID == 4) || \ (THR_21_PARTID == 4) || \ (THR_22_PARTID == 4) || \ (THR_23_PARTID == 4) || \ (THR_24_PARTID == 4) || \ (THR_25_PARTID == 4) || \ (THR_26_PARTID == 4) || \ (THR_27_PARTID == 4) || \ (THR_28_PARTID == 4) || \ (THR_29_PARTID == 4) || \ (THR_30_PARTID == 4) || \ (THR_31_PARTID == 4) || \ (THR_32_PARTID == 4) || \ (THR_33_PARTID == 4) || \ (THR_34_PARTID == 4) || \ (THR_35_PARTID == 4) || \ (THR_36_PARTID == 4) || \ (THR_37_PARTID == 4) || \ (THR_38_PARTID == 4) || \ (THR_39_PARTID == 4) || \ (THR_40_PARTID == 4) || \ (THR_41_PARTID == 4) || \ (THR_42_PARTID == 4) || \ (THR_43_PARTID == 4) || \ (THR_44_PARTID == 4) || \ (THR_45_PARTID == 4) || \ (THR_46_PARTID == 4) || \ (THR_47_PARTID == 4) || \ (THR_48_PARTID == 4) || \ (THR_49_PARTID == 4) || \ (THR_50_PARTID == 4) || \ (THR_51_PARTID == 4) || \ (THR_52_PARTID == 4) || \ (THR_53_PARTID == 4) || \ (THR_54_PARTID == 4) || \ (THR_55_PARTID == 4) || \ (THR_56_PARTID == 4) || \ (THR_57_PARTID == 4) || \ (THR_58_PARTID == 4) || \ (THR_59_PARTID == 4) || \ (THR_60_PARTID == 4) || \ (THR_61_PARTID == 4) || \ (THR_62_PARTID == 4) || \ (THR_63_PARTID == 4) #define PART_4_USED 1 define(part_4_used, 1) #endif #if (THR_0_PARTID == 5) || \ (THR_1_PARTID == 5) || \ (THR_2_PARTID == 5) || \ (THR_3_PARTID == 5) || \ (THR_4_PARTID == 5) || \ (THR_5_PARTID == 5) || \ (THR_6_PARTID == 5) || \ (THR_7_PARTID == 5) || \ (THR_8_PARTID == 5) || \ (THR_9_PARTID == 5) || \ (THR_10_PARTID == 5) || \ (THR_11_PARTID == 5) || \ (THR_12_PARTID == 5) || \ (THR_13_PARTID == 5) || \ (THR_14_PARTID == 5) || \ (THR_15_PARTID == 5) || \ (THR_16_PARTID == 5) || \ (THR_17_PARTID == 5) || \ (THR_18_PARTID == 5) || \ (THR_19_PARTID == 5) || \ (THR_20_PARTID == 5) || \ (THR_21_PARTID == 5) || \ (THR_22_PARTID == 5) || \ (THR_23_PARTID == 5) || \ (THR_24_PARTID == 5) || \ (THR_25_PARTID == 5) || \ (THR_26_PARTID == 5) || \ (THR_27_PARTID == 5) || \ (THR_28_PARTID == 5) || \ (THR_29_PARTID == 5) || \ (THR_30_PARTID == 5) || \ (THR_31_PARTID == 5) || \ (THR_32_PARTID == 5) || \ (THR_33_PARTID == 5) || \ (THR_34_PARTID == 5) || \ (THR_35_PARTID == 5) || \ (THR_36_PARTID == 5) || \ (THR_37_PARTID == 5) || \ (THR_38_PARTID == 5) || \ (THR_39_PARTID == 5) || \ (THR_40_PARTID == 5) || \ (THR_41_PARTID == 5) || \ (THR_42_PARTID == 5) || \ (THR_43_PARTID == 5) || \ (THR_44_PARTID == 5) || \ (THR_45_PARTID == 5) || \ (THR_46_PARTID == 5) || \ (THR_47_PARTID == 5) || \ (THR_48_PARTID == 5) || \ (THR_49_PARTID == 5) || \ (THR_50_PARTID == 5) || \ (THR_51_PARTID == 5) || \ (THR_52_PARTID == 5) || \ (THR_53_PARTID == 5) || \ (THR_54_PARTID == 5) || \ (THR_55_PARTID == 5) || \ (THR_56_PARTID == 5) || \ (THR_57_PARTID == 5) || \ (THR_58_PARTID == 5) || \ (THR_59_PARTID == 5) || \ (THR_60_PARTID == 5) || \ (THR_61_PARTID == 5) || \ (THR_62_PARTID == 5) || \ (THR_63_PARTID == 5) #define PART_5_USED 1 define(part_5_used, 1) #endif #if (THR_0_PARTID == 6) || \ (THR_1_PARTID == 6) || \ (THR_2_PARTID == 6) || \ (THR_3_PARTID == 6) || \ (THR_4_PARTID == 6) || \ (THR_5_PARTID == 6) || \ (THR_6_PARTID == 6) || \ (THR_7_PARTID == 6) || \ (THR_8_PARTID == 6) || \ (THR_9_PARTID == 6) || \ (THR_10_PARTID == 6) || \ (THR_11_PARTID == 6) || \ (THR_12_PARTID == 6) || \ (THR_13_PARTID == 6) || \ (THR_14_PARTID == 6) || \ (THR_15_PARTID == 6) || \ (THR_16_PARTID == 6) || \ (THR_17_PARTID == 6) || \ (THR_18_PARTID == 6) || \ (THR_19_PARTID == 6) || \ (THR_20_PARTID == 6) || \ (THR_21_PARTID == 6) || \ (THR_22_PARTID == 6) || \ (THR_23_PARTID == 6) || \ (THR_24_PARTID == 6) || \ (THR_25_PARTID == 6) || \ (THR_26_PARTID == 6) || \ (THR_27_PARTID == 6) || \ (THR_28_PARTID == 6) || \ (THR_29_PARTID == 6) || \ (THR_30_PARTID == 6) || \ (THR_31_PARTID == 6) || \ (THR_32_PARTID == 6) || \ (THR_33_PARTID == 6) || \ (THR_34_PARTID == 6) || \ (THR_35_PARTID == 6) || \ (THR_36_PARTID == 6) || \ (THR_37_PARTID == 6) || \ (THR_38_PARTID == 6) || \ (THR_39_PARTID == 6) || \ (THR_40_PARTID == 6) || \ (THR_41_PARTID == 6) || \ (THR_42_PARTID == 6) || \ (THR_43_PARTID == 6) || \ (THR_44_PARTID == 6) || \ (THR_45_PARTID == 6) || \ (THR_46_PARTID == 6) || \ (THR_47_PARTID == 6) || \ (THR_48_PARTID == 6) || \ (THR_49_PARTID == 6) || \ (THR_50_PARTID == 6) || \ (THR_51_PARTID == 6) || \ (THR_52_PARTID == 6) || \ (THR_53_PARTID == 6) || \ (THR_54_PARTID == 6) || \ (THR_55_PARTID == 6) || \ (THR_56_PARTID == 6) || \ (THR_57_PARTID == 6) || \ (THR_58_PARTID == 6) || \ (THR_59_PARTID == 6) || \ (THR_60_PARTID == 6) || \ (THR_61_PARTID == 6) || \ (THR_62_PARTID == 6) || \ (THR_63_PARTID == 6) #define PART_6_USED 1 define(part_6_used, 1) #endif #if (THR_0_PARTID == 7) || \ (THR_1_PARTID == 7) || \ (THR_2_PARTID == 7) || \ (THR_3_PARTID == 7) || \ (THR_4_PARTID == 7) || \ (THR_5_PARTID == 7) || \ (THR_6_PARTID == 7) || \ (THR_7_PARTID == 7) || \ (THR_8_PARTID == 7) || \ (THR_9_PARTID == 7) || \ (THR_10_PARTID == 7) || \ (THR_11_PARTID == 7) || \ (THR_12_PARTID == 7) || \ (THR_13_PARTID == 7) || \ (THR_14_PARTID == 7) || \ (THR_15_PARTID == 7) || \ (THR_16_PARTID == 7) || \ (THR_17_PARTID == 7) || \ (THR_18_PARTID == 7) || \ (THR_19_PARTID == 7) || \ (THR_20_PARTID == 7) || \ (THR_21_PARTID == 7) || \ (THR_22_PARTID == 7) || \ (THR_23_PARTID == 7) || \ (THR_24_PARTID == 7) || \ (THR_25_PARTID == 7) || \ (THR_26_PARTID == 7) || \ (THR_27_PARTID == 7) || \ (THR_28_PARTID == 7) || \ (THR_29_PARTID == 7) || \ (THR_30_PARTID == 7) || \ (THR_31_PARTID == 7) || \ (THR_32_PARTID == 7) || \ (THR_33_PARTID == 7) || \ (THR_34_PARTID == 7) || \ (THR_35_PARTID == 7) || \ (THR_36_PARTID == 7) || \ (THR_37_PARTID == 7) || \ (THR_38_PARTID == 7) || \ (THR_39_PARTID == 7) || \ (THR_40_PARTID == 7) || \ (THR_41_PARTID == 7) || \ (THR_42_PARTID == 7) || \ (THR_43_PARTID == 7) || \ (THR_44_PARTID == 7) || \ (THR_45_PARTID == 7) || \ (THR_46_PARTID == 7) || \ (THR_47_PARTID == 7) || \ (THR_48_PARTID == 7) || \ (THR_49_PARTID == 7) || \ (THR_50_PARTID == 7) || \ (THR_51_PARTID == 7) || \ (THR_52_PARTID == 7) || \ (THR_53_PARTID == 7) || \ (THR_54_PARTID == 7) || \ (THR_55_PARTID == 7) || \ (THR_56_PARTID == 7) || \ (THR_57_PARTID == 7) || \ (THR_58_PARTID == 7) || \ (THR_59_PARTID == 7) || \ (THR_60_PARTID == 7) || \ (THR_61_PARTID == 7) || \ (THR_62_PARTID == 7) || \ (THR_63_PARTID == 7) #define PART_7_USED 1 define(part_7_used, 1) #endif dnl Macro for translating Thread ID to Partition ID dnl usage: tid2pid(THR_ID,PART_ID) define(tid2pid,`ifelse( $1, 0, THR_0_PARTID, $1, 1, THR_1_PARTID, $1, 2, THR_2_PARTID, $1, 3, THR_3_PARTID, $1, 4, THR_4_PARTID, $1, 5, THR_5_PARTID, $1, 6, THR_6_PARTID, $1, 7, THR_7_PARTID, $1, 8, THR_8_PARTID, $1, 9, THR_9_PARTID, $1, 10, THR_10_PARTID, $1, 11, THR_11_PARTID, $1, 12, THR_12_PARTID, $1, 13, THR_13_PARTID, $1, 14, THR_14_PARTID, $1, 15, THR_15_PARTID, $1, 16, THR_16_PARTID, $1, 17, THR_17_PARTID, $1, 18, THR_18_PARTID, $1, 19, THR_19_PARTID, $1, 20, THR_20_PARTID, $1, 21, THR_21_PARTID, $1, 22, THR_22_PARTID, $1, 23, THR_23_PARTID, $1, 24, THR_24_PARTID, $1, 25, THR_25_PARTID, $1, 26, THR_26_PARTID, $1, 27, THR_27_PARTID, $1, 28, THR_28_PARTID, $1, 29, THR_29_PARTID, $1, 30, THR_30_PARTID, $1, 31, THR_31_PARTID, $1, 32, THR_32_PARTID, $1, 33, THR_33_PARTID, $1, 34, THR_34_PARTID, $1, 35, THR_35_PARTID, $1, 36, THR_36_PARTID, $1, 37, THR_37_PARTID, $1, 38, THR_38_PARTID, $1, 39, THR_39_PARTID, $1, 40, THR_40_PARTID, $1, 41, THR_41_PARTID, $1, 42, THR_42_PARTID, $1, 43, THR_43_PARTID, $1, 44, THR_44_PARTID, $1, 45, THR_45_PARTID, $1, 46, THR_46_PARTID, $1, 47, THR_47_PARTID, $1, 48, THR_48_PARTID, $1, 49, THR_49_PARTID, $1, 50, THR_50_PARTID, $1, 51, THR_51_PARTID, $1, 52, THR_52_PARTID, $1, 53, THR_53_PARTID, $1, 54, THR_54_PARTID, $1, 55, THR_55_PARTID, $1, 56, THR_56_PARTID, $1, 57, THR_57_PARTID, $1, 58, THR_58_PARTID, $1, 59, THR_59_PARTID, $1, 60, THR_60_PARTID, $1, 61, THR_61_PARTID, $1, 62, THR_62_PARTID, $1, 63, THR_63_PARTID)') #ifndef PART_0_BASE #define PART_0_BASE 0x1000000000 #endif #ifndef PART_0_LIMIT #define PART_0_LIMIT 0x01ffffffff #endif #ifndef PART_1_BASE #define PART_1_BASE 0x1200000000 #endif #ifndef PART_1_LIMIT #define PART_1_LIMIT 0x01ffffffff #endif #ifndef PART_2_BASE #define PART_2_BASE 0x1400000000 #endif #ifndef PART_2_LIMIT #define PART_2_LIMIT 0x01ffffffff #endif #ifndef PART_3_BASE #define PART_3_BASE 0x1600000000 #endif #ifndef PART_3_LIMIT #define PART_3_LIMIT 0x01ffffffff #endif #ifndef PART_4_BASE #define PART_4_BASE 0x1800000000 #endif #ifndef PART_4_LIMIT #define PART_4_LIMIT 0x01ffffffff #endif #ifndef PART_5_BASE #define PART_5_BASE 0x1a00000000 #endif #ifndef PART_5_LIMIT #define PART_5_LIMIT 0x01ffffffff #endif #ifndef PART_6_BASE #define PART_6_BASE 0x1c00000000 #endif #ifndef PART_6_LIMIT #define PART_6_LIMIT 0x01ffffffff #endif #ifndef PART_7_BASE #define PART_7_BASE 0x1e00000000 #endif #ifndef PART_7_LIMIT #define PART_7_LIMIT 0x01ffffffff #endif dnl Macro for translating RA to PA dnl usage: ra2pa(RA,PART_ID) define(ra2pa,``0x'mpeval($1 + ifelse( $2, 0, PART_0_BASE, $2, 1, PART_1_BASE, $2, 2, PART_2_BASE, $2, 3, PART_3_BASE, $2, 4, PART_4_BASE, $2, 5, PART_5_BASE, $2, 6, PART_6_BASE, $2, 7, PART_7_BASE),16)') dnl Macro for translating RA to PA dnl Used after change quote to [ ] dnl usage: ra2pa2(RA,PART_ID) define(ra2pa2,`[0x]mpeval($1 + ifelse( $2, 0, PART_0_BASE, $2, 1, PART_1_BASE, $2, 2, PART_2_BASE, $2, 3, PART_3_BASE, $2, 4, PART_4_BASE, $2, 5, PART_5_BASE, $2, 6, PART_6_BASE, $2, 7, PART_7_BASE),16)') define(part_0_base, PART_0_BASE) define(part_1_base, PART_1_BASE) define(part_2_base, PART_2_BASE) define(part_3_base, PART_3_BASE) define(part_4_base, PART_4_BASE) define(part_5_base, PART_5_BASE) define(part_6_base, PART_6_BASE) define(part_7_base, PART_7_BASE) define(th00_part_limit, PART_0_LIMIT) #ifndef PART_0_LINK_AREA_BASE_ADDR #define PART_0_LINK_AREA_BASE_ADDR 0x41000000 #endif #ifndef PART_1_LINK_AREA_BASE_ADDR #define PART_1_LINK_AREA_BASE_ADDR 0x41100000 #endif #ifndef PART_2_LINK_AREA_BASE_ADDR #define PART_2_LINK_AREA_BASE_ADDR 0x41200000 #endif #ifndef PART_3_LINK_AREA_BASE_ADDR #define PART_3_LINK_AREA_BASE_ADDR 0x41300000 #endif #ifndef PART_4_LINK_AREA_BASE_ADDR #define PART_4_LINK_AREA_BASE_ADDR 0x41400000 #endif #ifndef PART_5_LINK_AREA_BASE_ADDR #define PART_5_LINK_AREA_BASE_ADDR 0x41500000 #endif #ifndef PART_6_LINK_AREA_BASE_ADDR #define PART_6_LINK_AREA_BASE_ADDR 0x41600000 #endif #ifndef PART_7_LINK_AREA_BASE_ADDR #define PART_7_LINK_AREA_BASE_ADDR 0x41700000 #endif #if 0 part_0_base PART_0_BASE part_1_base PART_1_BASE part_2_base PART_2_BASE part_3_base PART_3_BASE part_4_base PART_4_BASE part_5_base PART_5_BASE part_6_base PART_6_BASE part_7_base PART_7_BASE part_0_limit PART_0_LIMIT part_1_limit PART_1_LIMIT part_2_limit PART_2_LIMIT part_3_limit PART_3_LIMIT part_4_limit PART_4_LIMIT part_5_limit PART_5_LIMIT part_6_limit PART_6_LIMIT part_7_limit PART_7_LIMIT #endif dnl // If TSB_SIZE is large (>11), PARTn_Z_ADDR_n will have to be moved apart dnl // and then might encroach on MAIN_BASE_TEXT_VA, which will have to dnl // moved higher in memory too. dnl // If NOHWTW is defined then define HWTEN to 0 #ifdef NOHWTW #define PART0_Z_HWTEN_0 0 #define PART0_Z_HWTEN_1 0 #define PART0_Z_HWTEN_2 0 #define PART0_Z_HWTEN_3 0 #define PART0_NZ_HWTEN_0 0 #define PART0_NZ_HWTEN_1 0 #define PART0_NZ_HWTEN_2 0 #define PART0_NZ_HWTEN_3 0 #define PART1_Z_HWTEN_0 0 #define PART1_Z_HWTEN_1 0 #define PART1_Z_HWTEN_2 0 #define PART1_Z_HWTEN_3 0 #define PART1_NZ_HWTEN_0 0 #define PART1_NZ_HWTEN_1 0 #define PART1_NZ_HWTEN_2 0 #define PART1_NZ_HWTEN_3 0 #define PART2_Z_HWTEN_0 0 #define PART2_Z_HWTEN_1 0 #define PART2_Z_HWTEN_2 0 #define PART2_Z_HWTEN_3 0 #define PART2_NZ_HWTEN_0 0 #define PART2_NZ_HWTEN_1 0 #define PART2_NZ_HWTEN_2 0 #define PART2_NZ_HWTEN_3 0 #define PART3_Z_HWTEN_0 0 #define PART3_Z_HWTEN_1 0 #define PART3_Z_HWTEN_2 0 #define PART3_Z_HWTEN_3 0 #define PART3_NZ_HWTEN_0 0 #define PART3_NZ_HWTEN_1 0 #define PART3_NZ_HWTEN_2 0 #define PART3_NZ_HWTEN_3 0 #define PART4_Z_HWTEN_0 0 #define PART4_Z_HWTEN_1 0 #define PART4_Z_HWTEN_2 0 #define PART4_Z_HWTEN_3 0 #define PART4_NZ_HWTEN_0 0 #define PART4_NZ_HWTEN_1 0 #define PART4_NZ_HWTEN_2 0 #define PART4_NZ_HWTEN_3 0 #define PART5_Z_HWTEN_0 0 #define PART5_Z_HWTEN_1 0 #define PART5_Z_HWTEN_2 0 #define PART5_Z_HWTEN_3 0 #define PART5_NZ_HWTEN_0 0 #define PART5_NZ_HWTEN_1 0 #define PART5_NZ_HWTEN_2 0 #define PART5_NZ_HWTEN_3 0 #define PART6_Z_HWTEN_0 0 #define PART6_Z_HWTEN_1 0 #define PART6_Z_HWTEN_2 0 #define PART6_Z_HWTEN_3 0 #define PART6_NZ_HWTEN_0 0 #define PART6_NZ_HWTEN_1 0 #define PART6_NZ_HWTEN_2 0 #define PART6_NZ_HWTEN_3 0 #define PART7_Z_HWTEN_0 0 #define PART7_Z_HWTEN_1 0 #define PART7_Z_HWTEN_2 0 #define PART7_Z_HWTEN_3 0 #define PART7_NZ_HWTEN_0 0 #define PART7_NZ_HWTEN_1 0 #define PART7_NZ_HWTEN_2 0 #define PART7_NZ_HWTEN_3 0 #endif dnl 0 //////////////////////// #ifndef PART0_Z_HWTEN_0 #define PART0_Z_HWTEN_0 1 #endif #ifndef PART0_Z_USECTX0_0 #define PART0_Z_USECTX0_0 0 #endif #ifndef PART0_Z_USECTX1_0 #define PART0_Z_USECTX1_0 0 #endif #ifndef PART0_Z_RANOTPA_0 #define PART0_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART0_Z_SUN4V_0 0 #else #define PART0_Z_SUN4V_0 1 #endif #ifndef PART0_Z_ADDR_0 #define PART0_Z_ADDR_0 0x1000000 #endif #ifndef PART0_Z_TSB_SIZE_0 #define PART0_Z_TSB_SIZE_0 1 #endif #ifndef PART0_Z_PAGE_SIZE_0 #define PART0_Z_PAGE_SIZE_0 0 #endif #ifndef PART0_Z_TSB_CONFIG_0 #define PART0_Z_TSB_CONFIG_0 ((PART0_Z_HWTEN_0 << 63) | (PART0_Z_USECTX0_0 << 62) | (PART0_Z_USECTX1_0 << 61) | (PART0_Z_ADDR_0 & 0xffffffe000) | (PART0_Z_RANOTPA_0 << 8) | (PART0_Z_PAGE_SIZE_0 << 4) | (PART0_Z_TSB_SIZE_0)) #endif define(part_0_z_tsb_config_0, `0x'dnl' mpeval(PART0_Z_TSB_CONFIG_0,16))dnl #ifndef PART0_NZ_HWTEN_0 #define PART0_NZ_HWTEN_0 1 #endif #ifndef PART0_NZ_USECTX0_0 #define PART0_NZ_USECTX0_0 0 #endif #ifndef PART0_NZ_USECTX1_0 #define PART0_NZ_USECTX1_0 0 #endif #ifndef PART0_NZ_RANOTPA_0 #define PART0_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART0_NZ_SUN4V_0 0 #else #define PART0_NZ_SUN4V_0 1 #endif #ifndef PART0_NZ_ADDR_0 #define PART0_NZ_ADDR_0 0x2000000 #endif #ifndef PART0_NZ_TSB_SIZE_0 #define PART0_NZ_TSB_SIZE_0 1 #endif #ifndef PART0_NZ_PAGE_SIZE_0 #define PART0_NZ_PAGE_SIZE_0 0 #endif #ifndef PART0_NZ_TSB_CONFIG_0 #define PART0_NZ_TSB_CONFIG_0 ((PART0_NZ_HWTEN_0 << 63) | (PART0_NZ_USECTX0_0 << 62) | (PART0_NZ_USECTX1_0 << 61) | (PART0_NZ_ADDR_0 & 0xffffffe000) | (PART0_NZ_RANOTPA_0 << 8) | (PART0_NZ_PAGE_SIZE_0 << 4) | (PART0_NZ_TSB_SIZE_0)) #endif define(part_0_nz_tsb_config_0, `0x'dnl' mpeval(PART0_NZ_TSB_CONFIG_0,16))dnl #ifndef PART0_Z_HWTEN_1 #define PART0_Z_HWTEN_1 1 #endif #ifndef PART0_Z_USECTX0_1 #define PART0_Z_USECTX0_1 0 #endif #ifndef PART0_Z_USECTX1_1 #define PART0_Z_USECTX1_1 0 #endif #ifndef PART0_Z_RANOTPA_1 #define PART0_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART0_Z_SUN4V_1 0 #else #define PART0_Z_SUN4V_1 1 #endif #ifndef PART0_Z_ADDR_1 #define PART0_Z_ADDR_1 0x3000000 #endif #ifndef PART0_Z_TSB_SIZE_1 #define PART0_Z_TSB_SIZE_1 1 #endif #ifndef PART0_Z_PAGE_SIZE_1 #define PART0_Z_PAGE_SIZE_1 0 #endif #ifndef PART0_Z_TSB_CONFIG_1 #define PART0_Z_TSB_CONFIG_1 ((PART0_Z_HWTEN_1 << 63) | (PART0_Z_USECTX0_1 << 62) | (PART0_Z_USECTX1_1 << 61) | (PART0_Z_ADDR_1 & 0xffffffe000) | (PART0_Z_RANOTPA_1 << 8) | (PART0_Z_PAGE_SIZE_1 << 4) | (PART0_Z_TSB_SIZE_1)) #endif define(part_0_z_tsb_config_1, `0x'dnl' mpeval(PART0_Z_TSB_CONFIG_1,16))dnl #ifndef PART0_NZ_HWTEN_1 #define PART0_NZ_HWTEN_1 1 #endif #ifndef PART0_NZ_USECTX0_1 #define PART0_NZ_USECTX0_1 0 #endif #ifndef PART0_NZ_USECTX1_1 #define PART0_NZ_USECTX1_1 0 #endif #ifndef PART0_NZ_RANOTPA_1 #define PART0_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART0_NZ_SUN4V_1 0 #else #define PART0_NZ_SUN4V_1 1 #endif #ifndef PART0_NZ_ADDR_1 #define PART0_NZ_ADDR_1 0x4000000 #endif #ifndef PART0_NZ_TSB_SIZE_1 #define PART0_NZ_TSB_SIZE_1 1 #endif #ifndef PART0_NZ_PAGE_SIZE_1 #define PART0_NZ_PAGE_SIZE_1 0 #endif #ifndef PART0_NZ_TSB_CONFIG_1 #define PART0_NZ_TSB_CONFIG_1 ((PART0_NZ_HWTEN_1 << 63) | (PART0_NZ_USECTX0_1 << 62) | (PART0_NZ_USECTX1_1 << 61) | (PART0_NZ_ADDR_1 & 0xffffffe000) | (PART0_NZ_RANOTPA_1 << 8) | (PART0_NZ_PAGE_SIZE_1 << 4) | (PART0_NZ_TSB_SIZE_1)) #endif define(part_0_nz_tsb_config_1, `0x'dnl' mpeval(PART0_NZ_TSB_CONFIG_1,16))dnl #ifndef PART0_Z_HWTEN_2 #define PART0_Z_HWTEN_2 1 #endif #ifndef PART0_Z_USECTX0_2 #define PART0_Z_USECTX0_2 0 #endif #ifndef PART0_Z_USECTX1_2 #define PART0_Z_USECTX1_2 0 #endif #ifndef PART0_Z_RANOTPA_2 #define PART0_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART0_Z_SUN4V_2 0 #else #define PART0_Z_SUN4V_2 1 #endif #ifndef PART0_Z_ADDR_2 #define PART0_Z_ADDR_2 0x5000000 #endif #ifndef PART0_Z_TSB_SIZE_2 #define PART0_Z_TSB_SIZE_2 1 #endif #ifndef PART0_Z_PAGE_SIZE_2 #define PART0_Z_PAGE_SIZE_2 0 #endif #ifndef PART0_Z_TSB_CONFIG_2 #define PART0_Z_TSB_CONFIG_2 ((PART0_Z_HWTEN_2 << 63) | (PART0_Z_USECTX0_2 << 62) | (PART0_Z_USECTX1_2 << 61) | (PART0_Z_ADDR_2 & 0xffffffe000) | (PART0_Z_RANOTPA_2 << 8) | (PART0_Z_PAGE_SIZE_2 << 4) | (PART0_Z_TSB_SIZE_2)) #endif define(part_0_z_tsb_config_2, `0x'dnl' mpeval(PART0_Z_TSB_CONFIG_2,16))dnl #ifndef PART0_NZ_HWTEN_2 #define PART0_NZ_HWTEN_2 1 #endif #ifndef PART0_NZ_USECTX0_2 #define PART0_NZ_USECTX0_2 0 #endif #ifndef PART0_NZ_USECTX1_2 #define PART0_NZ_USECTX1_2 0 #endif #ifndef PART0_NZ_RANOTPA_2 #define PART0_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART0_NZ_SUN4V_2 0 #else #define PART0_NZ_SUN4V_2 1 #endif #ifndef PART0_NZ_ADDR_2 #define PART0_NZ_ADDR_2 0x6000000 #endif #ifndef PART0_NZ_TSB_SIZE_2 #define PART0_NZ_TSB_SIZE_2 1 #endif #ifndef PART0_NZ_PAGE_SIZE_2 #define PART0_NZ_PAGE_SIZE_2 0 #endif #ifndef PART0_NZ_TSB_CONFIG_2 #define PART0_NZ_TSB_CONFIG_2 ((PART0_NZ_HWTEN_2 << 63) | (PART0_NZ_USECTX0_2 << 62) | (PART0_NZ_USECTX1_2 << 61) | (PART0_NZ_ADDR_2 & 0xffffffe000) | (PART0_NZ_RANOTPA_2 << 8) | (PART0_NZ_PAGE_SIZE_2 << 4) | (PART0_NZ_TSB_SIZE_2)) #endif define(part_0_nz_tsb_config_2, `0x'dnl' mpeval(PART0_NZ_TSB_CONFIG_2,16))dnl #ifndef PART0_Z_HWTEN_3 #define PART0_Z_HWTEN_3 1 #endif #ifndef PART0_Z_USECTX0_3 #define PART0_Z_USECTX0_3 0 #endif #ifndef PART0_Z_USECTX1_3 #define PART0_Z_USECTX1_3 0 #endif #ifndef PART0_Z_RANOTPA_3 #define PART0_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART0_Z_SUN4V_3 0 #else #define PART0_Z_SUN4V_3 1 #endif #ifndef PART0_Z_ADDR_3 #define PART0_Z_ADDR_3 0x7000000 #endif #ifndef PART0_Z_TSB_SIZE_3 #define PART0_Z_TSB_SIZE_3 1 #endif #ifndef PART0_Z_PAGE_SIZE_3 #define PART0_Z_PAGE_SIZE_3 0 #endif #ifndef PART0_Z_TSB_CONFIG_3 #define PART0_Z_TSB_CONFIG_3 ((PART0_Z_HWTEN_3 << 63) | (PART0_Z_USECTX0_3 << 62) | (PART0_Z_USECTX1_3 << 61) | (PART0_Z_ADDR_3 & 0xffffffe000) | (PART0_Z_RANOTPA_3 << 8) | (PART0_Z_PAGE_SIZE_3 << 4) | (PART0_Z_TSB_SIZE_3)) #endif define(part_0_z_tsb_config_3, `0x'dnl' mpeval(PART0_Z_TSB_CONFIG_3,16))dnl #ifndef PART0_NZ_HWTEN_3 #define PART0_NZ_HWTEN_3 1 #endif #ifndef PART0_NZ_USECTX0_3 #define PART0_NZ_USECTX0_3 0 #endif #ifndef PART0_NZ_USECTX1_3 #define PART0_NZ_USECTX1_3 0 #endif #ifndef PART0_NZ_RANOTPA_3 #define PART0_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART0_NZ_SUN4V_3 0 #else #define PART0_NZ_SUN4V_3 1 #endif #ifndef PART0_NZ_ADDR_3 #define PART0_NZ_ADDR_3 0x8000000 #endif #ifndef PART0_NZ_TSB_SIZE_3 #define PART0_NZ_TSB_SIZE_3 1 #endif #ifndef PART0_NZ_PAGE_SIZE_3 #define PART0_NZ_PAGE_SIZE_3 0 #endif #ifndef PART0_NZ_TSB_CONFIG_3 #define PART0_NZ_TSB_CONFIG_3 ((PART0_NZ_HWTEN_3 << 63) | (PART0_NZ_USECTX0_3 << 62) | (PART0_NZ_USECTX1_3 << 61) | (PART0_NZ_ADDR_3 & 0xffffffe000) | (PART0_NZ_RANOTPA_3 << 8) | (PART0_NZ_PAGE_SIZE_3 << 4) | (PART0_NZ_TSB_SIZE_3)) #endif define(part_0_nz_tsb_config_3, `0x'dnl' mpeval(PART0_NZ_TSB_CONFIG_3,16))dnl #ifndef PART0_PHY_OFF_X_0 #define PART0_PHY_OFF_X_0 1 #endif #ifndef PART0_PHY_OFF_P_0 #define PART0_PHY_OFF_P_0 0 #endif #ifndef PART0_PHY_OFF_W_0 #define PART0_PHY_OFF_W_0 0 #endif #ifndef PART0_PHY_OFF_0 #define PART0_PHY_OFF_0 ((PART_0_BASE) | (PART0_PHY_OFF_X_1 << 12) | (PART0_PHY_OFF_P_1 << 11) | (PART0_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART0_PHY_OFF_X_1 #define PART0_PHY_OFF_X_1 1 #endif #ifndef PART0_PHY_OFF_P_1 #define PART0_PHY_OFF_P_1 0 #endif #ifndef PART0_PHY_OFF_W_1 #define PART0_PHY_OFF_W_1 0 #endif #ifndef PART0_PHY_OFF_1 #define PART0_PHY_OFF_1 ((PART_0_BASE) | (PART0_PHY_OFF_X_1 << 12) | (PART0_PHY_OFF_P_1 << 11) | (PART0_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART0_PHY_OFF_X_2 #define PART0_PHY_OFF_X_2 1 #endif #ifndef PART0_PHY_OFF_P_2 #define PART0_PHY_OFF_P_2 0 #endif #ifndef PART0_PHY_OFF_W_2 #define PART0_PHY_OFF_W_2 0 #endif #ifndef PART0_PHY_OFF_2 #define PART0_PHY_OFF_2 ((PART_0_BASE) | (PART0_PHY_OFF_X_2 << 12) | (PART0_PHY_OFF_P_2 << 11) | (PART0_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART0_PHY_OFF_X_3 #define PART0_PHY_OFF_X_3 1 #endif #ifndef PART0_PHY_OFF_P_3 #define PART0_PHY_OFF_P_3 0 #endif #ifndef PART0_PHY_OFF_W_3 #define PART0_PHY_OFF_W_3 0 #endif #ifndef PART0_PHY_OFF_3 #define PART0_PHY_OFF_3 ((PART_0_BASE) | (PART0_PHY_OFF_X_3 << 12) | (PART0_PHY_OFF_P_3 << 11) | (PART0_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 1 //////////////////////// #ifndef PART1_Z_HWTEN_0 #define PART1_Z_HWTEN_0 1 #endif #ifndef PART1_Z_USECTX0_0 #define PART1_Z_USECTX0_0 0 #endif #ifndef PART1_Z_USECTX1_0 #define PART1_Z_USECTX1_0 0 #endif #ifndef PART1_Z_RANOTPA_0 #define PART1_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART1_Z_SUN4V_0 0 #else #define PART1_Z_SUN4V_0 1 #endif #ifndef PART1_Z_ADDR_0 #define PART1_Z_ADDR_0 0x9000000 #endif #ifndef PART1_Z_TSB_SIZE_0 #define PART1_Z_TSB_SIZE_0 1 #endif #ifndef PART1_Z_PAGE_SIZE_0 #define PART1_Z_PAGE_SIZE_0 0 #endif #ifndef PART1_Z_TSB_CONFIG_0 #define PART1_Z_TSB_CONFIG_0 ((PART1_Z_HWTEN_0 << 63) | (PART1_Z_USECTX0_0 << 62) | (PART1_Z_USECTX1_0 << 61) | (PART1_Z_ADDR_0 & 0xffffffe000) | (PART1_Z_RANOTPA_0 << 8) | (PART1_Z_PAGE_SIZE_0 << 4) | (PART1_Z_TSB_SIZE_0)) #endif define(part_1_z_tsb_config_0, `0x'dnl' mpeval(PART1_Z_TSB_CONFIG_0,16))dnl #ifndef PART1_NZ_HWTEN_0 #define PART1_NZ_HWTEN_0 1 #endif #ifndef PART1_NZ_USECTX0_0 #define PART1_NZ_USECTX0_0 0 #endif #ifndef PART1_NZ_USECTX1_0 #define PART1_NZ_USECTX1_0 0 #endif #ifndef PART1_NZ_RANOTPA_0 #define PART1_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART1_NZ_SUN4V_0 0 #else #define PART1_NZ_SUN4V_0 1 #endif #ifndef PART1_NZ_ADDR_0 #define PART1_NZ_ADDR_0 0xa000000 #endif #ifndef PART1_NZ_TSB_SIZE_0 #define PART1_NZ_TSB_SIZE_0 1 #endif #ifndef PART1_NZ_PAGE_SIZE_0 #define PART1_NZ_PAGE_SIZE_0 0 #endif #ifndef PART1_NZ_TSB_CONFIG_0 #define PART1_NZ_TSB_CONFIG_0 ((PART1_NZ_HWTEN_0 << 63) | (PART1_NZ_USECTX0_0 << 62) | (PART1_NZ_USECTX1_0 << 61) | (PART1_NZ_ADDR_0 & 0xffffffe000) | (PART1_NZ_RANOTPA_0 << 8) | (PART1_NZ_PAGE_SIZE_0 << 4) | (PART1_NZ_TSB_SIZE_0)) #endif define(part_1_nz_tsb_config_0, `0x'dnl' mpeval(PART1_NZ_TSB_CONFIG_0,16))dnl #ifndef PART1_Z_HWTEN_1 #define PART1_Z_HWTEN_1 1 #endif #ifndef PART1_Z_USECTX0_1 #define PART1_Z_USECTX0_1 0 #endif #ifndef PART1_Z_USECTX1_1 #define PART1_Z_USECTX1_1 0 #endif #ifndef PART1_Z_RANOTPA_1 #define PART1_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART1_Z_SUN4V_1 0 #else #define PART1_Z_SUN4V_1 1 #endif #ifndef PART1_Z_ADDR_1 #define PART1_Z_ADDR_1 0xb000000 #endif #ifndef PART1_Z_TSB_SIZE_1 #define PART1_Z_TSB_SIZE_1 1 #endif #ifndef PART1_Z_PAGE_SIZE_1 #define PART1_Z_PAGE_SIZE_1 0 #endif #ifndef PART1_Z_TSB_CONFIG_1 #define PART1_Z_TSB_CONFIG_1 ((PART1_Z_HWTEN_1 << 63) | (PART1_Z_USECTX0_1 << 62) | (PART1_Z_USECTX1_1 << 61) | (PART1_Z_ADDR_1 & 0xffffffe000) | (PART1_Z_RANOTPA_1 << 8) | (PART1_Z_PAGE_SIZE_1 << 4) | (PART1_Z_TSB_SIZE_1)) #endif define(part_1_z_tsb_config_1, `0x'dnl' mpeval(PART1_Z_TSB_CONFIG_1,16))dnl #ifndef PART1_NZ_HWTEN_1 #define PART1_NZ_HWTEN_1 1 #endif #ifndef PART1_NZ_USECTX0_1 #define PART1_NZ_USECTX0_1 0 #endif #ifndef PART1_NZ_USECTX1_1 #define PART1_NZ_USECTX1_1 0 #endif #ifndef PART1_NZ_RANOTPA_1 #define PART1_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART1_NZ_SUN4V_1 0 #else #define PART1_NZ_SUN4V_1 1 #endif #ifndef PART1_NZ_ADDR_1 #define PART1_NZ_ADDR_1 0xc000000 #endif #ifndef PART1_NZ_TSB_SIZE_1 #define PART1_NZ_TSB_SIZE_1 1 #endif #ifndef PART1_NZ_PAGE_SIZE_1 #define PART1_NZ_PAGE_SIZE_1 0 #endif #ifndef PART1_NZ_TSB_CONFIG_1 #define PART1_NZ_TSB_CONFIG_1 ((PART1_NZ_HWTEN_1 << 63) | (PART1_NZ_USECTX0_1 << 62) | (PART1_NZ_USECTX1_1 << 61) | (PART1_NZ_ADDR_1 & 0xffffffe000) | (PART1_NZ_RANOTPA_1 << 8) | (PART1_NZ_PAGE_SIZE_1 << 4) | (PART1_NZ_TSB_SIZE_1)) #endif define(part_1_nz_tsb_config_1, `0x'dnl' mpeval(PART1_NZ_TSB_CONFIG_1,16))dnl #ifndef PART1_Z_HWTEN_2 #define PART1_Z_HWTEN_2 1 #endif #ifndef PART1_Z_USECTX0_2 #define PART1_Z_USECTX0_2 0 #endif #ifndef PART1_Z_USECTX1_2 #define PART1_Z_USECTX1_2 0 #endif #ifndef PART1_Z_RANOTPA_2 #define PART1_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART1_Z_SUN4V_2 0 #else #define PART1_Z_SUN4V_2 1 #endif #ifndef PART1_Z_ADDR_2 #define PART1_Z_ADDR_2 0xd000000 #endif #ifndef PART1_Z_TSB_SIZE_2 #define PART1_Z_TSB_SIZE_2 1 #endif #ifndef PART1_Z_PAGE_SIZE_2 #define PART1_Z_PAGE_SIZE_2 0 #endif #ifndef PART1_Z_TSB_CONFIG_2 #define PART1_Z_TSB_CONFIG_2 ((PART1_Z_HWTEN_2 << 63) | (PART1_Z_USECTX0_2 << 62) | (PART1_Z_USECTX1_2 << 61) | (PART1_Z_ADDR_2 & 0xffffffe000) | (PART1_Z_RANOTPA_2 << 8) |(PART1_Z_PAGE_SIZE_2 << 4) | (PART1_Z_TSB_SIZE_2)) #endif define(part_1_z_tsb_config_2, `0x'dnl' mpeval(PART1_Z_TSB_CONFIG_2,16))dnl #ifndef PART1_NZ_HWTEN_2 #define PART1_NZ_HWTEN_2 1 #endif #ifndef PART1_NZ_USECTX0_2 #define PART1_NZ_USECTX0_2 0 #endif #ifndef PART1_NZ_USECTX1_2 #define PART1_NZ_USECTX1_2 0 #endif #ifndef PART1_NZ_RANOTPA_2 #define PART1_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART1_NZ_SUN4V_2 0 #else #define PART1_NZ_SUN4V_2 1 #endif #ifndef PART1_NZ_ADDR_2 #define PART1_NZ_ADDR_2 0xe000000 #endif #ifndef PART1_NZ_TSB_SIZE_2 #define PART1_NZ_TSB_SIZE_2 1 #endif #ifndef PART1_NZ_PAGE_SIZE_2 #define PART1_NZ_PAGE_SIZE_2 0 #endif #ifndef PART1_NZ_TSB_CONFIG_2 #define PART1_NZ_TSB_CONFIG_2 ((PART1_NZ_HWTEN_2 << 63) | (PART1_NZ_USECTX0_2 << 62) | (PART1_NZ_USECTX1_2 << 61) | (PART1_NZ_ADDR_2 & 0xffffffe000) | (PART1_NZ_RANOTPA_2 << 8) | (PART1_NZ_PAGE_SIZE_2 << 4) | (PART1_NZ_TSB_SIZE_2)) #endif define(part_1_nz_tsb_config_2, `0x'dnl' mpeval(PART1_NZ_TSB_CONFIG_2,16))dnl #ifndef PART1_Z_HWTEN_3 #define PART1_Z_HWTEN_3 1 #endif #ifndef PART1_Z_USECTX0_3 #define PART1_Z_USECTX0_3 0 #endif #ifndef PART1_Z_USECTX1_3 #define PART1_Z_USECTX1_3 0 #endif #ifndef PART1_Z_RANOTPA_3 #define PART1_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART1_Z_SUN4V_3 0 #else #define PART1_Z_SUN4V_3 1 #endif #ifndef PART1_Z_ADDR_3 #define PART1_Z_ADDR_3 0xf000000 #endif #ifndef PART1_Z_TSB_SIZE_3 #define PART1_Z_TSB_SIZE_3 1 #endif #ifndef PART1_Z_PAGE_SIZE_3 #define PART1_Z_PAGE_SIZE_3 0 #endif #ifndef PART1_Z_TSB_CONFIG_3 #define PART1_Z_TSB_CONFIG_3 ((PART1_Z_HWTEN_3 << 63) | (PART1_Z_USECTX0_3 << 62) | (PART1_Z_USECTX1_3 << 61) | (PART1_Z_ADDR_3 & 0xffffffe000) | (PART1_Z_RANOTPA_3 << 8) | (PART1_Z_PAGE_SIZE_3 << 4) | (PART1_Z_TSB_SIZE_3)) #endif define(part_1_z_tsb_config_3, `0x'dnl' mpeval(PART1_Z_TSB_CONFIG_3,16))dnl #ifndef PART1_NZ_HWTEN_3 #define PART1_NZ_HWTEN_3 1 #endif #ifndef PART1_NZ_USECTX0_3 #define PART1_NZ_USECTX0_3 0 #endif #ifndef PART1_NZ_USECTX1_3 #define PART1_NZ_USECTX1_3 0 #endif #ifndef PART1_NZ_RANOTPA_3 #define PART1_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART1_NZ_SUN4V_3 0 #else #define PART1_NZ_SUN4V_3 1 #endif #ifndef PART1_NZ_ADDR_3 #define PART1_NZ_ADDR_3 0x10000000 #endif #ifndef PART1_NZ_TSB_SIZE_3 #define PART1_NZ_TSB_SIZE_3 1 #endif #ifndef PART1_NZ_PAGE_SIZE_3 #define PART1_NZ_PAGE_SIZE_3 0 #endif #ifndef PART1_NZ_TSB_CONFIG_3 #define PART1_NZ_TSB_CONFIG_3 ((PART1_NZ_HWTEN_3 << 63) | (PART1_NZ_USECTX0_3 << 62) | (PART1_NZ_USECTX1_3 << 61) | (PART1_NZ_ADDR_3 & 0xffffffe000) | (PART1_NZ_RANOTPA_3 << 8) | (PART1_NZ_PAGE_SIZE_3 << 4) | (PART1_NZ_TSB_SIZE_3)) #endif define(part_1_nz_tsb_config_3, `0x'dnl' mpeval(PART1_NZ_TSB_CONFIG_3,16))dnl #ifndef PART1_PHY_OFF_X_0 #define PART1_PHY_OFF_X_0 1 #endif #ifndef PART1_PHY_OFF_P_0 #define PART1_PHY_OFF_P_0 0 #endif #ifndef PART1_PHY_OFF_W_0 #define PART1_PHY_OFF_W_0 0 #endif #ifndef PART1_PHY_OFF_0 #define PART1_PHY_OFF_0 ((PART_1_BASE) | (PART1_PHY_OFF_X_1 << 12) | (PART1_PHY_OFF_P_1 << 11) | (PART1_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART1_PHY_OFF_X_1 #define PART1_PHY_OFF_X_1 1 #endif #ifndef PART1_PHY_OFF_P_1 #define PART1_PHY_OFF_P_1 0 #endif #ifndef PART1_PHY_OFF_W_1 #define PART1_PHY_OFF_W_1 0 #endif #ifndef PART1_PHY_OFF_1 #define PART1_PHY_OFF_1 ((PART_1_BASE) | (PART1_PHY_OFF_X_1 << 12) | (PART1_PHY_OFF_P_1 << 11) | (PART1_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART1_PHY_OFF_X_2 #define PART1_PHY_OFF_X_2 1 #endif #ifndef PART1_PHY_OFF_P_2 #define PART1_PHY_OFF_P_2 0 #endif #ifndef PART1_PHY_OFF_W_2 #define PART1_PHY_OFF_W_2 0 #endif #ifndef PART1_PHY_OFF_2 #define PART1_PHY_OFF_2 ((PART_1_BASE) | (PART1_PHY_OFF_X_2 << 12) | (PART1_PHY_OFF_P_2 << 11) | (PART1_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART1_PHY_OFF_X_3 #define PART1_PHY_OFF_X_3 1 #endif #ifndef PART1_PHY_OFF_P_3 #define PART1_PHY_OFF_P_3 0 #endif #ifndef PART1_PHY_OFF_W_3 #define PART1_PHY_OFF_W_3 0 #endif #ifndef PART1_PHY_OFF_3 #define PART1_PHY_OFF_3 ((PART_1_BASE) | (PART1_PHY_OFF_X_3 << 12) | (PART1_PHY_OFF_P_3 << 11) | (PART1_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 2 //////////////////////// #ifndef PART2_Z_HWTEN_0 #define PART2_Z_HWTEN_0 1 #endif #ifndef PART2_Z_USECTX0_0 #define PART2_Z_USECTX0_0 0 #endif #ifndef PART2_Z_USECTX1_0 #define PART2_Z_USECTX1_0 0 #endif #ifndef PART2_Z_RANOTPA_0 #define PART2_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART2_Z_SUN4V_0 0 #else #define PART2_Z_SUN4V_0 1 #endif #ifndef PART2_Z_ADDR_0 #define PART2_Z_ADDR_0 0x11000000 #endif #ifndef PART2_Z_TSB_SIZE_0 #define PART2_Z_TSB_SIZE_0 1 #endif #ifndef PART2_Z_PAGE_SIZE_0 #define PART2_Z_PAGE_SIZE_0 0 #endif #ifndef PART2_Z_TSB_CONFIG_0 #define PART2_Z_TSB_CONFIG_0 ((PART2_Z_HWTEN_0 << 63) | (PART2_Z_USECTX0_0 << 62) | (PART2_Z_USECTX1_0 << 61) | (PART2_Z_ADDR_0 & 0xffffffe000) | (PART2_Z_RANOTPA_0 << 8) | (PART2_Z_PAGE_SIZE_0 << 4) | (PART2_Z_TSB_SIZE_0)) #endif define(part_2_z_tsb_config_0, `0x'dnl' mpeval(PART2_Z_TSB_CONFIG_0,16))dnl #ifndef PART2_NZ_HWTEN_0 #define PART2_NZ_HWTEN_0 1 #endif #ifndef PART2_NZ_USECTX0_0 #define PART2_NZ_USECTX0_0 0 #endif #ifndef PART2_NZ_USECTX1_0 #define PART2_NZ_USECTX1_0 0 #endif #ifndef PART2_NZ_RANOTPA_0 #define PART2_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART2_NZ_SUN4V_0 0 #else #define PART2_NZ_SUN4V_0 1 #endif #ifndef PART2_NZ_ADDR_0 #define PART2_NZ_ADDR_0 0x12000000 #endif #ifndef PART2_NZ_TSB_SIZE_0 #define PART2_NZ_TSB_SIZE_0 1 #endif #ifndef PART2_NZ_PAGE_SIZE_0 #define PART2_NZ_PAGE_SIZE_0 0 #endif #ifndef PART2_NZ_TSB_CONFIG_0 #define PART2_NZ_TSB_CONFIG_0 ((PART2_NZ_HWTEN_0 << 63) | (PART2_NZ_USECTX0_0 << 62) | (PART2_NZ_USECTX1_0 << 61) | (PART2_NZ_ADDR_0 & 0xffffffe000) | (PART2_NZ_RANOTPA_0 << 8) | (PART2_NZ_PAGE_SIZE_0 << 4) | (PART2_NZ_TSB_SIZE_0)) #endif define(part_2_nz_tsb_config_0, `0x'dnl' mpeval(PART2_NZ_TSB_CONFIG_0,16))dnl #ifndef PART2_Z_HWTEN_1 #define PART2_Z_HWTEN_1 1 #endif #ifndef PART2_Z_USECTX0_1 #define PART2_Z_USECTX0_1 0 #endif #ifndef PART2_Z_USECTX1_1 #define PART2_Z_USECTX1_1 0 #endif #ifndef PART2_Z_RANOTPA_1 #define PART2_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART2_Z_SUN4V_1 0 #else #define PART2_Z_SUN4V_1 1 #endif #ifndef PART2_Z_ADDR_1 #define PART2_Z_ADDR_1 0x13000000 #endif #ifndef PART2_Z_TSB_SIZE_1 #define PART2_Z_TSB_SIZE_1 1 #endif #ifndef PART2_Z_PAGE_SIZE_1 #define PART2_Z_PAGE_SIZE_1 0 #endif #ifndef PART2_Z_TSB_CONFIG_1 #define PART2_Z_TSB_CONFIG_1 ((PART2_Z_HWTEN_1 << 63) | (PART2_Z_USECTX0_1 << 62) | (PART2_Z_USECTX1_1 << 61) | (PART2_Z_ADDR_1 & 0xffffffe000) | (PART2_Z_RANOTPA_1 << 8) | (PART2_Z_PAGE_SIZE_1 << 4) | (PART2_Z_TSB_SIZE_1)) #endif define(part_2_z_tsb_config_1, `0x'dnl' mpeval(PART2_Z_TSB_CONFIG_1,16))dnl #ifndef PART2_NZ_HWTEN_1 #define PART2_NZ_HWTEN_1 1 #endif #ifndef PART2_NZ_USECTX0_1 #define PART2_NZ_USECTX0_1 0 #endif #ifndef PART2_NZ_USECTX1_1 #define PART2_NZ_USECTX1_1 0 #endif #ifndef PART2_NZ_RANOTPA_1 #define PART2_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART2_NZ_SUN4V_1 0 #else #define PART2_NZ_SUN4V_1 1 #endif #ifndef PART2_NZ_ADDR_1 #define PART2_NZ_ADDR_1 0x14000000 #endif #ifndef PART2_NZ_TSB_SIZE_1 #define PART2_NZ_TSB_SIZE_1 1 #endif #ifndef PART2_NZ_PAGE_SIZE_1 #define PART2_NZ_PAGE_SIZE_1 0 #endif #ifndef PART2_NZ_TSB_CONFIG_1 #define PART2_NZ_TSB_CONFIG_1 ((PART2_NZ_HWTEN_1 << 63) | (PART2_NZ_USECTX0_1 << 62) | (PART2_NZ_USECTX1_1 << 61) | (PART2_NZ_ADDR_1 & 0xffffffe000) | (PART2_NZ_RANOTPA_1 << 8) | (PART2_NZ_PAGE_SIZE_1 << 4) | (PART2_NZ_TSB_SIZE_1)) #endif define(part_2_nz_tsb_config_1, `0x'dnl' mpeval(PART2_NZ_TSB_CONFIG_1,16))dnl #ifndef PART2_Z_HWTEN_2 #define PART2_Z_HWTEN_2 1 #endif #ifndef PART2_Z_USECTX0_2 #define PART2_Z_USECTX0_2 0 #endif #ifndef PART2_Z_USECTX1_2 #define PART2_Z_USECTX1_2 0 #endif #ifndef PART2_Z_RANOTPA_2 #define PART2_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART2_Z_SUN4V_2 0 #else #define PART2_Z_SUN4V_2 1 #endif #ifndef PART2_Z_ADDR_2 #define PART2_Z_ADDR_2 0x15000000 #endif #ifndef PART2_Z_TSB_SIZE_2 #define PART2_Z_TSB_SIZE_2 1 #endif #ifndef PART2_Z_PAGE_SIZE_2 #define PART2_Z_PAGE_SIZE_2 0 #endif #ifndef PART2_Z_TSB_CONFIG_2 #define PART2_Z_TSB_CONFIG_2 ((PART2_Z_HWTEN_2 << 63) | (PART2_Z_USECTX0_2 << 62) | (PART2_Z_USECTX1_2 << 61) | (PART2_Z_ADDR_2 & 0xffffffe000) | (PART2_Z_RANOTPA_2 << 8) | (PART2_Z_PAGE_SIZE_2 << 4) | (PART2_Z_TSB_SIZE_2)) #endif define(part_2_z_tsb_config_2, `0x'dnl' mpeval(PART2_Z_TSB_CONFIG_2,16))dnl #ifndef PART2_NZ_HWTEN_2 #define PART2_NZ_HWTEN_2 1 #endif #ifndef PART2_NZ_USECTX0_2 #define PART2_NZ_USECTX0_2 0 #endif #ifndef PART2_NZ_USECTX1_2 #define PART2_NZ_USECTX1_2 0 #endif #ifndef PART2_NZ_RANOTPA_2 #define PART2_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART2_NZ_SUN4V_2 0 #else #define PART2_NZ_SUN4V_2 1 #endif #ifndef PART2_NZ_ADDR_2 #define PART2_NZ_ADDR_2 0x16000000 #endif #ifndef PART2_NZ_TSB_SIZE_2 #define PART2_NZ_TSB_SIZE_2 1 #endif #ifndef PART2_NZ_PAGE_SIZE_2 #define PART2_NZ_PAGE_SIZE_2 0 #endif #ifndef PART2_NZ_TSB_CONFIG_2 #define PART2_NZ_TSB_CONFIG_2 ((PART2_NZ_HWTEN_2 << 63) | (PART2_NZ_USECTX0_2 << 62) | (PART2_NZ_USECTX1_2 << 61) | (PART2_NZ_ADDR_2 & 0xffffffe000) | (PART2_NZ_RANOTPA_2 << 8) | (PART2_NZ_PAGE_SIZE_2 << 4) | (PART2_NZ_TSB_SIZE_2)) #endif define(part_2_nz_tsb_config_2, `0x'dnl' mpeval(PART2_NZ_TSB_CONFIG_2,16))dnl #ifndef PART2_Z_HWTEN_3 #define PART2_Z_HWTEN_3 1 #endif #ifndef PART2_Z_USECTX0_3 #define PART2_Z_USECTX0_3 0 #endif #ifndef PART2_Z_USECTX1_3 #define PART2_Z_USECTX1_3 0 #endif #ifndef PART2_Z_RANOTPA_3 #define PART2_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART2_Z_SUN4V_3 0 #else #define PART2_Z_SUN4V_3 1 #endif #ifndef PART2_Z_ADDR_3 #define PART2_Z_ADDR_3 0x17000000 #endif #ifndef PART2_Z_TSB_SIZE_3 #define PART2_Z_TSB_SIZE_3 1 #endif #ifndef PART2_Z_PAGE_SIZE_3 #define PART2_Z_PAGE_SIZE_3 0 #endif #ifndef PART2_Z_TSB_CONFIG_3 #define PART2_Z_TSB_CONFIG_3 ((PART2_Z_HWTEN_3 << 63) | (PART2_Z_USECTX0_3 << 62) | (PART2_Z_USECTX1_3 << 61) | (PART2_Z_ADDR_3 & 0xffffffe000) | (PART2_Z_RANOTPA_3 << 8) | (PART2_Z_PAGE_SIZE_3 << 4) | (PART2_Z_TSB_SIZE_3)) #endif define(part_2_z_tsb_config_3, `0x'dnl' mpeval(PART2_Z_TSB_CONFIG_3,16))dnl #ifndef PART2_NZ_HWTEN_3 #define PART2_NZ_HWTEN_3 1 #endif #ifndef PART2_NZ_USECTX0_3 #define PART2_NZ_USECTX0_3 0 #endif #ifndef PART2_NZ_USECTX1_3 #define PART2_NZ_USECTX1_3 0 #endif #ifndef PART2_NZ_RANOTPA_3 #define PART2_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART2_NZ_SUN4V_3 0 #else #define PART2_NZ_SUN4V_3 1 #endif #ifndef PART2_NZ_ADDR_3 #define PART2_NZ_ADDR_3 0x18000000 #endif #ifndef PART2_NZ_TSB_SIZE_3 #define PART2_NZ_TSB_SIZE_3 1 #endif #ifndef PART2_NZ_PAGE_SIZE_3 #define PART2_NZ_PAGE_SIZE_3 0 #endif #ifndef PART2_NZ_TSB_CONFIG_3 #define PART2_NZ_TSB_CONFIG_3 ((PART2_NZ_HWTEN_3 << 63) | (PART2_NZ_USECTX0_3 << 62) | (PART2_NZ_USECTX1_3 << 61) | (PART2_NZ_ADDR_3 & 0xffffffe000) | (PART2_NZ_RANOTPA_3 << 8) | (PART2_NZ_PAGE_SIZE_3 << 4) | (PART2_NZ_TSB_SIZE_3)) #endif define(part_2_nz_tsb_config_3, `0x'dnl' mpeval(PART2_NZ_TSB_CONFIG_3,16))dnl #ifndef PART2_PHY_OFF_X_0 #define PART2_PHY_OFF_X_0 1 #endif #ifndef PART2_PHY_OFF_P_0 #define PART2_PHY_OFF_P_0 0 #endif #ifndef PART2_PHY_OFF_W_0 #define PART2_PHY_OFF_W_0 0 #endif #ifndef PART2_PHY_OFF_0 #define PART2_PHY_OFF_0 ((PART_2_BASE) | (PART2_PHY_OFF_X_1 << 12) | (PART2_PHY_OFF_P_1 << 11) | (PART2_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART2_PHY_OFF_X_1 #define PART2_PHY_OFF_X_1 1 #endif #ifndef PART2_PHY_OFF_P_1 #define PART2_PHY_OFF_P_1 0 #endif #ifndef PART2_PHY_OFF_W_1 #define PART2_PHY_OFF_W_1 0 #endif #ifndef PART2_PHY_OFF_1 #define PART2_PHY_OFF_1 ((PART_2_BASE) | (PART2_PHY_OFF_X_1 << 12) | (PART2_PHY_OFF_P_1 << 11) | (PART2_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART2_PHY_OFF_X_2 #define PART2_PHY_OFF_X_2 1 #endif #ifndef PART2_PHY_OFF_P_2 #define PART2_PHY_OFF_P_2 0 #endif #ifndef PART2_PHY_OFF_W_2 #define PART2_PHY_OFF_W_2 0 #endif #ifndef PART2_PHY_OFF_2 #define PART2_PHY_OFF_2 ((PART_2_BASE) | (PART2_PHY_OFF_X_2 << 12) | (PART2_PHY_OFF_P_2 << 11) | (PART2_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART2_PHY_OFF_X_3 #define PART2_PHY_OFF_X_3 1 #endif #ifndef PART2_PHY_OFF_P_3 #define PART2_PHY_OFF_P_3 0 #endif #ifndef PART2_PHY_OFF_W_3 #define PART2_PHY_OFF_W_3 0 #endif #ifndef PART2_PHY_OFF_3 #define PART2_PHY_OFF_3 ((PART_2_BASE) | (PART2_PHY_OFF_X_3 << 12) | (PART2_PHY_OFF_P_3 << 11) | (PART2_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 3 //////////////////////// #ifndef PART3_Z_HWTEN_0 #define PART3_Z_HWTEN_0 1 #endif #ifndef PART3_Z_USECTX0_0 #define PART3_Z_USECTX0_0 0 #endif #ifndef PART3_Z_USECTX1_0 #define PART3_Z_USECTX1_0 0 #endif #ifndef PART3_Z_RANOTPA_0 #define PART3_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART3_Z_SUN4V_0 0 #else #define PART3_Z_SUN4V_0 1 #endif #ifndef PART3_Z_ADDR_0 #define PART3_Z_ADDR_0 0x19000000 #endif #ifndef PART3_Z_TSB_SIZE_0 #define PART3_Z_TSB_SIZE_0 1 #endif #ifndef PART3_Z_PAGE_SIZE_0 #define PART3_Z_PAGE_SIZE_0 0 #endif #ifndef PART3_Z_TSB_CONFIG_0 #define PART3_Z_TSB_CONFIG_0 ((PART3_Z_HWTEN_0 << 63) | (PART3_Z_USECTX0_0 << 62) | (PART3_Z_USECTX1_0 << 61) | (PART3_Z_ADDR_0 & 0xffffffe000) | (PART3_Z_RANOTPA_0 << 8) | (PART3_Z_PAGE_SIZE_0 << 4) | (PART3_Z_TSB_SIZE_0)) #endif define(part_3_z_tsb_config_0, `0x'dnl' mpeval(PART3_Z_TSB_CONFIG_0,16))dnl #ifndef PART3_NZ_HWTEN_0 #define PART3_NZ_HWTEN_0 1 #endif #ifndef PART3_NZ_USECTX0_0 #define PART3_NZ_USECTX0_0 0 #endif #ifndef PART3_NZ_USECTX1_0 #define PART3_NZ_USECTX1_0 0 #endif #ifndef PART3_NZ_RANOTPA_0 #define PART3_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART3_NZ_SUN4V_0 0 #else #define PART3_NZ_SUN4V_0 1 #endif #ifndef PART3_NZ_ADDR_0 #define PART3_NZ_ADDR_0 0x1a000000 #endif #ifndef PART3_NZ_TSB_SIZE_0 #define PART3_NZ_TSB_SIZE_0 1 #endif #ifndef PART3_NZ_PAGE_SIZE_0 #define PART3_NZ_PAGE_SIZE_0 0 #endif #ifndef PART3_NZ_TSB_CONFIG_0 #define PART3_NZ_TSB_CONFIG_0 ((PART3_NZ_HWTEN_0 << 63) | (PART3_NZ_USECTX0_0 << 62) | (PART3_NZ_USECTX1_0 << 61) | (PART3_NZ_ADDR_0 & 0xffffffe000) | (PART3_NZ_RANOTPA_0 << 8) | (PART3_NZ_PAGE_SIZE_0 << 4) | (PART3_NZ_TSB_SIZE_0)) #endif define(part_3_nz_tsb_config_0, `0x'dnl' mpeval(PART3_NZ_TSB_CONFIG_0,16))dnl #ifndef PART3_Z_HWTEN_1 #define PART3_Z_HWTEN_1 1 #endif #ifndef PART3_Z_USECTX0_1 #define PART3_Z_USECTX0_1 0 #endif #ifndef PART3_Z_USECTX1_1 #define PART3_Z_USECTX1_1 0 #endif #ifndef PART3_Z_RANOTPA_1 #define PART3_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART3_Z_SUN4V_1 0 #else #define PART3_Z_SUN4V_1 1 #endif #ifndef PART3_Z_ADDR_1 #define PART3_Z_ADDR_1 0x1b000000 #endif #ifndef PART3_Z_TSB_SIZE_1 #define PART3_Z_TSB_SIZE_1 1 #endif #ifndef PART3_Z_PAGE_SIZE_1 #define PART3_Z_PAGE_SIZE_1 0 #endif #ifndef PART3_Z_TSB_CONFIG_1 #define PART3_Z_TSB_CONFIG_1 ((PART3_Z_HWTEN_1 << 63) | (PART3_Z_USECTX0_1 << 62) | (PART3_Z_USECTX1_1 << 61) | (PART3_Z_ADDR_1 & 0xffffffe000) | (PART3_Z_RANOTPA_1 << 8) | (PART3_Z_PAGE_SIZE_1 << 4) | (PART3_Z_TSB_SIZE_1)) #endif define(part_3_z_tsb_config_1, `0x'dnl' mpeval(PART3_Z_TSB_CONFIG_1,16))dnl #ifndef PART3_NZ_HWTEN_1 #define PART3_NZ_HWTEN_1 1 #endif #ifndef PART3_NZ_USECTX0_1 #define PART3_NZ_USECTX0_1 0 #endif #ifndef PART3_NZ_USECTX1_1 #define PART3_NZ_USECTX1_1 0 #endif #ifndef PART3_NZ_RANOTPA_1 #define PART3_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART3_NZ_SUN4V_1 0 #else #define PART3_NZ_SUN4V_1 1 #endif #ifndef PART3_NZ_ADDR_1 #define PART3_NZ_ADDR_1 0x1c000000 #endif #ifndef PART3_NZ_TSB_SIZE_1 #define PART3_NZ_TSB_SIZE_1 1 #endif #ifndef PART3_NZ_PAGE_SIZE_1 #define PART3_NZ_PAGE_SIZE_1 0 #endif #ifndef PART3_NZ_TSB_CONFIG_1 #define PART3_NZ_TSB_CONFIG_1 ((PART3_NZ_HWTEN_1 << 63) | (PART3_NZ_USECTX0_1 << 62) | (PART3_NZ_USECTX1_1 << 61) | (PART3_NZ_ADDR_1 & 0xffffffe000) | (PART3_NZ_RANOTPA_1 << 8) | (PART3_NZ_PAGE_SIZE_1 << 4) | (PART3_NZ_TSB_SIZE_1)) #endif define(part_3_nz_tsb_config_1, `0x'dnl' mpeval(PART3_NZ_TSB_CONFIG_1,16))dnl #ifndef PART3_Z_HWTEN_2 #define PART3_Z_HWTEN_2 1 #endif #ifndef PART3_Z_USECTX0_2 #define PART3_Z_USECTX0_2 0 #endif #ifndef PART3_Z_USECTX1_2 #define PART3_Z_USECTX1_2 0 #endif #ifndef PART3_Z_RANOTPA_2 #define PART3_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART3_Z_SUN4V_2 0 #else #define PART3_Z_SUN4V_2 1 #endif #ifndef PART3_Z_ADDR_2 #define PART3_Z_ADDR_2 0x1d000000 #endif #ifndef PART3_Z_TSB_SIZE_2 #define PART3_Z_TSB_SIZE_2 1 #endif #ifndef PART3_Z_PAGE_SIZE_2 #define PART3_Z_PAGE_SIZE_2 0 #endif #ifndef PART3_Z_TSB_CONFIG_2 #define PART3_Z_TSB_CONFIG_2 ((PART3_Z_HWTEN_2 << 63) | (PART3_Z_USECTX0_2 << 62) | (PART3_Z_USECTX1_2 << 61) | (PART3_Z_ADDR_2 & 0xffffffe000) | (PART3_Z_RANOTPA_2 << 8) | (PART3_Z_PAGE_SIZE_2 << 4) | (PART3_Z_TSB_SIZE_2)) #endif define(part_3_z_tsb_config_2, `0x'dnl' mpeval(PART3_Z_TSB_CONFIG_2,16))dnl #ifndef PART3_NZ_HWTEN_2 #define PART3_NZ_HWTEN_2 1 #endif #ifndef PART3_NZ_USECTX0_2 #define PART3_NZ_USECTX0_2 0 #endif #ifndef PART3_NZ_USECTX1_2 #define PART3_NZ_USECTX1_2 0 #endif #ifndef PART3_NZ_RANOTPA_2 #define PART3_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART3_NZ_SUN4V_2 0 #else #define PART3_NZ_SUN4V_2 1 #endif #ifndef PART3_NZ_ADDR_2 #define PART3_NZ_ADDR_2 0x1e000000 #endif #ifndef PART3_NZ_TSB_SIZE_2 #define PART3_NZ_TSB_SIZE_2 1 #endif #ifndef PART3_NZ_PAGE_SIZE_2 #define PART3_NZ_PAGE_SIZE_2 0 #endif #ifndef PART3_NZ_TSB_CONFIG_2 #define PART3_NZ_TSB_CONFIG_2 ((PART3_NZ_HWTEN_2 << 63) | (PART3_NZ_USECTX0_2 << 62) | (PART3_NZ_USECTX1_2 << 61) | (PART3_NZ_ADDR_2 & 0xffffffe000) | (PART3_NZ_RANOTPA_2 << 8) | (PART3_NZ_PAGE_SIZE_2 << 4) | (PART3_NZ_TSB_SIZE_2)) #endif define(part_3_nz_tsb_config_2, `0x'dnl' mpeval(PART3_NZ_TSB_CONFIG_2,16))dnl #ifndef PART3_Z_HWTEN_3 #define PART3_Z_HWTEN_3 1 #endif #ifndef PART3_Z_USECTX0_3 #define PART3_Z_USECTX0_3 0 #endif #ifndef PART3_Z_USECTX1_3 #define PART3_Z_USECTX1_3 0 #endif #ifndef PART3_Z_RANOTPA_3 #define PART3_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART3_Z_SUN4V_3 0 #else #define PART3_Z_SUN4V_3 1 #endif #ifndef PART3_Z_ADDR_3 #define PART3_Z_ADDR_3 0x1f000000 #endif #ifndef PART3_Z_TSB_SIZE_3 #define PART3_Z_TSB_SIZE_3 1 #endif #ifndef PART3_Z_PAGE_SIZE_3 #define PART3_Z_PAGE_SIZE_3 0 #endif #ifndef PART3_Z_TSB_CONFIG_3 #define PART3_Z_TSB_CONFIG_3 ((PART3_Z_HWTEN_3 << 63) | (PART3_Z_USECTX0_3 << 62) | (PART3_Z_USECTX1_3 << 61) | (PART3_Z_ADDR_3 & 0xffffffe000) | (PART3_Z_RANOTPA_3 << 8) | (PART3_Z_PAGE_SIZE_3 << 4) | (PART3_Z_TSB_SIZE_3)) #endif define(part_3_z_tsb_config_3, `0x'dnl' mpeval(PART3_Z_TSB_CONFIG_3,16))dnl #ifndef PART3_NZ_HWTEN_3 #define PART3_NZ_HWTEN_3 1 #endif #ifndef PART3_NZ_USECTX0_3 #define PART3_NZ_USECTX0_3 0 #endif #ifndef PART3_NZ_USECTX1_3 #define PART3_NZ_USECTX1_3 0 #endif #ifndef PART3_NZ_RANOTPA_3 #define PART3_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART3_NZ_SUN4V_3 0 #else #define PART3_NZ_SUN4V_3 1 #endif #ifndef PART3_NZ_ADDR_3 #define PART3_NZ_ADDR_3 0x20000000 #endif #ifndef PART3_NZ_TSB_SIZE_3 #define PART3_NZ_TSB_SIZE_3 1 #endif #ifndef PART3_NZ_PAGE_SIZE_3 #define PART3_NZ_PAGE_SIZE_3 0 #endif #ifndef PART3_NZ_TSB_CONFIG_3 #define PART3_NZ_TSB_CONFIG_3 ((PART3_NZ_HWTEN_3 << 63) | (PART3_NZ_USECTX0_3 << 62) | (PART3_NZ_USECTX1_3 << 61) | (PART3_NZ_ADDR_3 & 0xffffffe000) | (PART3_NZ_RANOTPA_3 << 8) | (PART3_NZ_PAGE_SIZE_3 << 4) | (PART3_NZ_TSB_SIZE_3)) #endif define(part_3_nz_tsb_config_3, `0x'dnl' mpeval(PART3_NZ_TSB_CONFIG_3,16))dnl #ifndef PART3_PHY_OFF_X_0 #define PART3_PHY_OFF_X_0 1 #endif #ifndef PART3_PHY_OFF_P_0 #define PART3_PHY_OFF_P_0 0 #endif #ifndef PART3_PHY_OFF_W_0 #define PART3_PHY_OFF_W_0 0 #endif #ifndef PART3_PHY_OFF_0 #define PART3_PHY_OFF_0 ((PART_3_BASE) | (PART3_PHY_OFF_X_1 << 12) | (PART3_PHY_OFF_P_1 << 11) | (PART3_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART3_PHY_OFF_X_1 #define PART3_PHY_OFF_X_1 1 #endif #ifndef PART3_PHY_OFF_P_1 #define PART3_PHY_OFF_P_1 0 #endif #ifndef PART3_PHY_OFF_W_1 #define PART3_PHY_OFF_W_1 0 #endif #ifndef PART3_PHY_OFF_1 #define PART3_PHY_OFF_1 ((PART_3_BASE) | (PART3_PHY_OFF_X_1 << 12) | (PART3_PHY_OFF_P_1 << 11) | (PART3_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART3_PHY_OFF_X_2 #define PART3_PHY_OFF_X_2 1 #endif #ifndef PART3_PHY_OFF_P_2 #define PART3_PHY_OFF_P_2 0 #endif #ifndef PART3_PHY_OFF_W_2 #define PART3_PHY_OFF_W_2 0 #endif #ifndef PART3_PHY_OFF_2 #define PART3_PHY_OFF_2 ((PART_3_BASE) | (PART3_PHY_OFF_X_2 << 12) | (PART3_PHY_OFF_P_2 << 11) | (PART3_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART3_PHY_OFF_X_3 #define PART3_PHY_OFF_X_3 1 #endif #ifndef PART3_PHY_OFF_P_3 #define PART3_PHY_OFF_P_3 0 #endif #ifndef PART3_PHY_OFF_W_3 #define PART3_PHY_OFF_W_3 0 #endif #ifndef PART3_PHY_OFF_3 #define PART3_PHY_OFF_3 ((PART_3_BASE) | (PART3_PHY_OFF_X_3 << 12) | (PART3_PHY_OFF_P_3 << 11) | (PART3_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 4 //////////////////////// #ifndef PART4_Z_HWTEN_0 #define PART4_Z_HWTEN_0 1 #endif #ifndef PART4_Z_USECTX0_0 #define PART4_Z_USECTX0_0 0 #endif #ifndef PART4_Z_USECTX1_0 #define PART4_Z_USECTX1_0 0 #endif #ifndef PART4_Z_RANOTPA_0 #define PART4_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART4_Z_SUN4V_0 0 #else #define PART4_Z_SUN4V_0 1 #endif #ifndef PART4_Z_ADDR_0 #define PART4_Z_ADDR_0 0x21000000 #endif #ifndef PART4_Z_TSB_SIZE_0 #define PART4_Z_TSB_SIZE_0 1 #endif #ifndef PART4_Z_PAGE_SIZE_0 #define PART4_Z_PAGE_SIZE_0 0 #endif #ifndef PART4_Z_TSB_CONFIG_0 #define PART4_Z_TSB_CONFIG_0 ((PART4_Z_HWTEN_0 << 63) | (PART4_Z_USECTX0_0 << 62) | (PART4_Z_USECTX1_0 << 61) | (PART4_Z_ADDR_0 & 0xffffffe000) | (PART4_Z_RANOTPA_0 << 8) | (PART4_Z_PAGE_SIZE_0 << 4) | (PART4_Z_TSB_SIZE_0)) #endif define(part_4_z_tsb_config_0, `0x'dnl' mpeval(PART4_Z_TSB_CONFIG_0,16))dnl #ifndef PART4_NZ_HWTEN_0 #define PART4_NZ_HWTEN_0 1 #endif #ifndef PART4_NZ_USECTX0_0 #define PART4_NZ_USECTX0_0 0 #endif #ifndef PART4_NZ_USECTX1_0 #define PART4_NZ_USECTX1_0 0 #endif #ifndef PART4_NZ_RANOTPA_0 #define PART4_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART4_NZ_SUN4V_0 0 #else #define PART4_NZ_SUN4V_0 1 #endif #ifndef PART4_NZ_ADDR_0 #define PART4_NZ_ADDR_0 0x22000000 #endif #ifndef PART4_NZ_TSB_SIZE_0 #define PART4_NZ_TSB_SIZE_0 1 #endif #ifndef PART4_NZ_PAGE_SIZE_0 #define PART4_NZ_PAGE_SIZE_0 0 #endif #ifndef PART4_NZ_TSB_CONFIG_0 #define PART4_NZ_TSB_CONFIG_0 ((PART4_NZ_HWTEN_0 << 63) | (PART4_NZ_USECTX0_0 << 62) | (PART4_NZ_USECTX1_0 << 61) | (PART4_NZ_ADDR_0 & 0xffffffe000) | (PART4_NZ_RANOTPA_0 << 8) | (PART4_NZ_PAGE_SIZE_0 << 4) | (PART4_NZ_TSB_SIZE_0)) #endif define(part_4_nz_tsb_config_0, `0x'dnl' mpeval(PART4_NZ_TSB_CONFIG_0,16))dnl #ifndef PART4_Z_HWTEN_1 #define PART4_Z_HWTEN_1 1 #endif #ifndef PART4_Z_USECTX0_1 #define PART4_Z_USECTX0_1 0 #endif #ifndef PART4_Z_USECTX1_1 #define PART4_Z_USECTX1_1 0 #endif #ifndef PART4_Z_RANOTPA_1 #define PART4_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART4_Z_SUN4V_1 0 #else #define PART4_Z_SUN4V_1 1 #endif #ifndef PART4_Z_ADDR_1 #define PART4_Z_ADDR_1 0x23000000 #endif #ifndef PART4_Z_TSB_SIZE_1 #define PART4_Z_TSB_SIZE_1 1 #endif #ifndef PART4_Z_PAGE_SIZE_1 #define PART4_Z_PAGE_SIZE_1 0 #endif #ifndef PART4_Z_TSB_CONFIG_1 #define PART4_Z_TSB_CONFIG_1 ((PART4_Z_HWTEN_1 << 63) | (PART4_Z_USECTX0_1 << 62) | (PART4_Z_USECTX1_1 << 61) | (PART4_Z_ADDR_1 & 0xffffffe000) | (PART4_Z_RANOTPA_1 << 8) | (PART4_Z_PAGE_SIZE_1 << 4) | (PART4_Z_TSB_SIZE_1)) #endif define(part_4_z_tsb_config_1, `0x'dnl' mpeval(PART4_Z_TSB_CONFIG_1,16))dnl #ifndef PART4_NZ_HWTEN_1 #define PART4_NZ_HWTEN_1 1 #endif #ifndef PART4_NZ_USECTX0_1 #define PART4_NZ_USECTX0_1 0 #endif #ifndef PART4_NZ_USECTX1_1 #define PART4_NZ_USECTX1_1 0 #endif #ifndef PART4_NZ_RANOTPA_1 #define PART4_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART4_NZ_SUN4V_1 0 #else #define PART4_NZ_SUN4V_1 1 #endif #ifndef PART4_NZ_ADDR_1 #define PART4_NZ_ADDR_1 0x24000000 #endif #ifndef PART4_NZ_TSB_SIZE_1 #define PART4_NZ_TSB_SIZE_1 1 #endif #ifndef PART4_NZ_PAGE_SIZE_1 #define PART4_NZ_PAGE_SIZE_1 0 #endif #ifndef PART4_NZ_TSB_CONFIG_1 #define PART4_NZ_TSB_CONFIG_1 ((PART4_NZ_HWTEN_1 << 63) | (PART4_NZ_USECTX0_1 << 62) | (PART4_NZ_USECTX1_1 << 61) | (PART4_NZ_ADDR_1 & 0xffffffe000) | (PART4_NZ_RANOTPA_1 << 8) | (PART4_NZ_PAGE_SIZE_1 << 4) | (PART4_NZ_TSB_SIZE_1)) #endif define(part_4_nz_tsb_config_1, `0x'dnl' mpeval(PART4_NZ_TSB_CONFIG_1,16))dnl #ifndef PART4_Z_HWTEN_2 #define PART4_Z_HWTEN_2 1 #endif #ifndef PART4_Z_USECTX0_2 #define PART4_Z_USECTX0_2 0 #endif #ifndef PART4_Z_USECTX1_2 #define PART4_Z_USECTX1_2 0 #endif #ifndef PART4_Z_RANOTPA_2 #define PART4_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART4_Z_SUN4V_2 0 #else #define PART4_Z_SUN4V_2 1 #endif #ifndef PART4_Z_ADDR_2 #define PART4_Z_ADDR_2 0x25000000 #endif #ifndef PART4_Z_TSB_SIZE_2 #define PART4_Z_TSB_SIZE_2 1 #endif #ifndef PART4_Z_PAGE_SIZE_2 #define PART4_Z_PAGE_SIZE_2 0 #endif #ifndef PART4_Z_TSB_CONFIG_2 #define PART4_Z_TSB_CONFIG_2 ((PART4_Z_HWTEN_2 << 63) | (PART4_Z_USECTX0_2 << 62) | (PART4_Z_USECTX1_2 << 61) | (PART4_Z_ADDR_2 & 0xffffffe000) | (PART4_Z_RANOTPA_2 << 8) | (PART4_Z_PAGE_SIZE_2 << 4) | (PART4_Z_TSB_SIZE_2)) #endif define(part_4_z_tsb_config_2, `0x'dnl' mpeval(PART4_Z_TSB_CONFIG_2,16))dnl #ifndef PART4_NZ_HWTEN_2 #define PART4_NZ_HWTEN_2 1 #endif #ifndef PART4_NZ_USECTX0_2 #define PART4_NZ_USECTX0_2 0 #endif #ifndef PART4_NZ_USECTX1_2 #define PART4_NZ_USECTX1_2 0 #endif #ifndef PART4_NZ_RANOTPA_2 #define PART4_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART4_NZ_SUN4V_2 0 #else #define PART4_NZ_SUN4V_2 1 #endif #ifndef PART4_NZ_ADDR_2 #define PART4_NZ_ADDR_2 0x26000000 #endif #ifndef PART4_NZ_TSB_SIZE_2 #define PART4_NZ_TSB_SIZE_2 1 #endif #ifndef PART4_NZ_PAGE_SIZE_2 #define PART4_NZ_PAGE_SIZE_2 0 #endif #ifndef PART4_NZ_TSB_CONFIG_2 #define PART4_NZ_TSB_CONFIG_2 ((PART4_NZ_HWTEN_2 << 63) | (PART4_NZ_USECTX0_2 << 62) | (PART4_NZ_USECTX1_2 << 61) | (PART4_NZ_ADDR_2 & 0xffffffe000) | (PART4_NZ_RANOTPA_2 << 8) | (PART4_NZ_PAGE_SIZE_2 << 4) | (PART4_NZ_TSB_SIZE_2)) #endif define(part_4_nz_tsb_config_2, `0x'dnl' mpeval(PART4_NZ_TSB_CONFIG_2,16))dnl #ifndef PART4_Z_HWTEN_3 #define PART4_Z_HWTEN_3 1 #endif #ifndef PART4_Z_USECTX0_3 #define PART4_Z_USECTX0_3 0 #endif #ifndef PART4_Z_USECTX1_3 #define PART4_Z_USECTX1_3 0 #endif #ifndef PART4_Z_RANOTPA_3 #define PART4_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART4_Z_SUN4V_3 0 #else #define PART4_Z_SUN4V_3 1 #endif #ifndef PART4_Z_ADDR_3 #define PART4_Z_ADDR_3 0x27000000 #endif #ifndef PART4_Z_TSB_SIZE_3 #define PART4_Z_TSB_SIZE_3 1 #endif #ifndef PART4_Z_PAGE_SIZE_3 #define PART4_Z_PAGE_SIZE_3 0 #endif #ifndef PART4_Z_TSB_CONFIG_3 #define PART4_Z_TSB_CONFIG_3 ((PART4_Z_HWTEN_3 << 63) | (PART4_Z_USECTX0_3 << 62) | (PART4_Z_USECTX1_3 << 61) | (PART4_Z_ADDR_3 & 0xffffffe000) | (PART4_Z_RANOTPA_3 << 8) | (PART4_Z_PAGE_SIZE_3 << 4) | (PART4_Z_TSB_SIZE_3)) #endif define(part_4_z_tsb_config_3, `0x'dnl' mpeval(PART4_Z_TSB_CONFIG_3,16))dnl #ifndef PART4_NZ_HWTEN_3 #define PART4_NZ_HWTEN_3 1 #endif #ifndef PART4_NZ_USECTX0_3 #define PART4_NZ_USECTX0_3 0 #endif #ifndef PART4_NZ_USECTX1_3 #define PART4_NZ_USECTX1_3 0 #endif #ifndef PART4_NZ_RANOTPA_3 #define PART4_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART4_NZ_SUN4V_3 0 #else #define PART4_NZ_SUN4V_3 1 #endif #ifndef PART4_NZ_ADDR_3 #define PART4_NZ_ADDR_3 0x28000000 #endif #ifndef PART4_NZ_TSB_SIZE_3 #define PART4_NZ_TSB_SIZE_3 1 #endif #ifndef PART4_NZ_PAGE_SIZE_3 #define PART4_NZ_PAGE_SIZE_3 0 #endif #ifndef PART4_NZ_TSB_CONFIG_3 #define PART4_NZ_TSB_CONFIG_3 ((PART4_NZ_HWTEN_3 << 63) | (PART4_NZ_USECTX0_3 << 62) | (PART4_NZ_USECTX1_3 << 61) | (PART4_NZ_ADDR_3 & 0xffffffe000) | (PART4_NZ_RANOTPA_3 << 8) | (PART4_NZ_PAGE_SIZE_3 << 4) | (PART4_NZ_TSB_SIZE_3)) #endif define(part_4_nz_tsb_config_3, `0x'dnl' mpeval(PART4_NZ_TSB_CONFIG_3,16))dnl #ifndef PART4_PHY_OFF_X_0 #define PART4_PHY_OFF_X_0 1 #endif #ifndef PART4_PHY_OFF_P_0 #define PART4_PHY_OFF_P_0 0 #endif #ifndef PART4_PHY_OFF_W_0 #define PART4_PHY_OFF_W_0 0 #endif #ifndef PART4_PHY_OFF_0 #define PART4_PHY_OFF_0 ((PART_4_BASE) | (PART4_PHY_OFF_X_1 << 12) | (PART4_PHY_OFF_P_1 << 11) | (PART4_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART4_PHY_OFF_X_1 #define PART4_PHY_OFF_X_1 1 #endif #ifndef PART4_PHY_OFF_P_1 #define PART4_PHY_OFF_P_1 0 #endif #ifndef PART4_PHY_OFF_W_1 #define PART4_PHY_OFF_W_1 0 #endif #ifndef PART4_PHY_OFF_1 #define PART4_PHY_OFF_1 ((PART_4_BASE) | (PART4_PHY_OFF_X_1 << 12) | (PART4_PHY_OFF_P_1 << 11) | (PART4_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART4_PHY_OFF_X_2 #define PART4_PHY_OFF_X_2 1 #endif #ifndef PART4_PHY_OFF_P_2 #define PART4_PHY_OFF_P_2 0 #endif #ifndef PART4_PHY_OFF_W_2 #define PART4_PHY_OFF_W_2 0 #endif #ifndef PART4_PHY_OFF_2 #define PART4_PHY_OFF_2 ((PART_4_BASE) | (PART4_PHY_OFF_X_2 << 12) | (PART4_PHY_OFF_P_2 << 11) | (PART4_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART4_PHY_OFF_X_3 #define PART4_PHY_OFF_X_3 1 #endif #ifndef PART4_PHY_OFF_P_3 #define PART4_PHY_OFF_P_3 0 #endif #ifndef PART4_PHY_OFF_W_3 #define PART4_PHY_OFF_W_3 0 #endif #ifndef PART4_PHY_OFF_3 #define PART4_PHY_OFF_3 ((PART_4_BASE) | (PART4_PHY_OFF_X_3 << 12) | (PART4_PHY_OFF_P_3 << 11) | (PART4_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 5 //////////////////////// #ifndef PART5_Z_HWTEN_0 #define PART5_Z_HWTEN_0 1 #endif #ifndef PART5_Z_USECTX0_0 #define PART5_Z_USECTX0_0 0 #endif #ifndef PART5_Z_USECTX1_0 #define PART5_Z_USECTX1_0 0 #endif #ifndef PART5_Z_RANOTPA_0 #define PART5_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART5_Z_SUN4V_0 0 #else #define PART5_Z_SUN4V_0 1 #endif #ifndef PART5_Z_ADDR_0 #define PART5_Z_ADDR_0 0x29000000 #endif #ifndef PART5_Z_TSB_SIZE_0 #define PART5_Z_TSB_SIZE_0 1 #endif #ifndef PART5_Z_PAGE_SIZE_0 #define PART5_Z_PAGE_SIZE_0 0 #endif #ifndef PART5_Z_TSB_CONFIG_0 #define PART5_Z_TSB_CONFIG_0 ((PART5_Z_HWTEN_0 << 63) | (PART5_Z_USECTX0_0 << 62) | (PART5_Z_USECTX1_0 << 61) | (PART5_Z_ADDR_0 & 0xffffffe000) | (PART5_Z_RANOTPA_0 << 8) | (PART5_Z_PAGE_SIZE_0 << 4) | (PART5_Z_TSB_SIZE_0)) #endif define(part_5_z_tsb_config_0, `0x'dnl' mpeval(PART5_Z_TSB_CONFIG_0,16))dnl #ifndef PART5_NZ_HWTEN_0 #define PART5_NZ_HWTEN_0 1 #endif #ifndef PART5_NZ_USECTX0_0 #define PART5_NZ_USECTX0_0 0 #endif #ifndef PART5_NZ_USECTX1_0 #define PART5_NZ_USECTX1_0 0 #endif #ifndef PART5_NZ_RANOTPA_0 #define PART5_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART5_NZ_SUN4V_0 0 #else #define PART5_NZ_SUN4V_0 1 #endif #ifndef PART5_NZ_ADDR_0 #define PART5_NZ_ADDR_0 0x2a000000 #endif #ifndef PART5_NZ_TSB_SIZE_0 #define PART5_NZ_TSB_SIZE_0 1 #endif #ifndef PART5_NZ_PAGE_SIZE_0 #define PART5_NZ_PAGE_SIZE_0 0 #endif #ifndef PART5_NZ_TSB_CONFIG_0 #define PART5_NZ_TSB_CONFIG_0 ((PART5_NZ_HWTEN_0 << 63) | (PART5_NZ_USECTX0_0 << 62) | (PART5_NZ_USECTX1_0 << 61) | (PART5_NZ_ADDR_0 & 0xffffffe000) | (PART5_NZ_RANOTPA_0 << 8) | (PART5_NZ_PAGE_SIZE_0 << 4) | (PART5_NZ_TSB_SIZE_0)) #endif define(part_5_nz_tsb_config_0, `0x'dnl' mpeval(PART5_NZ_TSB_CONFIG_0,16))dnl #ifndef PART5_Z_HWTEN_1 #define PART5_Z_HWTEN_1 1 #endif #ifndef PART5_Z_USECTX0_1 #define PART5_Z_USECTX0_1 0 #endif #ifndef PART5_Z_USECTX1_1 #define PART5_Z_USECTX1_1 0 #endif #ifndef PART5_Z_RANOTPA_1 #define PART5_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART5_Z_SUN4V_1 0 #else #define PART5_Z_SUN4V_1 1 #endif #ifndef PART5_Z_ADDR_1 #define PART5_Z_ADDR_1 0x2b000000 #endif #ifndef PART5_Z_TSB_SIZE_1 #define PART5_Z_TSB_SIZE_1 1 #endif #ifndef PART5_Z_PAGE_SIZE_1 #define PART5_Z_PAGE_SIZE_1 0 #endif #ifndef PART5_Z_TSB_CONFIG_1 #define PART5_Z_TSB_CONFIG_1 ((PART5_Z_HWTEN_1 << 63) | (PART5_Z_USECTX0_1 << 62) | (PART5_Z_USECTX1_1 << 61) | (PART5_Z_ADDR_1 & 0xffffffe000) | (PART5_Z_RANOTPA_1 << 8) | (PART5_Z_PAGE_SIZE_1 << 4) | (PART5_Z_TSB_SIZE_1)) #endif define(part_5_z_tsb_config_1, `0x'dnl' mpeval(PART5_Z_TSB_CONFIG_1,16))dnl #ifndef PART5_NZ_HWTEN_1 #define PART5_NZ_HWTEN_1 1 #endif #ifndef PART5_NZ_USECTX0_1 #define PART5_NZ_USECTX0_1 0 #endif #ifndef PART5_NZ_USECTX1_1 #define PART5_NZ_USECTX1_1 0 #endif #ifndef PART5_NZ_RANOTPA_1 #define PART5_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART5_NZ_SUN4V_1 0 #else #define PART5_NZ_SUN4V_1 1 #endif #ifndef PART5_NZ_ADDR_1 #define PART5_NZ_ADDR_1 0x2c000000 #endif #ifndef PART5_NZ_TSB_SIZE_1 #define PART5_NZ_TSB_SIZE_1 1 #endif #ifndef PART5_NZ_PAGE_SIZE_1 #define PART5_NZ_PAGE_SIZE_1 0 #endif #ifndef PART5_NZ_TSB_CONFIG_1 #define PART5_NZ_TSB_CONFIG_1 ((PART5_NZ_HWTEN_1 << 63) | (PART5_NZ_USECTX0_1 << 62) | (PART5_NZ_USECTX1_1 << 61) | (PART5_NZ_ADDR_1 & 0xffffffe000) | (PART5_NZ_RANOTPA_1 << 8) | (PART5_NZ_PAGE_SIZE_1 << 4) | (PART5_NZ_TSB_SIZE_1)) #endif define(part_5_nz_tsb_config_1, `0x'dnl' mpeval(PART5_NZ_TSB_CONFIG_1,16))dnl #ifndef PART5_Z_HWTEN_2 #define PART5_Z_HWTEN_2 1 #endif #ifndef PART5_Z_USECTX0_2 #define PART5_Z_USECTX0_2 0 #endif #ifndef PART5_Z_USECTX1_2 #define PART5_Z_USECTX1_2 0 #endif #ifndef PART5_Z_RANOTPA_2 #define PART5_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART5_Z_SUN4V_2 0 #else #define PART5_Z_SUN4V_2 1 #endif #ifndef PART5_Z_ADDR_2 #define PART5_Z_ADDR_2 0x2d000000 #endif #ifndef PART5_Z_TSB_SIZE_2 #define PART5_Z_TSB_SIZE_2 1 #endif #ifndef PART5_Z_PAGE_SIZE_2 #define PART5_Z_PAGE_SIZE_2 0 #endif #ifndef PART5_Z_TSB_CONFIG_2 #define PART5_Z_TSB_CONFIG_2 ((PART5_Z_HWTEN_2 << 63) | (PART5_Z_USECTX0_2 << 62) | (PART5_Z_USECTX1_2 << 61) | (PART5_Z_ADDR_2 & 0xffffffe000) | (PART5_Z_RANOTPA_2 << 8) | (PART5_Z_PAGE_SIZE_2 << 4) | (PART5_Z_TSB_SIZE_2)) #endif define(part_5_z_tsb_config_2, `0x'dnl' mpeval(PART5_Z_TSB_CONFIG_2,16))dnl #ifndef PART5_NZ_HWTEN_2 #define PART5_NZ_HWTEN_2 1 #endif #ifndef PART5_NZ_USECTX0_2 #define PART5_NZ_USECTX0_2 0 #endif #ifndef PART5_NZ_USECTX1_2 #define PART5_NZ_USECTX1_2 0 #endif #ifndef PART5_NZ_RANOTPA_2 #define PART5_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART5_NZ_SUN4V_2 0 #else #define PART5_NZ_SUN4V_2 1 #endif #ifndef PART5_NZ_ADDR_2 #define PART5_NZ_ADDR_2 0x2e000000 #endif #ifndef PART5_NZ_TSB_SIZE_2 #define PART5_NZ_TSB_SIZE_2 1 #endif #ifndef PART5_NZ_PAGE_SIZE_2 #define PART5_NZ_PAGE_SIZE_2 0 #endif #ifndef PART5_NZ_TSB_CONFIG_2 #define PART5_NZ_TSB_CONFIG_2 ((PART5_NZ_HWTEN_2 << 63) | (PART5_NZ_USECTX0_2 << 62) | (PART5_NZ_USECTX1_2 << 61) | (PART5_NZ_ADDR_2 & 0xffffffe000) | (PART5_NZ_RANOTPA_2 << 8) | (PART5_NZ_PAGE_SIZE_2 << 4) | (PART5_NZ_TSB_SIZE_2)) #endif define(part_5_nz_tsb_config_2, `0x'dnl' mpeval(PART5_NZ_TSB_CONFIG_2,16))dnl #ifndef PART5_Z_HWTEN_3 #define PART5_Z_HWTEN_3 1 #endif #ifndef PART5_Z_USECTX0_3 #define PART5_Z_USECTX0_3 0 #endif #ifndef PART5_Z_USECTX1_3 #define PART5_Z_USECTX1_3 0 #endif #ifndef PART5_Z_RANOTPA_3 #define PART5_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART5_Z_SUN4V_3 0 #else #define PART5_Z_SUN4V_3 1 #endif #ifndef PART5_Z_ADDR_3 #define PART5_Z_ADDR_3 0x2f000000 #endif #ifndef PART5_Z_TSB_SIZE_3 #define PART5_Z_TSB_SIZE_3 1 #endif #ifndef PART5_Z_PAGE_SIZE_3 #define PART5_Z_PAGE_SIZE_3 0 #endif #ifndef PART5_Z_TSB_CONFIG_3 #define PART5_Z_TSB_CONFIG_3 ((PART5_Z_HWTEN_3 << 63) | (PART5_Z_USECTX0_3 << 62) | (PART5_Z_USECTX1_3 << 61) | (PART5_Z_ADDR_3 & 0xffffffe000) | (PART5_Z_RANOTPA_3 << 8) | (PART5_Z_PAGE_SIZE_3 << 4) | (PART5_Z_TSB_SIZE_3)) #endif define(part_5_z_tsb_config_3, `0x'dnl' mpeval(PART5_Z_TSB_CONFIG_3,16))dnl #ifndef PART5_NZ_HWTEN_3 #define PART5_NZ_HWTEN_3 1 #endif #ifndef PART5_NZ_USECTX0_3 #define PART5_NZ_USECTX0_3 0 #endif #ifndef PART5_NZ_USECTX1_3 #define PART5_NZ_USECTX1_3 0 #endif #ifndef PART5_NZ_RANOTPA_3 #define PART5_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART5_NZ_SUN4V_3 0 #else #define PART5_NZ_SUN4V_3 1 #endif #ifndef PART5_NZ_ADDR_3 #define PART5_NZ_ADDR_3 0x30000000 #endif #ifndef PART5_NZ_TSB_SIZE_3 #define PART5_NZ_TSB_SIZE_3 1 #endif #ifndef PART5_NZ_PAGE_SIZE_3 #define PART5_NZ_PAGE_SIZE_3 0 #endif #ifndef PART5_NZ_TSB_CONFIG_3 #define PART5_NZ_TSB_CONFIG_3 ((PART5_NZ_HWTEN_3 << 63) | (PART5_NZ_USECTX0_3 << 62) | (PART5_NZ_USECTX1_3 << 61) | (PART5_NZ_ADDR_3 & 0xffffffe000) | (PART5_NZ_RANOTPA_3 << 8) | (PART5_NZ_PAGE_SIZE_3 << 4) | (PART5_NZ_TSB_SIZE_3)) #endif define(part_5_nz_tsb_config_3, `0x'dnl' mpeval(PART5_NZ_TSB_CONFIG_3,16))dnl #ifndef PART5_PHY_OFF_X_0 #define PART5_PHY_OFF_X_0 1 #endif #ifndef PART5_PHY_OFF_P_0 #define PART5_PHY_OFF_P_0 0 #endif #ifndef PART5_PHY_OFF_W_0 #define PART5_PHY_OFF_W_0 0 #endif #ifndef PART5_PHY_OFF_0 #define PART5_PHY_OFF_0 ((PART_5_BASE) | (PART5_PHY_OFF_X_1 << 12) | (PART5_PHY_OFF_P_1 << 11) | (PART5_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART5_PHY_OFF_X_1 #define PART5_PHY_OFF_X_1 1 #endif #ifndef PART5_PHY_OFF_P_1 #define PART5_PHY_OFF_P_1 0 #endif #ifndef PART5_PHY_OFF_W_1 #define PART5_PHY_OFF_W_1 0 #endif #ifndef PART5_PHY_OFF_1 #define PART5_PHY_OFF_1 ((PART_5_BASE) | (PART5_PHY_OFF_X_1 << 12) | (PART5_PHY_OFF_P_1 << 11) | (PART5_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART5_PHY_OFF_X_2 #define PART5_PHY_OFF_X_2 1 #endif #ifndef PART5_PHY_OFF_P_2 #define PART5_PHY_OFF_P_2 0 #endif #ifndef PART5_PHY_OFF_W_2 #define PART5_PHY_OFF_W_2 0 #endif #ifndef PART5_PHY_OFF_2 #define PART5_PHY_OFF_2 ((PART_5_BASE) | (PART5_PHY_OFF_X_2 << 12) | (PART5_PHY_OFF_P_2 << 11) | (PART5_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART5_PHY_OFF_X_3 #define PART5_PHY_OFF_X_3 1 #endif #ifndef PART5_PHY_OFF_P_3 #define PART5_PHY_OFF_P_3 0 #endif #ifndef PART5_PHY_OFF_W_3 #define PART5_PHY_OFF_W_3 0 #endif #ifndef PART5_PHY_OFF_3 #define PART5_PHY_OFF_3 ((PART_5_BASE) | (PART5_PHY_OFF_X_3 << 12) | (PART5_PHY_OFF_P_3 << 11) | (PART5_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 6 //////////////////////// #ifndef PART6_Z_HWTEN_0 #define PART6_Z_HWTEN_0 1 #endif #ifndef PART6_Z_USECTX0_0 #define PART6_Z_USECTX0_0 0 #endif #ifndef PART6_Z_USECTX1_0 #define PART6_Z_USECTX1_0 0 #endif #ifndef PART6_Z_RANOTPA_0 #define PART6_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART6_Z_SUN4V_0 0 #else #define PART6_Z_SUN4V_0 1 #endif #ifndef PART6_Z_ADDR_0 #define PART6_Z_ADDR_0 0x31000000 #endif #ifndef PART6_Z_TSB_SIZE_0 #define PART6_Z_TSB_SIZE_0 1 #endif #ifndef PART6_Z_PAGE_SIZE_0 #define PART6_Z_PAGE_SIZE_0 0 #endif #ifndef PART6_Z_TSB_CONFIG_0 #define PART6_Z_TSB_CONFIG_0 ((PART6_Z_HWTEN_0 << 63) | (PART6_Z_USECTX0_0 << 62) | (PART6_Z_USECTX1_0 << 61) | (PART6_Z_ADDR_0 & 0xffffffe000) | (PART6_Z_RANOTPA_0 << 8) | (PART6_Z_PAGE_SIZE_0 << 4) | (PART6_Z_TSB_SIZE_0)) #endif define(part_6_z_tsb_config_0, `0x'dnl' mpeval(PART6_Z_TSB_CONFIG_0,16))dnl #ifndef PART6_NZ_HWTEN_0 #define PART6_NZ_HWTEN_0 1 #endif #ifndef PART6_NZ_USECTX0_0 #define PART6_NZ_USECTX0_0 0 #endif #ifndef PART6_NZ_USECTX1_0 #define PART6_NZ_USECTX1_0 0 #endif #ifndef PART6_NZ_RANOTPA_0 #define PART6_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART6_NZ_SUN4V_0 0 #else #define PART6_NZ_SUN4V_0 1 #endif #ifndef PART6_NZ_ADDR_0 #define PART6_NZ_ADDR_0 0x32000000 #endif #ifndef PART6_NZ_TSB_SIZE_0 #define PART6_NZ_TSB_SIZE_0 1 #endif #ifndef PART6_NZ_PAGE_SIZE_0 #define PART6_NZ_PAGE_SIZE_0 0 #endif #ifndef PART6_NZ_TSB_CONFIG_0 #define PART6_NZ_TSB_CONFIG_0 ((PART6_NZ_HWTEN_0 << 63) | (PART6_NZ_USECTX0_0 << 62) | (PART6_NZ_USECTX1_0 << 61) | (PART6_NZ_ADDR_0 & 0xffffffe000) | (PART6_NZ_RANOTPA_0 << 8) | (PART6_NZ_PAGE_SIZE_0 << 4) | (PART6_NZ_TSB_SIZE_0)) #endif define(part_6_nz_tsb_config_0, `0x'dnl' mpeval(PART6_NZ_TSB_CONFIG_0,16))dnl #ifndef PART6_Z_HWTEN_1 #define PART6_Z_HWTEN_1 1 #endif #ifndef PART6_Z_USECTX0_1 #define PART6_Z_USECTX0_1 0 #endif #ifndef PART6_Z_USECTX1_1 #define PART6_Z_USECTX1_1 0 #endif #ifndef PART6_Z_RANOTPA_1 #define PART6_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART6_Z_SUN4V_1 0 #else #define PART6_Z_SUN4V_1 1 #endif #ifndef PART6_Z_ADDR_1 #define PART6_Z_ADDR_1 0x33000000 #endif #ifndef PART6_Z_TSB_SIZE_1 #define PART6_Z_TSB_SIZE_1 1 #endif #ifndef PART6_Z_PAGE_SIZE_1 #define PART6_Z_PAGE_SIZE_1 0 #endif #ifndef PART6_Z_TSB_CONFIG_1 #define PART6_Z_TSB_CONFIG_1 ((PART6_Z_HWTEN_1 << 63) | (PART6_Z_USECTX0_1 << 62) | (PART6_Z_USECTX1_1 << 61) | (PART6_Z_ADDR_1 & 0xffffffe000) | (PART6_Z_RANOTPA_1 << 8) | (PART6_Z_PAGE_SIZE_1 << 4) | (PART6_Z_TSB_SIZE_1)) #endif define(part_6_z_tsb_config_1, `0x'dnl' mpeval(PART6_Z_TSB_CONFIG_1,16))dnl #ifndef PART6_NZ_HWTEN_1 #define PART6_NZ_HWTEN_1 1 #endif #ifndef PART6_NZ_USECTX0_1 #define PART6_NZ_USECTX0_1 0 #endif #ifndef PART6_NZ_USECTX1_1 #define PART6_NZ_USECTX1_1 0 #endif #ifndef PART6_NZ_RANOTPA_1 #define PART6_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART6_NZ_SUN4V_1 0 #else #define PART6_NZ_SUN4V_1 1 #endif #ifndef PART6_NZ_ADDR_1 #define PART6_NZ_ADDR_1 0x34000000 #endif #ifndef PART6_NZ_TSB_SIZE_1 #define PART6_NZ_TSB_SIZE_1 1 #endif #ifndef PART6_NZ_PAGE_SIZE_1 #define PART6_NZ_PAGE_SIZE_1 0 #endif #ifndef PART6_NZ_TSB_CONFIG_1 #define PART6_NZ_TSB_CONFIG_1 ((PART6_NZ_HWTEN_1 << 63) | (PART6_NZ_USECTX0_1 << 62) | (PART6_NZ_USECTX1_1 << 61) | (PART6_NZ_ADDR_1 & 0xffffffe000) | (PART6_NZ_RANOTPA_1 << 8) | (PART6_NZ_PAGE_SIZE_1 << 4) | (PART6_NZ_TSB_SIZE_1)) #endif define(part_6_nz_tsb_config_1, `0x'dnl' mpeval(PART6_NZ_TSB_CONFIG_1,16))dnl #ifndef PART6_Z_HWTEN_2 #define PART6_Z_HWTEN_2 1 #endif #ifndef PART6_Z_USECTX0_2 #define PART6_Z_USECTX0_2 0 #endif #ifndef PART6_Z_USECTX1_2 #define PART6_Z_USECTX1_2 0 #endif #ifndef PART6_Z_RANOTPA_2 #define PART6_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART6_Z_SUN4V_2 0 #else #define PART6_Z_SUN4V_2 1 #endif #ifndef PART6_Z_ADDR_2 #define PART6_Z_ADDR_2 0x35000000 #endif #ifndef PART6_Z_TSB_SIZE_2 #define PART6_Z_TSB_SIZE_2 1 #endif #ifndef PART6_Z_PAGE_SIZE_2 #define PART6_Z_PAGE_SIZE_2 0 #endif #ifndef PART6_Z_TSB_CONFIG_2 #define PART6_Z_TSB_CONFIG_2 ((PART6_Z_HWTEN_2 << 63) | (PART6_Z_USECTX0_2 << 62) | (PART6_Z_USECTX1_2 << 61) | (PART6_Z_ADDR_2 & 0xffffffe000) | (PART6_Z_RANOTPA_2 << 8) | (PART6_Z_PAGE_SIZE_2 << 4) | (PART6_Z_TSB_SIZE_2)) #endif define(part_6_z_tsb_config_2, `0x'dnl' mpeval(PART6_Z_TSB_CONFIG_2,16))dnl #ifndef PART6_NZ_HWTEN_2 #define PART6_NZ_HWTEN_2 1 #endif #ifndef PART6_NZ_USECTX0_2 #define PART6_NZ_USECTX0_2 0 #endif #ifndef PART6_NZ_USECTX1_2 #define PART6_NZ_USECTX1_2 0 #endif #ifndef PART6_NZ_RANOTPA_2 #define PART6_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART6_NZ_SUN4V_2 0 #else #define PART6_NZ_SUN4V_2 1 #endif #ifndef PART6_NZ_ADDR_2 #define PART6_NZ_ADDR_2 0x36000000 #endif #ifndef PART6_NZ_TSB_SIZE_2 #define PART6_NZ_TSB_SIZE_2 1 #endif #ifndef PART6_NZ_PAGE_SIZE_2 #define PART6_NZ_PAGE_SIZE_2 0 #endif #ifndef PART6_NZ_TSB_CONFIG_2 #define PART6_NZ_TSB_CONFIG_2 ((PART6_NZ_HWTEN_2 << 63) | (PART6_NZ_USECTX0_2 << 62) | (PART6_NZ_USECTX1_2 << 61) | (PART6_NZ_ADDR_2 & 0xffffffe000) | (PART6_NZ_RANOTPA_2 << 8) | (PART6_NZ_PAGE_SIZE_2 << 4) | (PART6_NZ_TSB_SIZE_2)) #endif define(part_6_nz_tsb_config_2, `0x'dnl' mpeval(PART6_NZ_TSB_CONFIG_2,16))dnl #ifndef PART6_Z_HWTEN_3 #define PART6_Z_HWTEN_3 1 #endif #ifndef PART6_Z_USECTX0_3 #define PART6_Z_USECTX0_3 0 #endif #ifndef PART6_Z_USECTX1_3 #define PART6_Z_USECTX1_3 0 #endif #ifndef PART6_Z_RANOTPA_3 #define PART6_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART6_Z_SUN4V_3 0 #else #define PART6_Z_SUN4V_3 1 #endif #ifndef PART6_Z_ADDR_3 #define PART6_Z_ADDR_3 0x37000000 #endif #ifndef PART6_Z_TSB_SIZE_3 #define PART6_Z_TSB_SIZE_3 1 #endif #ifndef PART6_Z_PAGE_SIZE_3 #define PART6_Z_PAGE_SIZE_3 0 #endif #ifndef PART6_Z_TSB_CONFIG_3 #define PART6_Z_TSB_CONFIG_3 ((PART6_Z_HWTEN_3 << 63) | (PART6_Z_USECTX0_3 << 62) | (PART6_Z_USECTX1_3 << 61) | (PART6_Z_ADDR_3 & 0xffffffe000) | (PART6_Z_RANOTPA_3 << 8) | (PART6_Z_PAGE_SIZE_3 << 4) | (PART6_Z_TSB_SIZE_3)) #endif define(part_6_z_tsb_config_3, `0x'dnl' mpeval(PART6_Z_TSB_CONFIG_3,16))dnl #ifndef PART6_NZ_HWTEN_3 #define PART6_NZ_HWTEN_3 1 #endif #ifndef PART6_NZ_USECTX0_3 #define PART6_NZ_USECTX0_3 0 #endif #ifndef PART6_NZ_USECTX1_3 #define PART6_NZ_USECTX1_3 0 #endif #ifndef PART6_NZ_RANOTPA_3 #define PART6_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART6_NZ_SUN4V_3 0 #else #define PART6_NZ_SUN4V_3 1 #endif #ifndef PART6_NZ_ADDR_3 #define PART6_NZ_ADDR_3 0x38000000 #endif #ifndef PART6_NZ_TSB_SIZE_3 #define PART6_NZ_TSB_SIZE_3 1 #endif #ifndef PART6_NZ_PAGE_SIZE_3 #define PART6_NZ_PAGE_SIZE_3 0 #endif #ifndef PART6_NZ_TSB_CONFIG_3 #define PART6_NZ_TSB_CONFIG_3 ((PART6_NZ_HWTEN_3 << 63) | (PART6_NZ_USECTX0_3 << 62) | (PART6_NZ_USECTX1_3 << 61) | (PART6_NZ_ADDR_3 & 0xffffffe000) | (PART6_NZ_RANOTPA_3 << 8) | (PART6_NZ_PAGE_SIZE_3 << 4) | (PART6_NZ_TSB_SIZE_3)) #endif define(part_6_nz_tsb_config_3, `0x'dnl' mpeval(PART6_NZ_TSB_CONFIG_3,16))dnl #ifndef PART6_PHY_OFF_X_0 #define PART6_PHY_OFF_X_0 1 #endif #ifndef PART6_PHY_OFF_P_0 #define PART6_PHY_OFF_P_0 0 #endif #ifndef PART6_PHY_OFF_W_0 #define PART6_PHY_OFF_W_0 0 #endif #ifndef PART6_PHY_OFF_0 #define PART6_PHY_OFF_0 ((PART_6_BASE) | (PART6_PHY_OFF_X_1 << 12) | (PART6_PHY_OFF_P_1 << 11) | (PART6_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART6_PHY_OFF_X_1 #define PART6_PHY_OFF_X_1 1 #endif #ifndef PART6_PHY_OFF_P_1 #define PART6_PHY_OFF_P_1 0 #endif #ifndef PART6_PHY_OFF_W_1 #define PART6_PHY_OFF_W_1 0 #endif #ifndef PART6_PHY_OFF_1 #define PART6_PHY_OFF_1 ((PART_6_BASE) | (PART6_PHY_OFF_X_1 << 12) | (PART6_PHY_OFF_P_1 << 11) | (PART6_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART6_PHY_OFF_X_2 #define PART6_PHY_OFF_X_2 1 #endif #ifndef PART6_PHY_OFF_P_2 #define PART6_PHY_OFF_P_2 0 #endif #ifndef PART6_PHY_OFF_W_2 #define PART6_PHY_OFF_W_2 0 #endif #ifndef PART6_PHY_OFF_2 #define PART6_PHY_OFF_2 ((PART_6_BASE) | (PART6_PHY_OFF_X_2 << 12) | (PART6_PHY_OFF_P_2 << 11) | (PART6_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART6_PHY_OFF_X_3 #define PART6_PHY_OFF_X_3 1 #endif #ifndef PART6_PHY_OFF_P_3 #define PART6_PHY_OFF_P_3 0 #endif #ifndef PART6_PHY_OFF_W_3 #define PART6_PHY_OFF_W_3 0 #endif #ifndef PART6_PHY_OFF_3 #define PART6_PHY_OFF_3 ((PART_6_BASE) | (PART6_PHY_OFF_X_3 << 12) | (PART6_PHY_OFF_P_3 << 11) | (PART6_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl 7 //////////////////////// #ifndef PART7_Z_HWTEN_0 #define PART7_Z_HWTEN_0 1 #endif #ifndef PART7_Z_USECTX0_0 #define PART7_Z_USECTX0_0 0 #endif #ifndef PART7_Z_USECTX1_0 #define PART7_Z_USECTX1_0 0 #endif #ifndef PART7_Z_RANOTPA_0 #define PART7_Z_RANOTPA_0 1 #endif #ifndef SUN4V #define PART7_Z_SUN4V_0 0 #else #define PART7_Z_SUN4V_0 1 #endif #ifndef PART7_Z_ADDR_0 #define PART7_Z_ADDR_0 0x39000000 #endif #ifndef PART7_Z_TSB_SIZE_0 #define PART7_Z_TSB_SIZE_0 1 #endif #ifndef PART7_Z_PAGE_SIZE_0 #define PART7_Z_PAGE_SIZE_0 0 #endif #ifndef PART7_Z_TSB_CONFIG_0 #define PART7_Z_TSB_CONFIG_0 ((PART7_Z_HWTEN_0 << 63) | (PART7_Z_USECTX0_0 << 62) | (PART7_Z_USECTX1_0 << 61) | (PART7_Z_ADDR_0 & 0xffffffe000) | (PART7_Z_RANOTPA_0 << 8) | (PART7_Z_PAGE_SIZE_0 << 4) | (PART7_Z_TSB_SIZE_0)) #endif define(part_7_z_tsb_config_0, `0x'dnl' mpeval(PART7_Z_TSB_CONFIG_0,16))dnl #ifndef PART7_NZ_HWTEN_0 #define PART7_NZ_HWTEN_0 1 #endif #ifndef PART7_NZ_USECTX0_0 #define PART7_NZ_USECTX0_0 0 #endif #ifndef PART7_NZ_USECTX1_0 #define PART7_NZ_USECTX1_0 0 #endif #ifndef PART7_NZ_RANOTPA_0 #define PART7_NZ_RANOTPA_0 1 #endif #ifndef SUN4V #define PART7_NZ_SUN4V_0 0 #else #define PART7_NZ_SUN4V_0 1 #endif #ifndef PART7_NZ_ADDR_0 #define PART7_NZ_ADDR_0 0x3a000000 #endif #ifndef PART7_NZ_TSB_SIZE_0 #define PART7_NZ_TSB_SIZE_0 1 #endif #ifndef PART7_NZ_PAGE_SIZE_0 #define PART7_NZ_PAGE_SIZE_0 0 #endif #ifndef PART7_NZ_TSB_CONFIG_0 #define PART7_NZ_TSB_CONFIG_0 ((PART7_NZ_HWTEN_0 << 63) | (PART7_NZ_USECTX0_0 << 62) | (PART7_NZ_USECTX1_0 << 61) | (PART7_NZ_ADDR_0 & 0xffffffe000) | (PART7_NZ_RANOTPA_0 << 8) | (PART7_NZ_PAGE_SIZE_0 << 4) | (PART7_NZ_TSB_SIZE_0)) #endif define(part_7_nz_tsb_config_0, `0x'dnl' mpeval(PART7_NZ_TSB_CONFIG_0,16))dnl #ifndef PART7_Z_HWTEN_1 #define PART7_Z_HWTEN_1 1 #endif #ifndef PART7_Z_USECTX0_1 #define PART7_Z_USECTX0_1 0 #endif #ifndef PART7_Z_USECTX1_1 #define PART7_Z_USECTX1_1 0 #endif #ifndef PART7_Z_RANOTPA_1 #define PART7_Z_RANOTPA_1 1 #endif #ifndef SUN4V #define PART7_Z_SUN4V_1 0 #else #define PART7_Z_SUN4V_1 1 #endif #ifndef PART7_Z_ADDR_1 #define PART7_Z_ADDR_1 0x3b000000 #endif #ifndef PART7_Z_TSB_SIZE_1 #define PART7_Z_TSB_SIZE_1 1 #endif #ifndef PART7_Z_PAGE_SIZE_1 #define PART7_Z_PAGE_SIZE_1 0 #endif #ifndef PART7_Z_TSB_CONFIG_1 #define PART7_Z_TSB_CONFIG_1 ((PART7_Z_HWTEN_1 << 63) | (PART7_Z_USECTX0_1 << 62) | (PART7_Z_USECTX1_1 << 61) | (PART7_Z_ADDR_1 & 0xffffffe000) | (PART7_Z_RANOTPA_1 << 8) | (PART7_Z_PAGE_SIZE_1 << 4) | (PART7_Z_TSB_SIZE_1)) #endif define(part_7_z_tsb_config_1, `0x'dnl' mpeval(PART7_Z_TSB_CONFIG_1,16))dnl #ifndef PART7_NZ_HWTEN_1 #define PART7_NZ_HWTEN_1 1 #endif #ifndef PART7_NZ_USECTX0_1 #define PART7_NZ_USECTX0_1 0 #endif #ifndef PART7_NZ_USECTX1_1 #define PART7_NZ_USECTX1_1 0 #endif #ifndef PART7_NZ_RANOTPA_1 #define PART7_NZ_RANOTPA_1 1 #endif #ifndef SUN4V #define PART7_NZ_SUN4V_1 0 #else #define PART7_NZ_SUN4V_1 1 #endif #ifndef PART7_NZ_ADDR_1 #define PART7_NZ_ADDR_1 0x3c000000 #endif #ifndef PART7_NZ_TSB_SIZE_1 #define PART7_NZ_TSB_SIZE_1 1 #endif #ifndef PART7_NZ_PAGE_SIZE_1 #define PART7_NZ_PAGE_SIZE_1 0 #endif #ifndef PART7_NZ_TSB_CONFIG_1 #define PART7_NZ_TSB_CONFIG_1 ((PART7_NZ_HWTEN_1 << 63) | (PART7_NZ_USECTX0_1 << 62) | (PART7_NZ_USECTX1_1 << 61) | (PART7_NZ_ADDR_1 & 0xffffffe000) | (PART7_NZ_RANOTPA_1 << 8) | (PART7_NZ_PAGE_SIZE_1 << 4) | (PART7_NZ_TSB_SIZE_1)) #endif define(part_7_nz_tsb_config_1, `0x'dnl' mpeval(PART7_NZ_TSB_CONFIG_1,16))dnl #ifndef PART7_Z_HWTEN_2 #define PART7_Z_HWTEN_2 1 #endif #ifndef PART7_Z_USECTX0_2 #define PART7_Z_USECTX0_2 0 #endif #ifndef PART7_Z_USECTX1_2 #define PART7_Z_USECTX1_2 0 #endif #ifndef PART7_Z_RANOTPA_2 #define PART7_Z_RANOTPA_2 1 #endif #ifndef SUN4V #define PART7_Z_SUN4V_2 0 #else #define PART7_Z_SUN4V_2 1 #endif #ifndef PART7_Z_ADDR_2 #define PART7_Z_ADDR_2 0x3d000000 #endif #ifndef PART7_Z_TSB_SIZE_2 #define PART7_Z_TSB_SIZE_2 1 #endif #ifndef PART7_Z_PAGE_SIZE_2 #define PART7_Z_PAGE_SIZE_2 0 #endif #ifndef PART7_Z_TSB_CONFIG_2 #define PART7_Z_TSB_CONFIG_2 ((PART7_Z_HWTEN_2 << 63) | (PART7_Z_USECTX0_2 << 62) | (PART7_Z_USECTX1_2 << 61) | (PART7_Z_ADDR_2 & 0xffffffe000) | (PART7_Z_RANOTPA_2 << 8) | (PART7_Z_PAGE_SIZE_2 << 4) | (PART7_Z_TSB_SIZE_2)) #endif define(part_7_z_tsb_config_2, `0x'dnl' mpeval(PART7_Z_TSB_CONFIG_2,16))dnl #ifndef PART7_NZ_HWTEN_2 #define PART7_NZ_HWTEN_2 1 #endif #ifndef PART7_NZ_USECTX0_2 #define PART7_NZ_USECTX0_2 0 #endif #ifndef PART7_NZ_USECTX1_2 #define PART7_NZ_USECTX1_2 0 #endif #ifndef PART7_NZ_RANOTPA_2 #define PART7_NZ_RANOTPA_2 1 #endif #ifndef SUN4V #define PART7_NZ_SUN4V_2 0 #else #define PART7_NZ_SUN4V_2 1 #endif #ifndef PART7_NZ_ADDR_2 #define PART7_NZ_ADDR_2 0x3e000000 #endif #ifndef PART7_NZ_TSB_SIZE_2 #define PART7_NZ_TSB_SIZE_2 1 #endif #ifndef PART7_NZ_PAGE_SIZE_2 #define PART7_NZ_PAGE_SIZE_2 0 #endif #ifndef PART7_NZ_TSB_CONFIG_2 #define PART7_NZ_TSB_CONFIG_2 ((PART7_NZ_HWTEN_2 << 63) | (PART7_NZ_USECTX0_2 << 62) | (PART7_NZ_USECTX1_2 << 61) | (PART7_NZ_ADDR_2 & 0xffffffe000) | (PART7_NZ_RANOTPA_2 << 8) | (PART7_NZ_PAGE_SIZE_2 << 4) | (PART7_NZ_TSB_SIZE_2)) #endif define(part_7_nz_tsb_config_2, `0x'dnl' mpeval(PART7_NZ_TSB_CONFIG_2,16))dnl #ifndef PART7_Z_HWTEN_3 #define PART7_Z_HWTEN_3 1 #endif #ifndef PART7_Z_USECTX0_3 #define PART7_Z_USECTX0_3 0 #endif #ifndef PART7_Z_USECTX1_3 #define PART7_Z_USECTX1_3 0 #endif #ifndef PART7_Z_RANOTPA_3 #define PART7_Z_RANOTPA_3 1 #endif #ifndef SUN4V #define PART7_Z_SUN4V_3 0 #else #define PART7_Z_SUN4V_3 1 #endif #ifndef PART7_Z_ADDR_3 #define PART7_Z_ADDR_3 0x3f000000 #endif #ifndef PART7_Z_TSB_SIZE_3 #define PART7_Z_TSB_SIZE_3 1 #endif #ifndef PART7_Z_PAGE_SIZE_3 #define PART7_Z_PAGE_SIZE_3 0 #endif #ifndef PART7_Z_TSB_CONFIG_3 #define PART7_Z_TSB_CONFIG_3 ((PART7_Z_HWTEN_3 << 63) | (PART7_Z_USECTX0_3 << 62) | (PART7_Z_USECTX1_3 << 61) | (PART7_Z_ADDR_3 & 0xffffffe000) | (PART7_Z_RANOTPA_3 << 8) | (PART7_Z_PAGE_SIZE_3 << 4) | (PART7_Z_TSB_SIZE_3)) #endif define(part_7_z_tsb_config_3, `0x'dnl' mpeval(PART7_Z_TSB_CONFIG_3,16))dnl #ifndef PART7_NZ_HWTEN_3 #define PART7_NZ_HWTEN_3 1 #endif #ifndef PART7_NZ_USECTX0_3 #define PART7_NZ_USECTX0_3 0 #endif #ifndef PART7_NZ_USECTX1_3 #define PART7_NZ_USECTX1_3 0 #endif #ifndef PART7_NZ_RANOTPA_3 #define PART7_NZ_RANOTPA_3 1 #endif #ifndef SUN4V #define PART7_NZ_SUN4V_3 0 #else #define PART7_NZ_SUN4V_3 1 #endif #ifndef PART7_NZ_ADDR_3 #define PART7_NZ_ADDR_3 0x40000000 #endif #ifndef PART7_NZ_TSB_SIZE_3 #define PART7_NZ_TSB_SIZE_3 1 #endif #ifndef PART7_NZ_PAGE_SIZE_3 #define PART7_NZ_PAGE_SIZE_3 0 #endif #ifndef PART7_NZ_TSB_CONFIG_3 #define PART7_NZ_TSB_CONFIG_3 ((PART7_NZ_HWTEN_3 << 63) | (PART7_NZ_USECTX0_3 << 62) | (PART7_NZ_USECTX1_3 << 61) | (PART7_NZ_ADDR_3 & 0xffffffe000) | (PART7_NZ_RANOTPA_3 << 8) | (PART7_NZ_PAGE_SIZE_3 << 4) | (PART7_NZ_TSB_SIZE_3)) #endif define(part_7_nz_tsb_config_3, `0x'dnl' mpeval(PART7_NZ_TSB_CONFIG_3,16))dnl #ifndef PART7_PHY_OFF_X_0 #define PART7_PHY_OFF_X_0 1 #endif #ifndef PART7_PHY_OFF_P_0 #define PART7_PHY_OFF_P_0 0 #endif #ifndef PART7_PHY_OFF_W_0 #define PART7_PHY_OFF_W_0 0 #endif #ifndef PART7_PHY_OFF_0 #define PART7_PHY_OFF_0 ((PART_7_BASE) | (PART7_PHY_OFF_X_1 << 12) | (PART7_PHY_OFF_P_1 << 11) | (PART7_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART7_PHY_OFF_X_1 #define PART7_PHY_OFF_X_1 1 #endif #ifndef PART7_PHY_OFF_P_1 #define PART7_PHY_OFF_P_1 0 #endif #ifndef PART7_PHY_OFF_W_1 #define PART7_PHY_OFF_W_1 0 #endif #ifndef PART7_PHY_OFF_1 #define PART7_PHY_OFF_1 ((PART_7_BASE) | (PART7_PHY_OFF_X_1 << 12) | (PART7_PHY_OFF_P_1 << 11) | (PART7_PHY_OFF_W_1 << 10) | (0x0000000000000000)) #endif #ifndef PART7_PHY_OFF_X_2 #define PART7_PHY_OFF_X_2 1 #endif #ifndef PART7_PHY_OFF_P_2 #define PART7_PHY_OFF_P_2 0 #endif #ifndef PART7_PHY_OFF_W_2 #define PART7_PHY_OFF_W_2 0 #endif #ifndef PART7_PHY_OFF_2 #define PART7_PHY_OFF_2 ((PART_7_BASE) | (PART7_PHY_OFF_X_2 << 12) | (PART7_PHY_OFF_P_2 << 11) | (PART7_PHY_OFF_W_2 << 10) | (0x0000000000000000)) #endif #ifndef PART7_PHY_OFF_X_3 #define PART7_PHY_OFF_X_3 1 #endif #ifndef PART7_PHY_OFF_P_3 #define PART7_PHY_OFF_P_3 0 #endif #ifndef PART7_PHY_OFF_W_3 #define PART7_PHY_OFF_W_3 0 #endif #ifndef PART7_PHY_OFF_3 #define PART7_PHY_OFF_3 ((PART_7_BASE) | (PART7_PHY_OFF_X_3 << 12) | (PART7_PHY_OFF_P_3 << 11) | (PART7_PHY_OFF_W_3 << 10) | (0x0000000000000000)) #endif dnl Done //////////////////////// #if !(PART0_NZ_RANOTPA_0 & PART0_Z_RANOTPA_0 & PART0_NZ_RANOTPA_1 & PART0_Z_RANOTPA_1 & PART0_NZ_RANOTPA_2 & PART0_Z_RANOTPA_2 & PART0_NZ_RANOTPA_3 & PART0_Z_RANOTPA_3 & PART1_NZ_RANOTPA_0 & PART1_Z_RANOTPA_0 & PART1_NZ_RANOTPA_1 & PART1_Z_RANOTPA_1 & PART1_NZ_RANOTPA_2 & PART1_Z_RANOTPA_2 & PART1_NZ_RANOTPA_3 & PART1_Z_RANOTPA_3 & PART2_NZ_RANOTPA_0 & PART2_Z_RANOTPA_0 & PART2_NZ_RANOTPA_1 & PART2_Z_RANOTPA_1 & PART2_NZ_RANOTPA_2 & PART2_Z_RANOTPA_2 & PART2_NZ_RANOTPA_3 & PART2_Z_RANOTPA_3 & PART3_NZ_RANOTPA_0 & PART3_Z_RANOTPA_0 & PART3_NZ_RANOTPA_1 & PART3_Z_RANOTPA_1 & PART3_NZ_RANOTPA_2 & PART3_Z_RANOTPA_2 & PART3_NZ_RANOTPA_3 & PART3_Z_RANOTPA_3 & PART4_NZ_RANOTPA_0 & PART4_Z_RANOTPA_0 & PART4_NZ_RANOTPA_1 & PART4_Z_RANOTPA_1 & PART4_NZ_RANOTPA_2 & PART4_Z_RANOTPA_2 & PART4_NZ_RANOTPA_3 & PART4_Z_RANOTPA_3 & PART5_NZ_RANOTPA_0 & PART5_Z_RANOTPA_0 & PART5_NZ_RANOTPA_1 & PART5_Z_RANOTPA_1 & PART5_NZ_RANOTPA_2 & PART5_Z_RANOTPA_2 & PART5_NZ_RANOTPA_3 & PART5_Z_RANOTPA_3 & PART6_NZ_RANOTPA_0 & PART6_Z_RANOTPA_0 & PART6_NZ_RANOTPA_1 & PART6_Z_RANOTPA_1 & PART6_NZ_RANOTPA_2 & PART6_Z_RANOTPA_2 & PART6_NZ_RANOTPA_3 & PART6_Z_RANOTPA_3 & PART7_NZ_RANOTPA_0 & PART7_Z_RANOTPA_0 & PART7_NZ_RANOTPA_1 & PART7_Z_RANOTPA_1 & PART7_NZ_RANOTPA_2 & PART7_Z_RANOTPA_2 & PART7_NZ_RANOTPA_3 & PART7_Z_RANOTPA_3) #define SOME_TSB_PANOTRA #endif #ifndef NO_DECLARE_TSB #ifdef GOLDFINGER #ifdef PART_0_USED MIDAS_TSB_LINK part_0_tsb_link PART_0_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_0_ctx_zero_tsb_config_0 part_0_z_tsb_config_0 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_ctx_nonzero_tsb_config_0 part_0_nz_tsb_config_0 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_ctx_zero_tsb_config_1 part_0_z_tsb_config_1 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_ctx_nonzero_tsb_config_1 part_0_nz_tsb_config_1 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_ctx_zero_tsb_config_2 part_0_z_tsb_config_2 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_ctx_nonzero_tsb_config_2 part_0_nz_tsb_config_2 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_ctx_zero_tsb_config_3 part_0_z_tsb_config_3 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_ctx_nonzero_tsb_config_3 part_0_nz_tsb_config_3 link=part_0_tsb_link ttefmt=sun4v #else MIDAS_TSB part_0_i_ctx_zero_ps0_tsb part_0_z_tsb_config_0 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_i_ctx_nonzero_ps0_tsb part_0_nz_tsb_config_0 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_d_ctx_zero_ps0_tsb part_0_z_tsb_config_1 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_d_ctx_nonzero_ps0_tsb part_0_nz_tsb_config_1 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_i_ctx_zero_ps1_tsb part_0_z_tsb_config_2 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_i_ctx_nonzero_ps1_tsb part_0_nz_tsb_config_2 link=part_0_tsb_link ttefmt=sun4v MIDAS_TSB part_0_d_ctx_zero_ps1_tsb part_0_z_tsb_config_3 link=part_0_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_0_d_ctx_nonzero_ps1_tsb part_0_nz_tsb_config_3 link=part_0_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_1_USED MIDAS_TSB_LINK part_1_tsb_link PART_1_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_1_ctx_zero_tsb_config_0 part_1_z_tsb_config_0 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_ctx_nonzero_tsb_config_0 part_1_nz_tsb_config_0 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_ctx_zero_tsb_config_1 part_1_z_tsb_config_1 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_ctx_nonzero_tsb_config_1 part_1_nz_tsb_config_1 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_ctx_zero_tsb_config_2 part_1_z_tsb_config_2 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_ctx_nonzero_tsb_config_2 part_1_nz_tsb_config_2 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_ctx_zero_tsb_config_3 part_1_z_tsb_config_3 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_ctx_nonzero_tsb_config_3 part_1_nz_tsb_config_3 link=part_1_tsb_link ttefmt=sun4v #else MIDAS_TSB part_1_i_ctx_zero_ps0_tsb part_1_z_tsb_config_0 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_i_ctx_nonzero_ps0_tsb part_1_nz_tsb_config_0 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_d_ctx_zero_ps0_tsb part_1_z_tsb_config_1 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_d_ctx_nonzero_ps0_tsb part_1_nz_tsb_config_1 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_i_ctx_zero_ps1_tsb part_1_z_tsb_config_2 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_i_ctx_nonzero_ps1_tsb part_1_nz_tsb_config_2 link=part_1_tsb_link ttefmt=sun4v MIDAS_TSB part_1_d_ctx_zero_ps1_tsb part_1_z_tsb_config_3 link=part_1_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_1_d_ctx_nonzero_ps1_tsb part_1_nz_tsb_config_3 link=part_1_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_2_USED MIDAS_TSB_LINK part_2_tsb_link PART_2_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_2_ctx_zero_tsb_config_0 part_2_z_tsb_config_0 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_ctx_nonzero_tsb_config_0 part_2_nz_tsb_config_0 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_ctx_zero_tsb_config_1 part_2_z_tsb_config_1 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_ctx_nonzero_tsb_config_1 part_2_nz_tsb_config_1 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_ctx_zero_tsb_config_2 part_2_z_tsb_config_2 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_ctx_nonzero_tsb_config_2 part_2_nz_tsb_config_2 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_ctx_zero_tsb_config_3 part_2_z_tsb_config_3 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_ctx_nonzero_tsb_config_3 part_2_nz_tsb_config_3 link=part_2_tsb_link ttefmt=sun4v #else MIDAS_TSB part_2_i_ctx_zero_ps0_tsb part_2_z_tsb_config_0 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_i_ctx_nonzero_ps0_tsb part_2_nz_tsb_config_0 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_d_ctx_zero_ps0_tsb part_2_z_tsb_config_1 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_d_ctx_nonzero_ps0_tsb part_2_nz_tsb_config_1 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_i_ctx_zero_ps1_tsb part_2_z_tsb_config_2 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_i_ctx_nonzero_ps1_tsb part_2_nz_tsb_config_2 link=part_2_tsb_link ttefmt=sun4v MIDAS_TSB part_2_d_ctx_zero_ps1_tsb part_2_z_tsb_config_3 link=part_2_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_2_d_ctx_nonzero_ps1_tsb part_2_nz_tsb_config_3 link=part_2_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_3_USED MIDAS_TSB_LINK part_3_tsb_link PART_3_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_3_ctx_zero_tsb_config_0 part_3_z_tsb_config_0 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_ctx_nonzero_tsb_config_0 part_3_nz_tsb_config_0 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_ctx_zero_tsb_config_1 part_3_z_tsb_config_1 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_ctx_nonzero_tsb_config_1 part_3_nz_tsb_config_1 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_ctx_zero_tsb_config_2 part_3_z_tsb_config_2 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_ctx_nonzero_tsb_config_2 part_3_nz_tsb_config_2 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_ctx_zero_tsb_config_3 part_3_z_tsb_config_3 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_ctx_nonzero_tsb_config_3 part_3_nz_tsb_config_3 link=part_3_tsb_link ttefmt=sun4v #else MIDAS_TSB part_3_i_ctx_zero_ps0_tsb part_3_z_tsb_config_0 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_i_ctx_nonzero_ps0_tsb part_3_nz_tsb_config_0 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_d_ctx_zero_ps0_tsb part_3_z_tsb_config_1 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_d_ctx_nonzero_ps0_tsb part_3_nz_tsb_config_1 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_i_ctx_zero_ps1_tsb part_3_z_tsb_config_2 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_i_ctx_nonzero_ps1_tsb part_3_nz_tsb_config_2 link=part_3_tsb_link ttefmt=sun4v MIDAS_TSB part_3_d_ctx_zero_ps1_tsb part_3_z_tsb_config_3 link=part_3_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_3_d_ctx_nonzero_ps1_tsb part_3_nz_tsb_config_3 link=part_3_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_4_USED MIDAS_TSB_LINK part_4_tsb_link PART_4_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_4_ctx_zero_tsb_config_0 part_4_z_tsb_config_0 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_ctx_nonzero_tsb_config_0 part_4_nz_tsb_config_0 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_ctx_zero_tsb_config_1 part_4_z_tsb_config_1 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_ctx_nonzero_tsb_config_1 part_4_nz_tsb_config_1 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_ctx_zero_tsb_config_2 part_4_z_tsb_config_2 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_ctx_nonzero_tsb_config_2 part_4_nz_tsb_config_2 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_ctx_zero_tsb_config_3 part_4_z_tsb_config_3 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_ctx_nonzero_tsb_config_3 part_4_nz_tsb_config_3 link=part_4_tsb_link ttefmt=sun4v #else MIDAS_TSB part_4_i_ctx_zero_ps0_tsb part_4_z_tsb_config_0 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_i_ctx_nonzero_ps0_tsb part_4_nz_tsb_config_0 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_d_ctx_zero_ps0_tsb part_4_z_tsb_config_1 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_d_ctx_nonzero_ps0_tsb part_4_nz_tsb_config_1 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_i_ctx_zero_ps1_tsb part_4_z_tsb_config_2 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_i_ctx_nonzero_ps1_tsb part_4_nz_tsb_config_2 link=part_4_tsb_link ttefmt=sun4v MIDAS_TSB part_4_d_ctx_zero_ps1_tsb part_4_z_tsb_config_3 link=part_4_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_4_d_ctx_nonzero_ps1_tsb part_4_nz_tsb_config_3 link=part_4_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_5_USED MIDAS_TSB_LINK part_5_tsb_link PART_5_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_5_ctx_zero_tsb_config_0 part_5_z_tsb_config_0 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_ctx_nonzero_tsb_config_0 part_5_nz_tsb_config_0 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_ctx_zero_tsb_config_1 part_5_z_tsb_config_1 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_ctx_nonzero_tsb_config_1 part_5_nz_tsb_config_1 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_ctx_zero_tsb_config_2 part_5_z_tsb_config_2 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_ctx_nonzero_tsb_config_2 part_5_nz_tsb_config_2 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_ctx_zero_tsb_config_3 part_5_z_tsb_config_3 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_ctx_nonzero_tsb_config_3 part_5_nz_tsb_config_3 link=part_5_tsb_link ttefmt=sun4v #else MIDAS_TSB part_5_i_ctx_zero_ps0_tsb part_5_z_tsb_config_0 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_i_ctx_nonzero_ps0_tsb part_5_nz_tsb_config_0 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_d_ctx_zero_ps0_tsb part_5_z_tsb_config_1 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_d_ctx_nonzero_ps0_tsb part_5_nz_tsb_config_1 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_i_ctx_zero_ps1_tsb part_5_z_tsb_config_2 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_i_ctx_nonzero_ps1_tsb part_5_nz_tsb_config_2 link=part_5_tsb_link ttefmt=sun4v MIDAS_TSB part_5_d_ctx_zero_ps1_tsb part_5_z_tsb_config_3 link=part_5_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_5_d_ctx_nonzero_ps1_tsb part_5_nz_tsb_config_3 link=part_5_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_6_USED MIDAS_TSB_LINK part_6_tsb_link PART_6_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_6_ctx_zero_tsb_config_0 part_6_z_tsb_config_0 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_ctx_nonzero_tsb_config_0 part_6_nz_tsb_config_0 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_ctx_zero_tsb_config_1 part_6_z_tsb_config_1 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_ctx_nonzero_tsb_config_1 part_6_nz_tsb_config_1 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_ctx_zero_tsb_config_2 part_6_z_tsb_config_2 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_ctx_nonzero_tsb_config_2 part_6_nz_tsb_config_2 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_ctx_zero_tsb_config_3 part_6_z_tsb_config_3 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_ctx_nonzero_tsb_config_3 part_6_nz_tsb_config_3 link=part_6_tsb_link ttefmt=sun4v #else MIDAS_TSB part_6_i_ctx_zero_ps0_tsb part_6_z_tsb_config_0 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_i_ctx_nonzero_ps0_tsb part_6_nz_tsb_config_0 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_d_ctx_zero_ps0_tsb part_6_z_tsb_config_1 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_d_ctx_nonzero_ps0_tsb part_6_nz_tsb_config_1 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_i_ctx_zero_ps1_tsb part_6_z_tsb_config_2 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_i_ctx_nonzero_ps1_tsb part_6_nz_tsb_config_2 link=part_6_tsb_link ttefmt=sun4v MIDAS_TSB part_6_d_ctx_zero_ps1_tsb part_6_z_tsb_config_3 link=part_6_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_6_d_ctx_nonzero_ps1_tsb part_6_nz_tsb_config_3 link=part_6_tsb_link ttefmt=sun4v #endif #endif #ifdef PART_7_USED MIDAS_TSB_LINK part_7_tsb_link PART_7_LINK_AREA_BASE_ADDR #ifndef USE_N1_TSB_NAMES MIDAS_TSB part_7_ctx_zero_tsb_config_0 part_7_z_tsb_config_0 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_ctx_nonzero_tsb_config_0 part_7_nz_tsb_config_0 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_ctx_zero_tsb_config_1 part_7_z_tsb_config_1 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_ctx_nonzero_tsb_config_1 part_7_nz_tsb_config_1 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_ctx_zero_tsb_config_2 part_7_z_tsb_config_2 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_ctx_nonzero_tsb_config_2 part_7_nz_tsb_config_2 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_ctx_zero_tsb_config_3 part_7_z_tsb_config_3 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_ctx_nonzero_tsb_config_3 part_7_nz_tsb_config_3 link=part_7_tsb_link ttefmt=sun4v #else MIDAS_TSB part_7_i_ctx_zero_ps0_tsb part_7_z_tsb_config_0 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_i_ctx_nonzero_ps0_tsb part_7_nz_tsb_config_0 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_d_ctx_zero_ps0_tsb part_7_z_tsb_config_1 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_d_ctx_nonzero_ps0_tsb part_7_nz_tsb_config_1 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_i_ctx_zero_ps1_tsb part_7_z_tsb_config_2 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_i_ctx_nonzero_ps1_tsb part_7_nz_tsb_config_2 link=part_7_tsb_link ttefmt=sun4v MIDAS_TSB part_7_d_ctx_zero_ps1_tsb part_7_z_tsb_config_3 link=part_7_tsb_link force_ctx_zero ttefmt=sun4v MIDAS_TSB part_7_d_ctx_nonzero_ps1_tsb part_7_nz_tsb_config_3 link=part_7_tsb_link ttefmt=sun4v #endif #endif #else part_0_ctx_zero_tsb_config_0 part_0_z_tsb_config_0 part_0_ctx_nonzero_tsb_config_0 part_0_nz_tsb_config_0 part_0_ctx_zero_tsb_config_1 part_0_z_tsb_config_1 part_0_ctx_nonzero_tsb_config_1 part_0_nz_tsb_config_1 part_0_ctx_zero_tsb_config_2 part_0_z_tsb_config_2 part_0_ctx_nonzero_tsb_config_2 part_0_nz_tsb_config_2 part_0_ctx_zero_tsb_config_3 part_0_z_tsb_config_3 part_0_ctx_nonzero_tsb_config_3 part_0_nz_tsb_config_3 part_1_ctx_zero_tsb_config_0 part_1_z_tsb_config_0 part_1_ctx_nonzero_tsb_config_0 part_1_nz_tsb_config_0 part_1_ctx_zero_tsb_config_1 part_1_z_tsb_config_1 part_1_ctx_nonzero_tsb_config_1 part_1_nz_tsb_config_1 part_1_ctx_zero_tsb_config_2 part_1_z_tsb_config_2 part_1_ctx_nonzero_tsb_config_2 part_1_nz_tsb_config_2 part_1_ctx_zero_tsb_config_3 part_1_z_tsb_config_3 part_1_ctx_nonzero_tsb_config_3 part_1_nz_tsb_config_3 part_2_ctx_zero_tsb_config_0 part_2_z_tsb_config_0 part_2_ctx_nonzero_tsb_config_0 part_2_nz_tsb_config_0 part_2_ctx_zero_tsb_config_1 part_2_z_tsb_config_1 part_2_ctx_nonzero_tsb_config_1 part_2_nz_tsb_config_1 part_2_ctx_zero_tsb_config_2 part_2_z_tsb_config_2 part_2_ctx_nonzero_tsb_config_2 part_2_nz_tsb_config_2 part_2_ctx_zero_tsb_config_3 part_2_z_tsb_config_3 part_2_ctx_nonzero_tsb_config_3 part_2_nz_tsb_config_3 part_3_ctx_zero_tsb_config_0 part_3_z_tsb_config_0 part_3_ctx_nonzero_tsb_config_0 part_3_nz_tsb_config_0 part_3_ctx_zero_tsb_config_1 part_3_z_tsb_config_1 part_3_ctx_nonzero_tsb_config_1 part_3_nz_tsb_config_1 part_3_ctx_zero_tsb_config_2 part_3_z_tsb_config_2 part_3_ctx_nonzero_tsb_config_2 part_3_nz_tsb_config_2 part_3_ctx_zero_tsb_config_3 part_3_z_tsb_config_3 part_3_ctx_nonzero_tsb_config_3 part_3_nz_tsb_config_3 part_4_ctx_zero_tsb_config_0 part_4_z_tsb_config_0 part_4_ctx_nonzero_tsb_config_0 part_4_nz_tsb_config_0 part_4_ctx_zero_tsb_config_1 part_4_z_tsb_config_1 part_4_ctx_nonzero_tsb_config_1 part_4_nz_tsb_config_1 part_4_ctx_zero_tsb_config_2 part_4_z_tsb_config_2 part_4_ctx_nonzero_tsb_config_2 part_4_nz_tsb_config_2 part_4_ctx_zero_tsb_config_3 part_4_z_tsb_config_3 part_4_ctx_nonzero_tsb_config_3 part_4_nz_tsb_config_3 part_5_ctx_zero_tsb_config_0 part_5_z_tsb_config_0 part_5_ctx_nonzero_tsb_config_0 part_5_nz_tsb_config_0 part_5_ctx_zero_tsb_config_1 part_5_z_tsb_config_1 part_5_ctx_nonzero_tsb_config_1 part_5_nz_tsb_config_1 part_5_ctx_zero_tsb_config_2 part_5_z_tsb_config_2 part_5_ctx_nonzero_tsb_config_2 part_5_nz_tsb_config_2 part_5_ctx_zero_tsb_config_3 part_5_z_tsb_config_3 part_5_ctx_nonzero_tsb_config_3 part_5_nz_tsb_config_3 part_6_ctx_zero_tsb_config_0 part_6_z_tsb_config_0 part_6_ctx_nonzero_tsb_config_0 part_6_nz_tsb_config_0 part_6_ctx_zero_tsb_config_1 part_6_z_tsb_config_1 part_6_ctx_nonzero_tsb_config_1 part_6_nz_tsb_config_1 part_6_ctx_zero_tsb_config_2 part_6_z_tsb_config_2 part_6_ctx_nonzero_tsb_config_2 part_6_nz_tsb_config_2 part_6_ctx_zero_tsb_config_3 part_6_z_tsb_config_3 part_6_ctx_nonzero_tsb_config_3 part_6_nz_tsb_config_3 part_7_ctx_zero_tsb_config_0 part_7_z_tsb_config_0 part_7_ctx_nonzero_tsb_config_0 part_7_nz_tsb_config_0 part_7_ctx_zero_tsb_config_1 part_7_z_tsb_config_1 part_7_ctx_nonzero_tsb_config_1 part_7_nz_tsb_config_1 part_7_ctx_zero_tsb_config_2 part_7_z_tsb_config_2 part_7_ctx_nonzero_tsb_config_2 part_7_nz_tsb_config_2 part_7_ctx_zero_tsb_config_3 part_7_z_tsb_config_3 part_7_ctx_nonzero_tsb_config_3 part_7_nz_tsb_config_3 #endif #endif