// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: fc_niu_tx_P0P1_2DMA.diaglist // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ //KH //KH //KH FcNiuTx_McPort1_DMA15_PktCnt25 FcNiuBasicTx.s //KH //KH FcNiuTx_McPort1_DMA15_PktCnt25_Xlate FcNiuBasicTx.s //KH //KH //KH //KH //KH //KH FcNiuTx_McPort1_PktCnt1_Jumbo FcNiuBasicTx.s //KH //KH // FcNiuTx_MULTI_P0DMA_0001_P1DMA_0002 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P0DMA_0001_P1DMA_0004 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P0DMA_0001_P1DMA_0008 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P0DMA_0001_P1DMA_0010_TX_GATHER tx_MULTI_PORT_DMA_rand.s // // FcNiuTx_MULTI_P0DMA_0001_P1DMA_0020 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0040 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0080 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0100 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0200 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0400 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_0800 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_1000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_2000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_4000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_8000 tx_MULTI_PORT_DMA_rand.s // **************************************************************************** // **************************************************************************** // P0P1 Multi_Port/Mluti_DMA (Port0 DMA1-15, Port1 DMA0) // **************************************************************************** // FcNiuTx_MULTI_P1DMA_0001_P0DMA_0002 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P1DMA_0001_P0DMA_0004 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P1DMA_0001_P0DMA_0008 tx_MULTI_PORT_DMA_rand.s // FcNiuTx_MULTI_P1DMA_0001_P0DMA_0010_TX_GATHER tx_MULTI_PORT_DMA_rand.s // // FcNiuTx_MULTI_P1DMA_0001_P0DMA_0020 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0040 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0080 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0100 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0200 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0400 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_0800 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_1000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_2000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P1DMA_0001_P0DMA_4000 tx_MULTI_PORT_DMA_rand.s FcNiuTx_MULTI_P0DMA_0001_P1DMA_8000 tx_MULTI_PORT_DMA_rand.s // ****************************************************************************