// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: dmu_cov_ports_binds.vrhpal // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #inc "dmu_cov_inc.pal"; #ifndef __DMU_PORTS_VRH__ #define __DMU_PORTS_VRH__ #include //////////////////////////////////////////////////////////////// // The clock port //////////////////////////////////////////////////////////////// // #ifndef FC_COVERAGE port dmu_clk_port { clk; cmp_diag_done; } port dmu_cov_pio_port { clk; hdr_vld; mmu_vld; data; ack_vld; ack_tag; } bind dmu_cov_pio_port dmu_cov_pio_dw_bind { clk dmu_cov_dmupio.clk; hdr_vld dmu_cov_dmupio.ncu_dmu_pio_hdr_vld; mmu_vld dmu_cov_dmupio.ncu_dmu_mmu_addr_vld; data dmu_cov_dmupio.ncu_dmu_pio_data; ack_vld dmu_cov_dmupio.dmu_ncu_wrack_vld; ack_tag dmu_cov_dmupio.dmu_ncu_wrack_tag; } // #endif port dmu_intctl_fsm_port { dmu_intcnt_fsm_state; } bind dmu_intctl_fsm_port dmu_intctl_fsm_bind { dmu_intcnt_fsm_state { dmu_int_controller_if.intctl3, dmu_int_controller_if.intctl2, dmu_int_controller_if.intctl1, dmu_int_controller_if.intctl0 }; } #endif