// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: sio_dmu_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#inc "dmu_cov_inc.pal";

// sio_dmu_this_cmd is ignored by DSN, any hdr_vld indicates dma rd return
// hdr_vld is covered by the other sio egress VCO's

// DMCTag[15] = 0 for DMA/Int (DI) = 1 for DMA Tablewalk (TW)
sample dmu_siu_intf_eHdr_Cmd_cov (dmu_id_out[15])
{
  state DI (1'b0);
  state TW (1'b1);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_UE_cov (sio_dmu_rd_return_ue) 
{
  m_state UE (0:1);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_DE_cov (sio_dmu_rd_return_de) 
{
  m_state DE (0:1);
  cov_weight = 0;
}

// make sure all bits of the dmc tag field are toggled.
// Exclude bit [15] because that determines DI or TW
sample dmu_siu_intf_eHdr_DMCtag_cov (dmu_id_out[14:0]) 
{
. &toggle(15);
  cov_weight = 0;
}

sample dmu_siu_intf_eHdr_CtagECC_cov (sio_dmu_rd_return_ctagecc) 
{
. &toggle(6);
  cov_weight = 0;
}

cross dmu_siu_intf_eHdr_Cmd_UE_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                      dmu_siu_intf_eHdr_UE_cov);

cross dmu_siu_intf_eHdr_Cmd_DE_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                      dmu_siu_intf_eHdr_DE_cov);
        
cross dmu_siu_intf_eHdr_Cmd_DMCtag_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                          dmu_siu_intf_eHdr_DMCtag_cov);

cross dmu_siu_intf_eHdr_Cmd_CtagECC_cross (dmu_siu_intf_eHdr_Cmd_cov,
                                           dmu_siu_intf_eHdr_CtagECC_cov);