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// OpenSPARC T2 Processor File: mcusat_ch0_fbd_cmd_a_sample.vrhpal
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state s_sync (5'b10000);
state s_scr  (5'b01000);
state s_act  (5'b00100);
state s_wr   (5'b00011);
state s_rd   (5'b00010);
state s_nop  (5'b00000);

wildcard bad_state s_invalid_sync (5'b1xxxx) if (dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_a_cmd != dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_sync_cmd);
wildcard bad_state s_invalid_scr (5'b01xxx) if (dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_a_cmd != dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_scr_cmd);
wildcard bad_state s_invalid_act (5'b00100) if (dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_a_cmd != dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_act_cmd);
wildcard bad_state s_invalid_rdwr (5'b0001x) if (dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_a_cmd != dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_rdwr_cmd);
wildcard bad_state s_invalid_nop (5'b00000) if (dram_coverage_ifc_dram_clk.dram_Ch0_fbdic_a_cmd != 0);