// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_rx_cov_if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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// it under the terms of the GNU General Public License as published by
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
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// choice is available it will apply instead, Sun elects to use only 
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// ========== Copyright Header End ============================================
#include <vera_defines.vrh>

#include "neptune_defines.vri"

#define CF_CK_IN_TIMING PSAMPLE #-1
#define CF_CK_OUT_TIMING PHOLD #0
#define CF_CK_CLK_TIMING  CLOCK

/*******************************************************************************************/
/*                                                                                         */
/*              Coverage Object Interface for Control FIFO                                 */
/*                                                                                         */
/*******************************************************************************************/

interface control_fifo_port0_cov_if {
  input [129:0] control_fifo_data               CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat0";
  input         control_fifo_ful_pkt            CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_ful_pkt0";
  input         control_fifo_err                CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat_err0";
  input         control_fifo_ack                CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_ack0";
  output        control_fifo_req                CF_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req0";
  input         clk                             CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}

interface control_fifo_port1_cov_if {
  input [129:0] control_fifo_data               CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat1";
  input         control_fifo_ful_pkt            CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_ful_pkt1";
  input         control_fifo_err                CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat_err1";
  input         control_fifo_ack                CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_ack1";
  output        control_fifo_req                CF_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req1";
  input         clk                             CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}

port control_fifo_cov_port{
  control_fifo_data;
  control_fifo_ful_pkt;
  control_fifo_err;
  control_fifo_ack;
  control_fifo_req;
  clk;
}

bind control_fifo_cov_port control_fifo_p0{
        control_fifo_data               control_fifo_port0_cov_if.control_fifo_data;
        control_fifo_ful_pkt            control_fifo_port0_cov_if.control_fifo_ful_pkt;
        control_fifo_err                control_fifo_port0_cov_if.control_fifo_err;
        control_fifo_ack                control_fifo_port0_cov_if.control_fifo_ack;
        control_fifo_req                control_fifo_port0_cov_if.control_fifo_req;
        clk                             control_fifo_port0_cov_if.clk;
}

bind control_fifo_cov_port control_fifo_p1{
        control_fifo_data               control_fifo_port1_cov_if.control_fifo_data;
        control_fifo_ful_pkt            control_fifo_port1_cov_if.control_fifo_ful_pkt;
        control_fifo_err                control_fifo_port1_cov_if.control_fifo_err;
        control_fifo_ack                control_fifo_port1_cov_if.control_fifo_ack;
        control_fifo_req                control_fifo_port1_cov_if.control_fifo_req;
        clk                             control_fifo_port1_cov_if.clk;
}


/*******************************************************************************************/
/*                                                                                         */
/*              Coverage Object Interface for Tx FIFO                                      */
/*                                                                                         */
/*******************************************************************************************/

interface niu_coverage_txc_1024_port0_RO_RAM
{
input           clk             CLOCK           verilog_node TXC_DUV_PATH_P0_RO_RAM.clk";
input           cmp_diag_done   PSAMPLE;

input           read_sig        CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.cs_rd";
input [9:0]     read_ptr        CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.addr_rd";
input           write_sig       CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.wt_enable";
input [9:0]     write_ptr       CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.addr_wt";
}

interface niu_coverage_txc_1024_port0_SF_RAM
{
input           clk             CLOCK           verilog_node TXC_DUV_PATH_P0_SF_RAM.clk";
input           cmp_diag_done   PSAMPLE;

input           read_sig        CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.cs_rd";
input [9:0]     read_ptr        CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.addr_rd";
input           write_sig       CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.wt_enable";
input [9:0]     write_ptr       CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.addr_wt";
}

interface niu_coverage_mac_xpcs_state_machine
{
input           clk             CLOCK           verilog_node MAC_DUV_PATH.mac_core.mac_2ports.xmac_2pcs_core_port0.xpcs.xpcs_rxio.rx_clk";
input [7:0]    cs_state         CF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_core.mac_2ports.xmac_2pcs_core_port0.xpcs.xpcs_pio.csr_ebuffer_state";
}

/*******************************************************************************************/
/*                                                                                         */
/*              Coverage Object Interface for Errors                                       */
/*                                                                                         */
/*******************************************************************************************/

interface niu_coverage_err_det
{
input           clk                   CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
input           cmp_diag_done         PSAMPLE;
input           control_fifo_err0     CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat_err0";
input           control_fifo_err1     CF_CK_IN_TIMING verilog_node  RXC_DUV_PATH.zcp_dmc_dat_err1";
}