// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpxorder.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_CPXORDER_IF_VRH
#define INC_CPXORDER_IF_VRH

interface cpxorder {

    input ccx_rclk CLOCK hdl_node "tb_top.cpu.l2clk";
    input ccx_gdbginit_l PSAMPLE #-1 hdl_node "tb_top.cpu.rst_l2_por_";
    
    // cpxport 0,1,2,3,4,5,6,7

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc0_data_cx2";
#ifdef CCX_GATE
    input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl0__ard__dir_a";
#else
    input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl0.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc1_data_cx2";
#ifdef CCX_GATE
    input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl1__ard__dir_a";
#else
    input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl1.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc2_data_cx2";
#ifdef CCX_GATE
    input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl2__ard__dir_a";
#else
    input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl2.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc3_data_cx2";
#ifdef CCX_GATE
    input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl3__ard__dir_a";
#else
    input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl3.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc4_data_cx2";
#ifdef CCX_GATE
    input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl4__ard__dir_a";
#else
    input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl4.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc5_data_cx2";
#ifdef CCX_GATE
    input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl5__ard__dir_a";
#else
    input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl5.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc6_data_cx2";
#ifdef CCX_GATE
    input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl6__ard__dir_a";
#else
    input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl6.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc7_data_cx2";
#ifdef CCX_GATE
    input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl7__ard__dir_a";
#else
    input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl7.ard.dir_a";
#endif


    // l2port 0,1,2,3, 4, 5, 6, 7
    input [7:0] sctag_cpx_req_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_req_cq";
    input sctag_cpx_atom_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag0_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_req_cq";
    input sctag_cpx_atom_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag1_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_req_cq";
    input sctag_cpx_atom_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag2_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_req_cq";
    input sctag_cpx_atom_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag3_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_req_cq";
    input sctag_cpx_atom_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag4_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_req_cq";
    input sctag_cpx_atom_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag5_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_req_cq";
    input sctag_cpx_atom_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag6_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_req_cq";
    input sctag_cpx_atom_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag7_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_data_ca";

    //input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_req_cq";
#ifdef CCX_GATE
    input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "{tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_7_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_6_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_5_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_4_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_3_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_2_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_1_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_0_}";
#else
    input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.io_cpx_req_cq_d1";
#endif
    input sctag_cpx_atom_cq_8 PSAMPLE #-1 hdl_node "1'b0";
    input [7:0] cpx_sctag_grant_cx_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx_io_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_data_ca";

}

#endif