// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tx_port_drr_if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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#ifdef N2_FC
#define OUTPUT_EDGE PHOLD
#define INPUT_EDGE PSAMPLE #-1
#define OUTPUT_SKEW #1
#endif

#ifdef N2_IOS
#include "top_defines.vrh"
#endif


#include "neptune_defines.vri"

 #ifndef RXC_SAT
   #ifndef MAC_SAT
     #ifdef NIU_GATE
        #define RTX_PATH tb_top.cpu.rtx
        #define TXC_PATH NIU_DUV_PATH.rtx
        #define TXC0_PATH NIU_DUV_PATH.rtx
        #define TXC1_PATH NIU_DUV_PATH.rtx
     #else
        #define TXC_PATH NIU_DUV_PATH.rtx.txc
        #define TXC0_PATH NIU_DUV_PATH.rtx.txc.niu_txc_debug
        #define TXC1_PATH NIU_DUV_PATH.rtx.txc.niu_txc_debug
     #endif
   #else //else for MAC_SAT
     #define TXC_PATH NIU_DUV_PATH.rtx.txc
     #define TXC0_PATH NIU_DUV_PATH.rtx.txc
     #define TXC1_PATH NIU_DUV_PATH.rtx.txc
   #endif
  #else //else for RXC_SAT
   #define TXC_PATH NIU_DUV_PATH.rtx.txc
   #define TXC0_PATH NIU_DUV_PATH.rtx.txc
   #define TXC1_PATH NIU_DUV_PATH.rtx.txc
  #endif

interface txc_port0_drr_if
{
#ifdef NIU_GATE
    input  clk CLOCK verilog_node TXC_PATH.iol2clk";
#else
#ifdef NIU_SYSTEMC_T2
    input  clk CLOCK verilog_node NIU_DUV_PATH.rtx_txc_niu_clk";
#else
    input  clk CLOCK verilog_node TXC_PATH.niu_clk";
#endif
#endif

  #ifndef RXC_SAT
    #ifdef NIU_GATE
       #ifdef POST_LAYOUT
	input  latch_activedma INPUT_EDGE verilog_node TXC0_PATH.txc_niu_txc_packetengine0_niu_txc_drr_engine_niu_txc_drr_arbiter_n438ASThfnNet23960";

	input  [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port0_contextactivelist_15_, tb_top.cpu.rtx.txc_port0_contextactivelist_14_, tb_top.cpu.rtx.txc_port0_contextactivelist_13_, tb_top.cpu.rtx.txc_port0_contextactivelist_12_, tb_top.cpu.rtx.txc_port0_contextactivelist_11_, tb_top.cpu.rtx.txc_port0_contextactivelist_10_, tb_top.cpu.rtx.txc_port0_contextactivelist_9_, tb_top.cpu.rtx.txc_port0_contextactivelist_8_, tb_top.cpu.rtx.txc_port0_contextactivelist_7_, tb_top.cpu.rtx.txc_port0_contextactivelist_6_, tb_top.cpu.rtx.txc_port0_contextactivelist_5_, tb_top.cpu.rtx.txc_port0_contextactivelist_4_, tb_top.cpu.rtx.txc_port0_contextactivelist_3_, tb_top.cpu.rtx.txc_port0_contextactivelist_2_, tb_top.cpu.rtx.txc_port0_contextactivelist_1_, tb_top.cpu.rtx.txc_port0_contextactivelist_0_}";

       #else	// if pre-layout gate netlist NOTE: now all lower case in pre-to_1.0
	// When defining LatchActiveDMA use the clken for the *port0_ContextActiveList* flip flops
       input  latch_activedma INPUT_EDGE verilog_node TXC0_PATH.n105044";

       input  [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port0_contextactivelist_15_, tb_top.cpu.rtx.txc_port0_contextactivelist_14_, tb_top.cpu.rtx.txc_port0_contextactivelist_13_, tb_top.cpu.rtx.txc_port0_contextactivelist_12_, tb_top.cpu.rtx.txc_port0_contextactivelist_11_, tb_top.cpu.rtx.txc_port0_contextactivelist_10_, tb_top.cpu.rtx.txc_port0_contextactivelist_9_, tb_top.cpu.rtx.txc_port0_contextactivelist_8_, tb_top.cpu.rtx.txc_port0_contextactivelist_7_, tb_top.cpu.rtx.txc_port0_contextactivelist_6_, tb_top.cpu.rtx.txc_port0_contextactivelist_5_, tb_top.cpu.rtx.txc_port0_contextactivelist_4_, tb_top.cpu.rtx.txc_port0_contextactivelist_3_, tb_top.cpu.rtx.txc_port0_contextactivelist_2_, tb_top.cpu.rtx.txc_port0_contextactivelist_1_, tb_top.cpu.rtx.txc_port0_contextactivelist_0_}";
      #endif	// switch between Pre and Post layout

// The following inputs were defined for RTL nodes which are not in the netlist
// tying them to 0's for now.  SOME TEST WILL FAIL BECAUSE OF THIS HENCE THESE
//  SIGNALS WILL CONTRIBUTE TO A GATE VS. RTL MISMATCH!!!!    VJH
	input  add_credit INPUT_EDGE verilog_node "1'b0";
	input  clr_eoflist INPUT_EDGE verilog_node "1'b0";
	input	[23:0] eoflist INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.dmc_txc_dma15_eoflist, tb_top.cpu.rtx.dmc_txc_dma14_eoflist,tb_top.cpu.rtx.dmc_txc_dma13_eoflist,tb_top.cpu.rtx.dmc_txc_dma12_eoflist,tb_top.cpu.rtx.dmc_txc_dma11_eoflist,tb_top.cpu.rtx.dmc_txc_dma10_eoflist,tb_top.cpu.rtx.dmc_txc_dma9_eoflist,tb_top.cpu.rtx.dmc_txc_dma8_eoflist, tb_top.cpu.rtx.dmc_txc_dma7_eoflist, tb_top.cpu.rtx.dmc_txc_dma6_eoflist, tb_top.cpu.rtx.dmc_txc_dma5_eoflist, tb_top.cpu.rtx.dmc_txc_dma4_eoflist, tb_top.cpu.rtx.dmc_txc_dma3_eoflist, tb_top.cpu.rtx.dmc_txc_dma2_eoflist, tb_top.cpu.rtx.dmc_txc_dma1_eoflist, tb_top.cpu.rtx.dmc_txc_dma0_eoflist}";

    #else  // if GATEs vs RTL
      #ifdef NIU_SYSTEMC_T2
       input  latch_activedma INPUT_EDGE verilog_node "1'b0";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node "24'b0";
       input  add_credit INPUT_EDGE verilog_node "1'b0";
       input  clr_eoflist INPUT_EDGE verilog_node "1'b0";
      #else
       input  latch_activedma INPUT_EDGE verilog_node TXC0_PATH.Port0_LatchActiveDMA";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node TXC0_PATH.Port0_ContextActiveList";
       input  add_credit INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter.AddCreditToContext";
       input  clr_eoflist INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter.ClrDeficitForEofList";
      #endif
    #ifdef NIU_SYSTEMC_T2
       input  [23:0] eoflist INPUT_EDGE verilog_node "24'h0";
    #else
       input  [23:0] eoflist INPUT_EDGE verilog_node "{8'h0,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma15_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma14_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma13_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma12_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma11_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma10_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma9_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma8_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma7_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma6_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma5_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma4_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma3_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma2_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma1_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma0_eoflist}"; 
    #endif // NIU_SYSTEMC_T2
    #endif
  #endif 

}

interface txc_port1_drr_if
{
#ifdef NIU_GATE
    input  clk CLOCK verilog_node TXC_PATH.iol2clk";
#else
  #ifdef NIU_SYSTEMC_T2
    input  clk CLOCK verilog_node NIU_DUV_PATH.rtx_txc_niu_clk";
  #else
    input  clk CLOCK verilog_node TXC_PATH.niu_clk";
  #endif // NIU_SYSTEMC_T2
#endif

  #ifndef RXC_SAT
    #ifdef NIU_GATE
       #ifdef POST_LAYOUT
       input  latch_activedma INPUT_EDGE verilog_node TXC1_PATH.txc_niu_txc_packetengine1_niu_txc_drr_engine_niu_txc_drr_arbiter_n438ASThfnNet23961";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port1_contextactivelist_15_, tb_top.cpu.rtx.txc_port1_contextactivelist_14_, tb_top.cpu.rtx.txc_port1_contextactivelist_13_, tb_top.cpu.rtx.txc_port1_contextactivelist_12_, tb_top.cpu.rtx.txc_port1_contextactivelist_11_, tb_top.cpu.rtx.txc_port1_contextactivelist_10_, tb_top.cpu.rtx.txc_port1_contextactivelist_9_, tb_top.cpu.rtx.txc_port1_contextactivelist_8_, tb_top.cpu.rtx.txc_port1_contextactivelist_7_, tb_top.cpu.rtx.txc_port1_contextactivelist_6_, tb_top.cpu.rtx.txc_port1_contextactivelist_5_, tb_top.cpu.rtx.txc_port1_contextactivelist_4_, tb_top.cpu.rtx.txc_port1_contextactivelist_3_, tb_top.cpu.rtx.txc_port1_contextactivelist_2_, tb_top.cpu.rtx.txc_port1_contextactivelist_1_, tb_top.cpu.rtx.txc_port1_contextactivelist_0_}"; // if RTL
        #else // If pre-layout gates
	// When defining LatchActiveDMA use the clken for the *port1_ContextActiveList* flip flops
       input  latch_activedma INPUT_EDGE verilog_node TXC1_PATH.n105047";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port1_contextactivelist_15_, tb_top.cpu.rtx.txc_port1_contextactivelist_14_, tb_top.cpu.rtx.txc_port1_contextactivelist_13_, tb_top.cpu.rtx.txc_port1_contextactivelist_12_, tb_top.cpu.rtx.txc_port1_contextactivelist_11_, tb_top.cpu.rtx.txc_port1_contextactivelist_10_, tb_top.cpu.rtx.txc_port1_contextactivelist_9_, tb_top.cpu.rtx.txc_port1_contextactivelist_8_, tb_top.cpu.rtx.txc_port1_contextactivelist_7_, tb_top.cpu.rtx.txc_port1_contextactivelist_6_, tb_top.cpu.rtx.txc_port1_contextactivelist_5_, tb_top.cpu.rtx.txc_port1_contextactivelist_4_, tb_top.cpu.rtx.txc_port1_contextactivelist_3_, tb_top.cpu.rtx.txc_port1_contextactivelist_2_, tb_top.cpu.rtx.txc_port1_contextactivelist_1_, tb_top.cpu.rtx.txc_port1_contextactivelist_0_}";

        #endif  // Pre vs. Post gates

// The following inputs were defined for RTL nodes which are not in the netlist
// tying them to 0's for now.  SOME TEST WILL FAIL BECAUSE OF THIS HENCE THESE
//  SIGNALS WILL CONTRIBUTE TO A GATE VS. RTL MISMATCH!!!!    VJH
	input  add_credit INPUT_EDGE verilog_node "1'b0";
	input  clr_eoflist INPUT_EDGE verilog_node "1'b0";
	input	[23:0] eoflist INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.dmc_txc_dma15_eoflist, tb_top.cpu.rtx.dmc_txc_dma14_eoflist,tb_top.cpu.rtx.dmc_txc_dma13_eoflist,tb_top.cpu.rtx.dmc_txc_dma12_eoflist,tb_top.cpu.rtx.dmc_txc_dma11_eoflist,tb_top.cpu.rtx.dmc_txc_dma10_eoflist,tb_top.cpu.rtx.dmc_txc_dma9_eoflist,tb_top.cpu.rtx.dmc_txc_dma8_eoflist, tb_top.cpu.rtx.dmc_txc_dma7_eoflist, tb_top.cpu.rtx.dmc_txc_dma6_eoflist, tb_top.cpu.rtx.dmc_txc_dma5_eoflist, tb_top.cpu.rtx.dmc_txc_dma4_eoflist, tb_top.cpu.rtx.dmc_txc_dma3_eoflist, tb_top.cpu.rtx.dmc_txc_dma2_eoflist, tb_top.cpu.rtx.dmc_txc_dma1_eoflist, tb_top.cpu.rtx.dmc_txc_dma0_eoflist}";

    #else // if RTL
      #ifdef NIU_SYSTEMC_T2
       input  latch_activedma INPUT_EDGE verilog_node "1'b0";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node "24'b0";
       input  add_credit INPUT_EDGE verilog_node "1'b0";
       input  clr_eoflist INPUT_EDGE verilog_node "1'b0";
      #else
       input  latch_activedma INPUT_EDGE verilog_node TXC1_PATH.Port1_LatchActiveDMA";
       input  [23:0] activeListDMA INPUT_EDGE verilog_node TXC1_PATH.Port1_ContextActiveList";
       input  add_credit INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine1.niu_txc_drr_engine.niu_txc_drr_arbiter.AddCreditToContext";
       input  clr_eoflist INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine1.niu_txc_drr_engine.niu_txc_drr_arbiter.ClrDeficitForEofList";
      #endif
    #ifdef NIU_SYSTEMC_T2
       input  [23:0] eoflist INPUT_EDGE verilog_node "24'h0";
    #else
       input  [23:0] eoflist INPUT_EDGE verilog_node "{8'h0,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma15_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma14_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma13_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma12_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma11_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma10_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma9_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma8_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma7_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma6_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma5_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma4_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma3_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma2_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma1_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma0_eoflist}"; 
    #endif
 #endif
#endif 

}

port txc_port_drr{

       clk;
  #ifndef RXC_SAT
       latch_activedma;
       activeListDMA;
       add_credit;
       clr_eoflist;
       eoflist;
  #endif
}
bind txc_port_drr txc_port0_drr_bind {
	clk txc_port0_drr_if.clk;
  #ifndef RXC_SAT
	latch_activedma txc_port0_drr_if.latch_activedma;
	activeListDMA txc_port0_drr_if.activeListDMA;
        add_credit txc_port0_drr_if.add_credit;
        clr_eoflist txc_port0_drr_if.clr_eoflist;
        eoflist txc_port0_drr_if.eoflist; 
  #endif
}


bind txc_port_drr txc_port1_drr_bind {
        clk txc_port1_drr_if.clk;
  #ifndef RXC_SAT
        latch_activedma txc_port1_drr_if.latch_activedma;
        activeListDMA txc_port1_drr_if.activeListDMA;
        add_credit txc_port1_drr_if.add_credit;
        clr_eoflist txc_port1_drr_if.clr_eoflist;
        eoflist txc_port1_drr_if.eoflist; 
  #endif
}