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// 
// OpenSPARC T2 Processor File: siumon_ports_binds.vrhpal
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#inc "siu_inc.pal"

#ifndef INC_SIUMON_PORTS_BINDS_VRH
#define INC_SIUMON_PORTS_BINDS_VRH

#include "top_defines.vrh"

port ncumon_port {
   iol2clk;
   syn_vld;
   syn_data;
   niu_a_pei;
   niu_a_pe;
   niu_d_pei;
   niu_d_pe;
   niu_ctag_uei;
   niu_ctag_ue;
   niu_ctag_cei;
   niu_ctag_ce;
   dmu_a_pei;
   dmu_a_pe;
   dmu_d_pei;
   dmu_d_pe;
   dmu_ctag_uei;
   dmu_ctag_ue;
   dmu_ctag_cei;
   dmu_ctag_ce;
   sio_ctag_uei;
   sio_ctag_ue;
   sio_ctag_cei;
   sio_ctag_ce;
}

bind ncumon_port ncumon_bind {
   iol2clk      ncu_mon.iol2clk;
   syn_vld      ncu_mon.syn_vld;
   syn_data     ncu_mon.syn_data;
   niu_a_pei    ncu_mon.niu_a_pei;
   niu_a_pe     ncu_mon.niu_a_pe;
   niu_d_pei    ncu_mon.niu_d_pei;
   niu_d_pe     ncu_mon.niu_d_pe;
   niu_ctag_uei ncu_mon.niu_ctag_uei;
   niu_ctag_ue  ncu_mon.niu_ctag_ue;
   niu_ctag_cei ncu_mon.niu_ctag_cei;
   niu_ctag_ce  ncu_mon.niu_ctag_ce;
   dmu_a_pei    ncu_mon.dmu_a_pei;
   dmu_a_pe     ncu_mon.dmu_a_pe;
   dmu_d_pei    ncu_mon.dmu_d_pei;
   dmu_d_pe     ncu_mon.dmu_d_pe;
   dmu_ctag_uei ncu_mon.dmu_ctag_uei;
   dmu_ctag_ue  ncu_mon.dmu_ctag_ue;
   dmu_ctag_cei ncu_mon.dmu_ctag_cei;
   dmu_ctag_ce  ncu_mon.dmu_ctag_ce;
   sio_ctag_uei ncu_mon.sio_ctag_uei;
   sio_ctag_ue  ncu_mon.sio_ctag_ue;
   sio_ctag_cei ncu_mon.sio_ctag_cei;
   sio_ctag_ce  ncu_mon.sio_ctag_ce;
}

port niumon_port {
   clk;
   sreq;
   bypass;
   sdatareq;
   sdata;
   sparity;
   oqdq;
   bqdq;
   rreq;
   rdatareq;
   rdata;
   rparity;
   niu_dq;
}

bind niumon_port niumon_bind {
   clk 		niu_mon.clk;
   sreq		niu_mon.sreq;
   bypass	niu_mon.bypass;
   sdatareq	niu_mon.sdatareq;
   sdata	niu_mon.sdata;
   sparity	niu_mon.sparity;
   oqdq         niu_mon.oqdq;
   bqdq         niu_mon.bqdq;
   rreq         niu_mon.rreq;
   rdatareq     niu_mon.rdatareq;
   rdata        niu_mon.rdata;
   rparity      niu_mon.rparity;
   niu_dq 	niu_mon.niu_dq;
}

port dmumon_port {
	clk;
	sreq;
	bypass;
	sdatareq;
	datareq16;
	sdata;
	sparity;
	be;
	beparity;
	wrack_vld;
	wrack_tag;
	rreq;
	//rdatareq;
	rdata;
	rparity;
}

bind dmumon_port dmumon_bind {
	clk		dmu_mon.clk;
	sreq		dmu_mon.sreq;
	bypass		dmu_mon.bypass;
	sdatareq	dmu_mon.sdatareq;
	datareq16	dmu_mon.datareq16;
	sdata		dmu_mon.sdata;
	sparity		dmu_mon.sparity;
	be		dmu_mon.be;
	beparity	dmu_mon.beparity;
	wrack_vld	dmu_mon.wrack_vld;
	wrack_tag	dmu_mon.wrack_tag;
	rreq		dmu_mon.rreq;
	//rdatareq	dmu_mon.rdatareq;
	rdata		dmu_mon.rdata;
	rparity		dmu_mon.rparity;
}

port l2_mon_port {
	clk;
	req_vld;
	req;
	ecc;
	ctag_vld;
	data;
	parity;
	ue_err;
	iq_dequeue;
	wib_dequeue;
        dbg_req;
}

.for($b=0; $b<$BANKS; $b++) {
bind l2_mon_port l2_mon_bind${b} {
	clk		l2_${b}_mon.clk;
	req_vld		l2_${b}_mon.req_vld;
	req		l2_${b}_mon.req;
	ecc		l2_${b}_mon.ecc;
	ctag_vld	l2_${b}_mon.ctag_vld;
	data		l2_${b}_mon.data;
	parity		l2_${b}_mon.parity;
	ue_err		l2_${b}_mon.ue_err;
	iq_dequeue	l2_${b}_mon.iq_dequeue;
	wib_dequeue	l2_${b}_mon.wib_dequeue;
	dbg_req	        l2_${b}_mon.dbg_req;
}
.}

#endif