// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: cluster_hdr.bind.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #ifndef INC_CLUSTER_HDR_BIND_VRI #define INC_CLUSTER_HDR_BIND_VRI #include "cluster_hdr.port.vri" #include "cluster_hdr.if.vri" // // WARNING: this file is generated by script gen_cluster_hdr.pl. Do not modify. // //####################################################### //### bind DR and IO2X clock ports for ccu_mon ###### //####################################################### bind CLKGEN_port clkgen_ccumon_dr_bind { aclk__gclk void; aclk_wmr__gclk void; array_wr_inhibit__gclk void; bclk__gclk void; ccu_cmp_slow_sync_en__gclk void; ccu_div_ph__gclk void; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk void; clk_ext__gclk void; cluster_arst_l__gclk void; cluster_div_en__gclk void; cmp_slow_sync_en__gclk void; dr_sync_en__gclk void; gclk void; io2x_sync_en__gclk void; l2clk__gclk void; pce_ov__gclk void; por___gclk void; rst_por___gclk void; rst_wmr___gclk void; rst_wmr_protect__gclk void; scan_en__gclk void; scan_in__gclk void; scan_out__gclk void; slow_cmp_sync_en__gclk void; tcu_aclk__gclk void; tcu_atpg_mode__gclk void; tcu_bclk__gclk void; tcu_clk_stop__gclk void; tcu_div_bypass__gclk void; tcu_pce_ov__gclk void; tcu_wr_inhibit__gclk void; wmr___gclk void; wmr_protect__gclk void; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; aclk__l2clk void; aclk_wmr__l2clk void; array_wr_inhibit__l2clk void; bclk__l2clk void; cmp_slow_sync_en__l2clk void; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ccumon_dr_l2clk_if.l2clk; pce_ov__l2clk void; por___l2clk void; scan_out__l2clk void; slow_cmp_sync_en__l2clk void; wmr___l2clk void; wmr_protect__l2clk void; } bind CLKGEN_port clkgen_ccumon_io2x_bind { aclk__gclk void; aclk_wmr__gclk void; array_wr_inhibit__gclk void; bclk__gclk void; ccu_cmp_slow_sync_en__gclk void; ccu_div_ph__gclk void; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk void; clk_ext__gclk void; cluster_arst_l__gclk void; cluster_div_en__gclk void; cmp_slow_sync_en__gclk void; dr_sync_en__gclk void; gclk void; io2x_sync_en__gclk void; l2clk__gclk void; pce_ov__gclk void; por___gclk void; rst_por___gclk void; rst_wmr___gclk void; rst_wmr_protect__gclk void; scan_en__gclk void; scan_in__gclk void; scan_out__gclk void; slow_cmp_sync_en__gclk void; tcu_aclk__gclk void; tcu_atpg_mode__gclk void; tcu_bclk__gclk void; tcu_clk_stop__gclk void; tcu_div_bypass__gclk void; tcu_pce_ov__gclk void; tcu_wr_inhibit__gclk void; wmr___gclk void; wmr_protect__gclk void; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; aclk__l2clk void; aclk_wmr__l2clk void; array_wr_inhibit__l2clk void; bclk__l2clk void; cmp_slow_sync_en__l2clk void; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ccumon_io2x_l2clk_if.l2clk; pce_ov__l2clk void; por___l2clk void; scan_out__l2clk void; slow_cmp_sync_en__l2clk void; wmr___l2clk void; wmr_protect__l2clk void; } //####################################################### //### port bindings for blocks in TCU SAT ### //####################################################### //----- port binding for clkgen_ccu_cmp ----- bind CLKGEN_port clkgen_ccu_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_ccu_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_ccu_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_ccu_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_ccu_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_ccu_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_ccu_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_ccu_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_ccu_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_ccu_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_ccu_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_ccu_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_ccu_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_ccu_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_ccu_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_ccu_cmp_gclk_if.pce_ov; por___gclk clkgen_ccu_cmp_gclk_if.por_; rst_por___gclk clkgen_ccu_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_ccu_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_ccu_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_ccu_cmp_gclk_if.scan_en; scan_in__gclk clkgen_ccu_cmp_gclk_if.scan_in; scan_out__gclk clkgen_ccu_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_ccu_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_ccu_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_ccu_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_ccu_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_ccu_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_ccu_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_ccu_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_ccu_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_ccu_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_ccu_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_ccu_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_ccu_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_ccu_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_ccu_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_ccu_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ccu_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_ccu_cmp_l2clk_if.pce_ov; por___l2clk clkgen_ccu_cmp_l2clk_if.por_; scan_out__l2clk clkgen_ccu_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_ccu_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_ccu_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_ccu_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_ccu_io ----- bind CLKGEN_port clkgen_ccu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_ccu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_ccu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_ccu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_ccu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_ccu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_ccu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_ccu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_ccu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_ccu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_ccu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_ccu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_ccu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_ccu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_ccu_io_gclk_if.l2clk; pce_ov__gclk clkgen_ccu_io_gclk_if.pce_ov; por___gclk clkgen_ccu_io_gclk_if.por_; rst_por___gclk clkgen_ccu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_ccu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_ccu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_ccu_io_gclk_if.scan_en; scan_in__gclk clkgen_ccu_io_gclk_if.scan_in; scan_out__gclk clkgen_ccu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_ccu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_ccu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_ccu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_ccu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_ccu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_ccu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_ccu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_ccu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_ccu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_ccu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_ccu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_ccu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_ccu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_ccu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_ccu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ccu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_ccu_io_l2clk_if.pce_ov; por___l2clk clkgen_ccu_io_l2clk_if.por_; scan_out__l2clk clkgen_ccu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_ccu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_ccu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_ccu_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_db0_cmp ----- bind CLKGEN_port clkgen_db0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_db0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_db0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_db0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_db0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_db0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_db0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_db0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_db0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_db0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_db0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_db0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_db0_cmp_gclk_if.dr_sync_en; gclk clkgen_db0_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_db0_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_db0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_db0_cmp_gclk_if.pce_ov; por___gclk clkgen_db0_cmp_gclk_if.por_; rst_por___gclk clkgen_db0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_db0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_db0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_db0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_db0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_db0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_db0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_db0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_db0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_db0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_db0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_db0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_db0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_db0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_db0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_db0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_db0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_db0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_db0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_db0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_db0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_db0_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_db0_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_db0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_db0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_db0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_db0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_db0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_db0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_db0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_db0_io ----- bind CLKGEN_port clkgen_db0_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_db0_io_gclk_if.aclk; aclk_wmr__gclk clkgen_db0_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_db0_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_db0_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_db0_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_db0_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_db0_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_db0_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_db0_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_db0_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_db0_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_db0_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_db0_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_db0_io_gclk_if.l2clk; pce_ov__gclk clkgen_db0_io_gclk_if.pce_ov; por___gclk clkgen_db0_io_gclk_if.por_; rst_por___gclk clkgen_db0_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_db0_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_db0_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_db0_io_gclk_if.scan_en; scan_in__gclk clkgen_db0_io_gclk_if.scan_in; scan_out__gclk clkgen_db0_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_db0_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_db0_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_db0_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_db0_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_db0_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_db0_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_db0_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_db0_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_db0_io_gclk_if.wmr_; wmr_protect__gclk clkgen_db0_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_db0_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_db0_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_db0_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_db0_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_db0_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_db0_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_db0_io_l2clk_if.pce_ov; por___l2clk clkgen_db0_io_l2clk_if.por_; scan_out__l2clk clkgen_db0_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_db0_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_db0_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_db0_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_db1_cmp ----- bind CLKGEN_port clkgen_db1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_db1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_db1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_db1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_db1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_db1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_db1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_db1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_db1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_db1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_db1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_db1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_db1_cmp_gclk_if.dr_sync_en; gclk clkgen_db1_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_db1_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_db1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_db1_cmp_gclk_if.pce_ov; por___gclk clkgen_db1_cmp_gclk_if.por_; rst_por___gclk clkgen_db1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_db1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_db1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_db1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_db1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_db1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_db1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_db1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_db1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_db1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_db1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_db1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_db1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_db1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_db1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_db1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_db1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_db1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_db1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_db1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_db1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_db1_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_db1_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_db1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_db1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_db1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_db1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_db1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_db1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_db1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_db1_io ----- bind CLKGEN_port clkgen_db1_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_db1_io_gclk_if.aclk; aclk_wmr__gclk clkgen_db1_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_db1_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_db1_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_db1_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_db1_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_db1_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_db1_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_db1_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_db1_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_db1_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_db1_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_db1_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_db1_io_gclk_if.l2clk; pce_ov__gclk clkgen_db1_io_gclk_if.pce_ov; por___gclk clkgen_db1_io_gclk_if.por_; rst_por___gclk clkgen_db1_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_db1_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_db1_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_db1_io_gclk_if.scan_en; scan_in__gclk clkgen_db1_io_gclk_if.scan_in; scan_out__gclk clkgen_db1_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_db1_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_db1_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_db1_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_db1_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_db1_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_db1_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_db1_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_db1_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_db1_io_gclk_if.wmr_; wmr_protect__gclk clkgen_db1_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_db1_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_db1_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_db1_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_db1_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_db1_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_db1_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_db1_io_l2clk_if.pce_ov; por___l2clk clkgen_db1_io_l2clk_if.por_; scan_out__l2clk clkgen_db1_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_db1_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_db1_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_db1_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_efu_io ----- bind CLKGEN_port clkgen_efu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_efu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_efu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_efu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_efu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_efu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_efu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_efu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_efu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_efu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_efu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_efu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_efu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_efu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_efu_io_gclk_if.l2clk; pce_ov__gclk clkgen_efu_io_gclk_if.pce_ov; por___gclk clkgen_efu_io_gclk_if.por_; rst_por___gclk clkgen_efu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_efu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_efu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_efu_io_gclk_if.scan_en; scan_in__gclk clkgen_efu_io_gclk_if.scan_in; scan_out__gclk clkgen_efu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_efu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_efu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_efu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_efu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_efu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_efu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_efu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_efu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_efu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_efu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_efu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_efu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_efu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_efu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_efu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_efu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_efu_io_l2clk_if.pce_ov; por___l2clk clkgen_efu_io_l2clk_if.por_; scan_out__l2clk clkgen_efu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_efu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_efu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_efu_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_efu_cmp ----- bind CLKGEN_port clkgen_efu_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_efu_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_efu_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_efu_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_efu_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_efu_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_efu_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_efu_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_efu_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_efu_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_efu_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_efu_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_efu_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_efu_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_efu_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_efu_cmp_gclk_if.pce_ov; por___gclk clkgen_efu_cmp_gclk_if.por_; rst_por___gclk clkgen_efu_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_efu_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_efu_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_efu_cmp_gclk_if.scan_en; scan_in__gclk clkgen_efu_cmp_gclk_if.scan_in; scan_out__gclk clkgen_efu_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_efu_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_efu_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_efu_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_efu_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_efu_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_efu_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_efu_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_efu_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_efu_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_efu_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_efu_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_efu_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_efu_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_efu_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_efu_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_efu_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_efu_cmp_l2clk_if.pce_ov; por___l2clk clkgen_efu_cmp_l2clk_if.por_; scan_out__l2clk clkgen_efu_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_efu_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_efu_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_efu_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mio_0_cmp ----- bind CLKGEN_port clkgen_mio_0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mio_0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mio_0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mio_0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mio_0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mio_0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mio_0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mio_0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mio_0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mio_0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mio_0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mio_0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mio_0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mio_0_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mio_0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mio_0_cmp_gclk_if.pce_ov; por___gclk clkgen_mio_0_cmp_gclk_if.por_; rst_por___gclk clkgen_mio_0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mio_0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mio_0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mio_0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mio_0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mio_0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mio_0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mio_0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mio_0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mio_0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mio_0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mio_0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mio_0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mio_0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mio_0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mio_0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mio_0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mio_0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mio_0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mio_0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mio_0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mio_0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mio_0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mio_0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mio_0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mio_0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mio_0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mio_0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mio_1_cmp ----- bind CLKGEN_port clkgen_mio_1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mio_1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mio_1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mio_1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mio_1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mio_1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mio_1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mio_1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mio_1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mio_1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mio_1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mio_1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mio_1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mio_1_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mio_1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mio_1_cmp_gclk_if.pce_ov; por___gclk clkgen_mio_1_cmp_gclk_if.por_; rst_por___gclk clkgen_mio_1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mio_1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mio_1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mio_1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mio_1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mio_1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mio_1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mio_1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mio_1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mio_1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mio_1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mio_1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mio_1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mio_1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mio_1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mio_1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mio_1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mio_1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mio_1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mio_1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mio_1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mio_1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mio_1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mio_1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mio_1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mio_1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mio_1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mio_1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mio_2_cmp ----- bind CLKGEN_port clkgen_mio_2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mio_2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mio_2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mio_2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mio_2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mio_2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mio_2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mio_2_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mio_2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mio_2_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mio_2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mio_2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mio_2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mio_2_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mio_2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mio_2_cmp_gclk_if.pce_ov; por___gclk clkgen_mio_2_cmp_gclk_if.por_; rst_por___gclk clkgen_mio_2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mio_2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mio_2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mio_2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mio_2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mio_2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mio_2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mio_2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mio_2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mio_2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mio_2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mio_2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mio_2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mio_2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mio_2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mio_2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mio_2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mio_2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mio_2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mio_2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mio_2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mio_2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mio_2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mio_2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mio_2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mio_2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mio_2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mio_2_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mio_3_cmp ----- bind CLKGEN_port clkgen_mio_3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mio_3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mio_3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mio_3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mio_3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mio_3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mio_3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mio_3_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mio_3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mio_3_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mio_3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mio_3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mio_3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mio_3_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mio_3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mio_3_cmp_gclk_if.pce_ov; por___gclk clkgen_mio_3_cmp_gclk_if.por_; rst_por___gclk clkgen_mio_3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mio_3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mio_3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mio_3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mio_3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mio_3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mio_3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mio_3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mio_3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mio_3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mio_3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mio_3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mio_3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mio_3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mio_3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mio_3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mio_3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mio_3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mio_3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mio_3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mio_3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mio_3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mio_3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mio_3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mio_3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mio_3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mio_3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mio_3_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mio_io ----- bind CLKGEN_port clkgen_mio_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mio_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mio_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mio_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mio_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mio_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mio_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mio_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mio_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mio_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mio_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mio_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mio_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mio_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mio_io_gclk_if.l2clk; pce_ov__gclk clkgen_mio_io_gclk_if.pce_ov; por___gclk clkgen_mio_io_gclk_if.por_; rst_por___gclk clkgen_mio_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mio_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mio_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mio_io_gclk_if.scan_en; scan_in__gclk clkgen_mio_io_gclk_if.scan_in; scan_out__gclk clkgen_mio_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mio_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mio_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mio_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mio_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mio_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mio_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mio_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mio_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mio_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mio_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mio_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mio_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mio_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mio_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mio_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mio_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mio_io_l2clk_if.pce_ov; por___l2clk clkgen_mio_io_l2clk_if.por_; scan_out__l2clk clkgen_mio_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mio_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mio_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mio_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_ncu_cmp ----- bind CLKGEN_port clkgen_ncu_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_ncu_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_ncu_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_ncu_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_ncu_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_ncu_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_ncu_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_ncu_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_ncu_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_ncu_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_ncu_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_ncu_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_ncu_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_ncu_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_ncu_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_ncu_cmp_gclk_if.pce_ov; por___gclk clkgen_ncu_cmp_gclk_if.por_; rst_por___gclk clkgen_ncu_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_ncu_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_ncu_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_ncu_cmp_gclk_if.scan_en; scan_in__gclk clkgen_ncu_cmp_gclk_if.scan_in; scan_out__gclk clkgen_ncu_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_ncu_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_ncu_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_ncu_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_ncu_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_ncu_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_ncu_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_ncu_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_ncu_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_ncu_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_ncu_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_ncu_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_ncu_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_ncu_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_ncu_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_ncu_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ncu_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_ncu_cmp_l2clk_if.pce_ov; por___l2clk clkgen_ncu_cmp_l2clk_if.por_; scan_out__l2clk clkgen_ncu_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_ncu_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_ncu_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_ncu_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_ncu_io ----- bind CLKGEN_port clkgen_ncu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_ncu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_ncu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_ncu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_ncu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_ncu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_ncu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_ncu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_ncu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_ncu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_ncu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_ncu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_ncu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_ncu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_ncu_io_gclk_if.l2clk; pce_ov__gclk clkgen_ncu_io_gclk_if.pce_ov; por___gclk clkgen_ncu_io_gclk_if.por_; rst_por___gclk clkgen_ncu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_ncu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_ncu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_ncu_io_gclk_if.scan_en; scan_in__gclk clkgen_ncu_io_gclk_if.scan_in; scan_out__gclk clkgen_ncu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_ncu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_ncu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_ncu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_ncu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_ncu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_ncu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_ncu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_ncu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_ncu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_ncu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_ncu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_ncu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_ncu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_ncu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_ncu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ncu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_ncu_io_l2clk_if.pce_ov; por___l2clk clkgen_ncu_io_l2clk_if.por_; scan_out__l2clk clkgen_ncu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_ncu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_ncu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_ncu_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_rst_cmp ----- bind CLKGEN_port clkgen_rst_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rst_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_rst_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rst_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rst_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rst_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rst_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rst_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rst_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rst_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rst_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rst_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rst_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rst_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rst_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_rst_cmp_gclk_if.pce_ov; por___gclk clkgen_rst_cmp_gclk_if.por_; rst_por___gclk clkgen_rst_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_rst_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rst_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rst_cmp_gclk_if.scan_en; scan_in__gclk clkgen_rst_cmp_gclk_if.scan_in; scan_out__gclk clkgen_rst_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rst_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rst_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rst_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rst_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rst_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rst_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rst_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rst_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rst_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_rst_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rst_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rst_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rst_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rst_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rst_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rst_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_rst_cmp_l2clk_if.pce_ov; por___l2clk clkgen_rst_cmp_l2clk_if.por_; scan_out__l2clk clkgen_rst_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rst_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rst_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rst_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_rst_io ----- bind CLKGEN_port clkgen_rst_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rst_io_gclk_if.aclk; aclk_wmr__gclk clkgen_rst_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rst_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rst_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rst_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rst_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rst_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rst_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rst_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rst_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rst_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rst_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rst_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rst_io_gclk_if.l2clk; pce_ov__gclk clkgen_rst_io_gclk_if.pce_ov; por___gclk clkgen_rst_io_gclk_if.por_; rst_por___gclk clkgen_rst_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_rst_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rst_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rst_io_gclk_if.scan_en; scan_in__gclk clkgen_rst_io_gclk_if.scan_in; scan_out__gclk clkgen_rst_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rst_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rst_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rst_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rst_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rst_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rst_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rst_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rst_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rst_io_gclk_if.wmr_; wmr_protect__gclk clkgen_rst_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rst_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rst_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rst_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rst_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rst_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rst_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_rst_io_l2clk_if.pce_ov; por___l2clk clkgen_rst_io_l2clk_if.por_; scan_out__l2clk clkgen_rst_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rst_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rst_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rst_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_tcu_cmp ----- bind CLKGEN_port clkgen_tcu_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_tcu_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_tcu_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_tcu_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_tcu_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_tcu_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_tcu_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_tcu_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_tcu_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_tcu_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_tcu_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_tcu_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_tcu_cmp_gclk_if.dr_sync_en; gclk clkgen_tcu_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_tcu_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_tcu_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_tcu_cmp_gclk_if.pce_ov; por___gclk clkgen_tcu_cmp_gclk_if.por_; rst_por___gclk clkgen_tcu_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_tcu_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_tcu_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_tcu_cmp_gclk_if.scan_en; scan_in__gclk clkgen_tcu_cmp_gclk_if.scan_in; scan_out__gclk clkgen_tcu_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_tcu_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_tcu_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_tcu_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_tcu_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_tcu_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_tcu_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_tcu_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_tcu_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_tcu_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_tcu_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_tcu_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_tcu_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_tcu_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_tcu_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_tcu_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_tcu_cmp_l2clk_if.pce_ov; por___l2clk clkgen_tcu_cmp_l2clk_if.por_; scan_out__l2clk clkgen_tcu_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_tcu_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_tcu_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_tcu_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_tcu_io ----- bind CLKGEN_port clkgen_tcu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_tcu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_tcu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_tcu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_tcu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_tcu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_tcu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_tcu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_tcu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_tcu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_tcu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_tcu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_tcu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_tcu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_tcu_io_gclk_if.l2clk; pce_ov__gclk clkgen_tcu_io_gclk_if.pce_ov; por___gclk clkgen_tcu_io_gclk_if.por_; rst_por___gclk clkgen_tcu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_tcu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_tcu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_tcu_io_gclk_if.scan_en; scan_in__gclk clkgen_tcu_io_gclk_if.scan_in; scan_out__gclk clkgen_tcu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_tcu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_tcu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_tcu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_tcu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_tcu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_tcu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_tcu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_tcu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_tcu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_tcu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_tcu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_tcu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_tcu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_tcu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_tcu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_tcu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_tcu_io_l2clk_if.pce_ov; por___l2clk clkgen_tcu_io_l2clk_if.por_; scan_out__l2clk clkgen_tcu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_tcu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_tcu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_tcu_io_l2clk_if.wmr_protect; } //####################################################### //### port bindings for blocks not in TCU SAT ### //####################################################### #ifdef FC_BENCH //----- port binding for clkgen_ccx_cmp ----- bind CLKGEN_port clkgen_ccx_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_ccx_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_ccx_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_ccx_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_ccx_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_ccx_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_ccx_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_ccx_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_ccx_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_ccx_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_ccx_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_ccx_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_ccx_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_ccx_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_ccx_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_ccx_cmp_gclk_if.pce_ov; por___gclk clkgen_ccx_cmp_gclk_if.por_; rst_por___gclk clkgen_ccx_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_ccx_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_ccx_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_ccx_cmp_gclk_if.scan_en; scan_in__gclk clkgen_ccx_cmp_gclk_if.scan_in; scan_out__gclk clkgen_ccx_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_ccx_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_ccx_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_ccx_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_ccx_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_ccx_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_ccx_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_ccx_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_ccx_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_ccx_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_ccx_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_ccx_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_ccx_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_ccx_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_ccx_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_ccx_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_ccx_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_ccx_cmp_l2clk_if.pce_ov; por___l2clk clkgen_ccx_cmp_l2clk_if.por_; scan_out__l2clk clkgen_ccx_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_ccx_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_ccx_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_ccx_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_dmu_io ----- bind CLKGEN_port clkgen_dmu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_dmu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_dmu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_dmu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_dmu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_dmu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_dmu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_dmu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_dmu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_dmu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_dmu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_dmu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_dmu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_dmu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_dmu_io_gclk_if.l2clk; pce_ov__gclk clkgen_dmu_io_gclk_if.pce_ov; por___gclk clkgen_dmu_io_gclk_if.por_; rst_por___gclk clkgen_dmu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_dmu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_dmu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_dmu_io_gclk_if.scan_en; scan_in__gclk clkgen_dmu_io_gclk_if.scan_in; scan_out__gclk clkgen_dmu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_dmu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_dmu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_dmu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_dmu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_dmu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_dmu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_dmu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_dmu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_dmu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_dmu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_dmu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_dmu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_dmu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_dmu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_dmu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_dmu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_dmu_io_l2clk_if.pce_ov; por___l2clk clkgen_dmu_io_l2clk_if.por_; scan_out__l2clk clkgen_dmu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_dmu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_dmu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_dmu_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b0_cmp ----- bind CLKGEN_port clkgen_l2b0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b0_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b0_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b0_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b1_cmp ----- bind CLKGEN_port clkgen_l2b1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b1_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b1_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b1_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b2_cmp ----- bind CLKGEN_port clkgen_l2b2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b2_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b2_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b2_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b2_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b2_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b2_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b3_cmp ----- bind CLKGEN_port clkgen_l2b3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b3_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b3_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b3_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b3_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b3_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b3_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b4_cmp ----- bind CLKGEN_port clkgen_l2b4_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b4_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b4_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b4_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b4_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b4_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b4_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b4_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b4_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b4_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b4_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b4_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b4_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b4_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b4_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b4_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b4_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b4_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b4_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b4_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b4_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b4_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b4_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b4_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b4_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b4_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b4_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b4_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b4_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b4_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b4_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b4_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b4_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b4_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b4_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b4_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b4_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b4_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b4_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b4_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b4_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b4_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b4_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b4_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b4_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b5_cmp ----- bind CLKGEN_port clkgen_l2b5_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b5_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b5_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b5_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b5_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b5_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b5_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b5_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b5_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b5_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b5_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b5_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b5_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b5_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b5_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b5_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b5_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b5_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b5_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b5_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b5_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b5_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b5_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b5_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b5_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b5_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b5_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b5_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b5_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b5_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b5_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b5_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b5_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b5_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b5_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b5_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b5_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b5_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b5_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b5_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b5_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b5_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b5_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b5_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b5_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b6_cmp ----- bind CLKGEN_port clkgen_l2b6_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b6_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b6_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b6_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b6_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b6_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b6_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b6_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b6_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b6_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b6_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b6_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b6_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b6_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b6_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b6_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b6_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b6_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b6_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b6_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b6_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b6_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b6_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b6_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b6_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b6_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b6_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b6_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b6_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b6_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b6_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b6_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b6_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b6_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b6_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b6_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b6_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b6_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b6_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b6_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b6_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b6_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b6_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b6_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b6_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2b7_cmp ----- bind CLKGEN_port clkgen_l2b7_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2b7_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2b7_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2b7_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2b7_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2b7_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2b7_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2b7_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2b7_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2b7_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2b7_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2b7_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2b7_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2b7_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2b7_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2b7_cmp_gclk_if.pce_ov; por___gclk clkgen_l2b7_cmp_gclk_if.por_; rst_por___gclk clkgen_l2b7_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2b7_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2b7_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2b7_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2b7_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2b7_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2b7_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2b7_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2b7_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2b7_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2b7_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2b7_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2b7_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2b7_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2b7_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2b7_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2b7_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2b7_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2b7_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2b7_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2b7_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2b7_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2b7_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2b7_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2b7_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2b7_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2b7_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2b7_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d0_cmp ----- bind CLKGEN_port clkgen_l2d0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d0_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d0_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d0_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d1_cmp ----- bind CLKGEN_port clkgen_l2d1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d1_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d1_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d1_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d2_cmp ----- bind CLKGEN_port clkgen_l2d2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d2_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d2_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d2_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d2_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d3_cmp ----- bind CLKGEN_port clkgen_l2d3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d3_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d3_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d3_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d3_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d4_cmp ----- bind CLKGEN_port clkgen_l2d4_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d4_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d4_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d4_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d4_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d4_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d4_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d4_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d4_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d4_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d4_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d4_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d4_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d4_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d4_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d4_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d4_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d4_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d4_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d4_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d4_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d4_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d4_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d4_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d4_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d4_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d4_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d4_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d4_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d4_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d4_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d4_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d4_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d4_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d4_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d4_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d4_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d4_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d4_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d4_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d4_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d4_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d4_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d5_cmp ----- bind CLKGEN_port clkgen_l2d5_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d5_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d5_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d5_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d5_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d5_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d5_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d5_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d5_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d5_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d5_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d5_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d5_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d5_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d5_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d5_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d5_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d5_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d5_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d5_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d5_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d5_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d5_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d5_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d5_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d5_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d5_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d5_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d5_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d5_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d5_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d5_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d5_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d5_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d5_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d5_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d5_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d5_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d5_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d5_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d5_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d5_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d5_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d6_cmp ----- bind CLKGEN_port clkgen_l2d6_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d6_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d6_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d6_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d6_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d6_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d6_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d6_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d6_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d6_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d6_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d6_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d6_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d6_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d6_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d6_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d6_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d6_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d6_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d6_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d6_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d6_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d6_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d6_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d6_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d6_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d6_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d6_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d6_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d6_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d6_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d6_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d6_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d6_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d6_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d6_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d6_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d6_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d6_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d6_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d6_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d6_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d6_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2d7_cmp ----- bind CLKGEN_port clkgen_l2d7_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2d7_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2d7_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2d7_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2d7_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2d7_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2d7_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk clkgen_l2d7_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk void; cluster_arst_l__gclk clkgen_l2d7_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2d7_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2d7_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2d7_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2d7_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2d7_cmp_gclk_if.pce_ov; por___gclk clkgen_l2d7_cmp_gclk_if.por_; rst_por___gclk clkgen_l2d7_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2d7_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2d7_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2d7_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2d7_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2d7_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2d7_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2d7_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2d7_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2d7_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2d7_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2d7_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2d7_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2d7_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2d7_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2d7_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2d7_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2d7_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2d7_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2d7_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2d7_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2d7_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2d7_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2d7_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2d7_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2d7_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2d7_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2d7_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t0_cmp ----- bind CLKGEN_port clkgen_l2t0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t0_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t0_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t0_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t1_cmp ----- bind CLKGEN_port clkgen_l2t1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t1_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t1_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t1_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t2_cmp ----- bind CLKGEN_port clkgen_l2t2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t2_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t2_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t2_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t2_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t2_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t2_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t3_cmp ----- bind CLKGEN_port clkgen_l2t3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t3_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t3_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t3_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t3_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t3_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t3_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t4_cmp ----- bind CLKGEN_port clkgen_l2t4_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t4_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t4_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t4_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t4_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t4_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t4_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t4_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t4_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t4_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t4_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t4_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t4_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t4_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t4_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t4_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t4_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t4_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t4_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t4_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t4_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t4_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t4_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t4_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t4_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t4_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t4_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t4_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t4_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t4_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t4_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t4_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t4_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t4_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t4_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t4_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t4_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t4_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t4_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t4_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t4_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t4_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t4_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t4_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t4_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t5_cmp ----- bind CLKGEN_port clkgen_l2t5_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t5_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t5_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t5_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t5_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t5_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t5_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t5_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t5_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t5_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t5_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t5_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t5_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t5_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t5_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t5_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t5_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t5_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t5_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t5_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t5_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t5_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t5_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t5_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t5_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t5_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t5_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t5_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t5_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t5_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t5_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t5_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t5_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t5_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t5_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t5_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t5_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t5_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t5_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t5_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t5_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t5_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t5_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t5_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t5_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t6_cmp ----- bind CLKGEN_port clkgen_l2t6_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t6_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t6_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t6_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t6_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t6_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t6_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t6_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t6_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t6_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t6_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t6_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t6_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t6_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t6_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t6_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t6_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t6_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t6_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t6_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t6_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t6_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t6_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t6_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t6_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t6_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t6_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t6_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t6_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t6_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t6_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t6_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t6_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t6_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t6_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t6_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t6_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t6_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t6_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t6_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t6_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t6_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t6_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t6_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t6_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_l2t7_cmp ----- bind CLKGEN_port clkgen_l2t7_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_l2t7_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_l2t7_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_l2t7_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_l2t7_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_l2t7_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_l2t7_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_l2t7_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_l2t7_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_l2t7_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_l2t7_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_l2t7_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_l2t7_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_l2t7_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_l2t7_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_l2t7_cmp_gclk_if.pce_ov; por___gclk clkgen_l2t7_cmp_gclk_if.por_; rst_por___gclk clkgen_l2t7_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_l2t7_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_l2t7_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_l2t7_cmp_gclk_if.scan_en; scan_in__gclk clkgen_l2t7_cmp_gclk_if.scan_in; scan_out__gclk clkgen_l2t7_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_l2t7_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_l2t7_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_l2t7_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_l2t7_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_l2t7_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_l2t7_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_l2t7_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_l2t7_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_l2t7_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_l2t7_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_l2t7_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_l2t7_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_l2t7_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_l2t7_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_l2t7_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_l2t7_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_l2t7_cmp_l2clk_if.pce_ov; por___l2clk clkgen_l2t7_cmp_l2clk_if.por_; scan_out__l2clk clkgen_l2t7_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_l2t7_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_l2t7_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_l2t7_cmp_l2clk_if.wmr_protect; } #ifndef FC_NO_NIU_T2 #ifndef NIU_SYSTEMC_T2 //----- port binding for clkgen_mac_io ----- bind CLKGEN_port clkgen_mac_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mac_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mac_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mac_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mac_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mac_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mac_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mac_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mac_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mac_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mac_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mac_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mac_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mac_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mac_io_gclk_if.l2clk; pce_ov__gclk clkgen_mac_io_gclk_if.pce_ov; por___gclk clkgen_mac_io_gclk_if.por_; rst_por___gclk clkgen_mac_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mac_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mac_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mac_io_gclk_if.scan_en; scan_in__gclk clkgen_mac_io_gclk_if.scan_in; scan_out__gclk clkgen_mac_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mac_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mac_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mac_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mac_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mac_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mac_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mac_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mac_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mac_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mac_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mac_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mac_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mac_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mac_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mac_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mac_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mac_io_l2clk_if.pce_ov; por___l2clk clkgen_mac_io_l2clk_if.por_; scan_out__l2clk clkgen_mac_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mac_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mac_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mac_io_l2clk_if.wmr_protect; } #endif #endif //----- port binding for clkgen_mcu0_cmp ----- bind CLKGEN_port clkgen_mcu0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_mcu0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_mcu0_cmp_gclk_if.dr_sync_en; gclk clkgen_mcu0_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_mcu0_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_mcu0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mcu0_cmp_gclk_if.pce_ov; por___gclk clkgen_mcu0_cmp_gclk_if.por_; rst_por___gclk clkgen_mcu0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mcu0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mcu0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_mcu0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mcu0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mcu0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu0_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu0_dr ----- bind CLKGEN_port clkgen_mcu0_dr_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu0_dr_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu0_dr_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu0_dr_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu0_dr_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu0_dr_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu0_dr_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu0_dr_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu0_dr_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu0_dr_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu0_dr_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu0_dr_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu0_dr_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu0_dr_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu0_dr_gclk_if.l2clk; pce_ov__gclk clkgen_mcu0_dr_gclk_if.pce_ov; por___gclk clkgen_mcu0_dr_gclk_if.por_; rst_por___gclk clkgen_mcu0_dr_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu0_dr_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu0_dr_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu0_dr_gclk_if.scan_en; scan_in__gclk clkgen_mcu0_dr_gclk_if.scan_in; scan_out__gclk clkgen_mcu0_dr_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu0_dr_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu0_dr_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu0_dr_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu0_dr_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu0_dr_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu0_dr_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu0_dr_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu0_dr_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu0_dr_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu0_dr_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu0_dr_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu0_dr_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu0_dr_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu0_dr_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu0_dr_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu0_dr_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu0_dr_l2clk_if.pce_ov; por___l2clk clkgen_mcu0_dr_l2clk_if.por_; scan_out__l2clk clkgen_mcu0_dr_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu0_dr_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu0_dr_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu0_dr_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu0_io ----- bind CLKGEN_port clkgen_mcu0_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu0_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu0_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu0_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu0_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu0_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu0_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu0_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu0_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu0_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu0_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu0_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu0_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu0_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu0_io_gclk_if.l2clk; pce_ov__gclk clkgen_mcu0_io_gclk_if.pce_ov; por___gclk clkgen_mcu0_io_gclk_if.por_; rst_por___gclk clkgen_mcu0_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu0_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu0_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu0_io_gclk_if.scan_en; scan_in__gclk clkgen_mcu0_io_gclk_if.scan_in; scan_out__gclk clkgen_mcu0_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu0_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu0_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu0_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu0_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu0_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu0_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu0_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu0_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu0_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu0_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu0_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu0_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu0_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu0_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu0_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu0_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu0_io_l2clk_if.pce_ov; por___l2clk clkgen_mcu0_io_l2clk_if.por_; scan_out__l2clk clkgen_mcu0_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu0_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu0_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu0_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu1_cmp ----- bind CLKGEN_port clkgen_mcu1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_mcu1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_mcu1_cmp_gclk_if.dr_sync_en; gclk clkgen_mcu1_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_mcu1_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_mcu1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mcu1_cmp_gclk_if.pce_ov; por___gclk clkgen_mcu1_cmp_gclk_if.por_; rst_por___gclk clkgen_mcu1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mcu1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mcu1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_mcu1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mcu1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mcu1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu1_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu1_dr ----- bind CLKGEN_port clkgen_mcu1_dr_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu1_dr_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu1_dr_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu1_dr_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu1_dr_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu1_dr_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu1_dr_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu1_dr_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu1_dr_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu1_dr_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu1_dr_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu1_dr_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu1_dr_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu1_dr_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu1_dr_gclk_if.l2clk; pce_ov__gclk clkgen_mcu1_dr_gclk_if.pce_ov; por___gclk clkgen_mcu1_dr_gclk_if.por_; rst_por___gclk clkgen_mcu1_dr_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu1_dr_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu1_dr_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu1_dr_gclk_if.scan_en; scan_in__gclk clkgen_mcu1_dr_gclk_if.scan_in; scan_out__gclk clkgen_mcu1_dr_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu1_dr_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu1_dr_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu1_dr_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu1_dr_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu1_dr_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu1_dr_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu1_dr_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu1_dr_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu1_dr_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu1_dr_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu1_dr_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu1_dr_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu1_dr_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu1_dr_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu1_dr_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu1_dr_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu1_dr_l2clk_if.pce_ov; por___l2clk clkgen_mcu1_dr_l2clk_if.por_; scan_out__l2clk clkgen_mcu1_dr_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu1_dr_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu1_dr_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu1_dr_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu1_io ----- bind CLKGEN_port clkgen_mcu1_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu1_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu1_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu1_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu1_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu1_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu1_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu1_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu1_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu1_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu1_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu1_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu1_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu1_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu1_io_gclk_if.l2clk; pce_ov__gclk clkgen_mcu1_io_gclk_if.pce_ov; por___gclk clkgen_mcu1_io_gclk_if.por_; rst_por___gclk clkgen_mcu1_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu1_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu1_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu1_io_gclk_if.scan_en; scan_in__gclk clkgen_mcu1_io_gclk_if.scan_in; scan_out__gclk clkgen_mcu1_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu1_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu1_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu1_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu1_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu1_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu1_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu1_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu1_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu1_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu1_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu1_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu1_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu1_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu1_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu1_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu1_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu1_io_l2clk_if.pce_ov; por___l2clk clkgen_mcu1_io_l2clk_if.por_; scan_out__l2clk clkgen_mcu1_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu1_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu1_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu1_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu2_cmp ----- bind CLKGEN_port clkgen_mcu2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_mcu2_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu2_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_mcu2_cmp_gclk_if.dr_sync_en; gclk clkgen_mcu2_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_mcu2_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_mcu2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mcu2_cmp_gclk_if.pce_ov; por___gclk clkgen_mcu2_cmp_gclk_if.por_; rst_por___gclk clkgen_mcu2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mcu2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mcu2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_mcu2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mcu2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mcu2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu2_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu2_dr ----- bind CLKGEN_port clkgen_mcu2_dr_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu2_dr_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu2_dr_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu2_dr_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu2_dr_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu2_dr_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu2_dr_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu2_dr_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu2_dr_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu2_dr_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu2_dr_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu2_dr_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu2_dr_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu2_dr_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu2_dr_gclk_if.l2clk; pce_ov__gclk clkgen_mcu2_dr_gclk_if.pce_ov; por___gclk clkgen_mcu2_dr_gclk_if.por_; rst_por___gclk clkgen_mcu2_dr_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu2_dr_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu2_dr_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu2_dr_gclk_if.scan_en; scan_in__gclk clkgen_mcu2_dr_gclk_if.scan_in; scan_out__gclk clkgen_mcu2_dr_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu2_dr_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu2_dr_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu2_dr_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu2_dr_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu2_dr_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu2_dr_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu2_dr_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu2_dr_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu2_dr_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu2_dr_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu2_dr_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu2_dr_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu2_dr_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu2_dr_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu2_dr_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu2_dr_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu2_dr_l2clk_if.pce_ov; por___l2clk clkgen_mcu2_dr_l2clk_if.por_; scan_out__l2clk clkgen_mcu2_dr_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu2_dr_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu2_dr_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu2_dr_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu2_io ----- bind CLKGEN_port clkgen_mcu2_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu2_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu2_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu2_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu2_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu2_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu2_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu2_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu2_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu2_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu2_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu2_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu2_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu2_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu2_io_gclk_if.l2clk; pce_ov__gclk clkgen_mcu2_io_gclk_if.pce_ov; por___gclk clkgen_mcu2_io_gclk_if.por_; rst_por___gclk clkgen_mcu2_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu2_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu2_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu2_io_gclk_if.scan_en; scan_in__gclk clkgen_mcu2_io_gclk_if.scan_in; scan_out__gclk clkgen_mcu2_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu2_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu2_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu2_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu2_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu2_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu2_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu2_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu2_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu2_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu2_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu2_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu2_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu2_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu2_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu2_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu2_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu2_io_l2clk_if.pce_ov; por___l2clk clkgen_mcu2_io_l2clk_if.por_; scan_out__l2clk clkgen_mcu2_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu2_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu2_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu2_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu3_cmp ----- bind CLKGEN_port clkgen_mcu3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_dr_sync_en; ccu_io2x_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_io2x_sync_en; ccu_serdes_dtm__gclk clkgen_mcu3_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu3_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk clkgen_mcu3_cmp_gclk_if.dr_sync_en; gclk clkgen_mcu3_cmp_gclk_if.gclk; io2x_sync_en__gclk clkgen_mcu3_cmp_gclk_if.io2x_sync_en; l2clk__gclk clkgen_mcu3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_mcu3_cmp_gclk_if.pce_ov; por___gclk clkgen_mcu3_cmp_gclk_if.por_; rst_por___gclk clkgen_mcu3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_mcu3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_mcu3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.dr_sync_en; io2x_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.io2x_sync_en; l2clk clkgen_mcu3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_mcu3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_mcu3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu3_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu3_dr ----- bind CLKGEN_port clkgen_mcu3_dr_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu3_dr_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu3_dr_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu3_dr_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu3_dr_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu3_dr_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu3_dr_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu3_dr_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu3_dr_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu3_dr_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu3_dr_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu3_dr_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu3_dr_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu3_dr_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu3_dr_gclk_if.l2clk; pce_ov__gclk clkgen_mcu3_dr_gclk_if.pce_ov; por___gclk clkgen_mcu3_dr_gclk_if.por_; rst_por___gclk clkgen_mcu3_dr_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu3_dr_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu3_dr_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu3_dr_gclk_if.scan_en; scan_in__gclk clkgen_mcu3_dr_gclk_if.scan_in; scan_out__gclk clkgen_mcu3_dr_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu3_dr_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu3_dr_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu3_dr_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu3_dr_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu3_dr_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu3_dr_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu3_dr_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu3_dr_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu3_dr_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu3_dr_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu3_dr_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu3_dr_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu3_dr_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu3_dr_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu3_dr_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu3_dr_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu3_dr_l2clk_if.pce_ov; por___l2clk clkgen_mcu3_dr_l2clk_if.por_; scan_out__l2clk clkgen_mcu3_dr_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu3_dr_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu3_dr_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu3_dr_l2clk_if.wmr_protect; } //----- port binding for clkgen_mcu3_io ----- bind CLKGEN_port clkgen_mcu3_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_mcu3_io_gclk_if.aclk; aclk_wmr__gclk clkgen_mcu3_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_mcu3_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_mcu3_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_mcu3_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_mcu3_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_mcu3_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_mcu3_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_mcu3_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_mcu3_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_mcu3_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_mcu3_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_mcu3_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_mcu3_io_gclk_if.l2clk; pce_ov__gclk clkgen_mcu3_io_gclk_if.pce_ov; por___gclk clkgen_mcu3_io_gclk_if.por_; rst_por___gclk clkgen_mcu3_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_mcu3_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_mcu3_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_mcu3_io_gclk_if.scan_en; scan_in__gclk clkgen_mcu3_io_gclk_if.scan_in; scan_out__gclk clkgen_mcu3_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_mcu3_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_mcu3_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_mcu3_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_mcu3_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_mcu3_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_mcu3_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_mcu3_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_mcu3_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_mcu3_io_gclk_if.wmr_; wmr_protect__gclk clkgen_mcu3_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_mcu3_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_mcu3_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_mcu3_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_mcu3_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_mcu3_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_mcu3_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_mcu3_io_l2clk_if.pce_ov; por___l2clk clkgen_mcu3_io_l2clk_if.por_; scan_out__l2clk clkgen_mcu3_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_mcu3_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_mcu3_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_mcu3_io_l2clk_if.wmr_protect; } // added this: #ifndef FC_NO_PEU_VERA #ifndef PEU_SYSTEMC_T2 //----- port binding for clkgen_peu_io ----- bind CLKGEN_port clkgen_peu_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_peu_io_gclk_if.aclk; aclk_wmr__gclk clkgen_peu_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_peu_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_peu_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_peu_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_peu_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_peu_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_peu_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_peu_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_peu_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_peu_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_peu_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_peu_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_peu_io_gclk_if.l2clk; pce_ov__gclk clkgen_peu_io_gclk_if.pce_ov; por___gclk clkgen_peu_io_gclk_if.por_; rst_por___gclk clkgen_peu_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_peu_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_peu_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_peu_io_gclk_if.scan_en; scan_in__gclk clkgen_peu_io_gclk_if.scan_in; scan_out__gclk clkgen_peu_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_peu_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_peu_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_peu_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_peu_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_peu_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_peu_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_peu_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_peu_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_peu_io_gclk_if.wmr_; wmr_protect__gclk clkgen_peu_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_peu_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_peu_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_peu_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_peu_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_peu_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_peu_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_peu_io_l2clk_if.pce_ov; por___l2clk clkgen_peu_io_l2clk_if.por_; scan_out__l2clk clkgen_peu_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_peu_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_peu_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_peu_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_peu_pc ----- bind CLKGEN_port clkgen_peu_pc_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_peu_pc_gclk_if.aclk; aclk_wmr__gclk clkgen_peu_pc_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_peu_pc_gclk_if.array_wr_inhibit; bclk__gclk clkgen_peu_pc_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk void; ccu_div_ph__gclk clkgen_peu_pc_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk void; ccu_slow_cmp_sync_en__gclk void; clk_ext__gclk void; cluster_arst_l__gclk clkgen_peu_pc_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_peu_pc_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk void; dr_sync_en__gclk void; gclk clkgen_peu_pc_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_peu_pc_gclk_if.l2clk; pce_ov__gclk clkgen_peu_pc_gclk_if.pce_ov; por___gclk clkgen_peu_pc_gclk_if.por_; rst_por___gclk clkgen_peu_pc_gclk_if.rst_por_; rst_wmr___gclk clkgen_peu_pc_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_peu_pc_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_peu_pc_gclk_if.scan_en; scan_in__gclk clkgen_peu_pc_gclk_if.scan_in; scan_out__gclk clkgen_peu_pc_gclk_if.scan_out; slow_cmp_sync_en__gclk void; tcu_aclk__gclk clkgen_peu_pc_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_peu_pc_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_peu_pc_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_peu_pc_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk void; tcu_pce_ov__gclk clkgen_peu_pc_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_peu_pc_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_peu_pc_gclk_if.wmr_; wmr_protect__gclk clkgen_peu_pc_gclk_if.wmr_protect; pc_clk__gclk clkgen_peu_pc_gclk_if.pc_clk; pc_clk_sel__gclk clkgen_peu_pc_gclk_if.pc_clk_sel; test_clk__gclk clkgen_peu_pc_gclk_if.test_clk; test_clk_sel__gclk clkgen_peu_pc_gclk_if.test_clk_sel; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_peu_pc_l2clk_if.aclk; aclk_wmr__l2clk clkgen_peu_pc_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_peu_pc_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_peu_pc_l2clk_if.bclk; cmp_slow_sync_en__l2clk void; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_peu_pc_l2clk_if.l2clk; pce_ov__l2clk clkgen_peu_pc_l2clk_if.pce_ov; por___l2clk clkgen_peu_pc_l2clk_if.por_; scan_out__l2clk clkgen_peu_pc_l2clk_if.scan_out; slow_cmp_sync_en__l2clk void; wmr___l2clk clkgen_peu_pc_l2clk_if.wmr_; wmr_protect__l2clk clkgen_peu_pc_l2clk_if.wmr_protect; } #endif #endif #ifndef FC_NO_NIU_T2 #ifndef NIU_SYSTEMC_T2 //----- port binding for clkgen_rdp_io ----- bind CLKGEN_port clkgen_rdp_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rdp_io_gclk_if.aclk; aclk_wmr__gclk clkgen_rdp_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rdp_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rdp_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rdp_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rdp_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rdp_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rdp_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rdp_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rdp_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rdp_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rdp_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rdp_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rdp_io_gclk_if.l2clk; pce_ov__gclk clkgen_rdp_io_gclk_if.pce_ov; por___gclk clkgen_rdp_io_gclk_if.por_; rst_por___gclk clkgen_rdp_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_rdp_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rdp_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rdp_io_gclk_if.scan_en; scan_in__gclk clkgen_rdp_io_gclk_if.scan_in; scan_out__gclk clkgen_rdp_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rdp_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rdp_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rdp_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rdp_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rdp_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rdp_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rdp_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rdp_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rdp_io_gclk_if.wmr_; wmr_protect__gclk clkgen_rdp_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rdp_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rdp_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rdp_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rdp_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rdp_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rdp_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_rdp_io_l2clk_if.pce_ov; por___l2clk clkgen_rdp_io_l2clk_if.por_; scan_out__l2clk clkgen_rdp_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rdp_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rdp_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rdp_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_rdp_io2x ----- bind CLKGEN_port clkgen_rdp_io2x_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rdp_io2x_gclk_if.aclk; aclk_wmr__gclk clkgen_rdp_io2x_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rdp_io2x_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rdp_io2x_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rdp_io2x_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rdp_io2x_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rdp_io2x_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rdp_io2x_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rdp_io2x_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rdp_io2x_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rdp_io2x_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rdp_io2x_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rdp_io2x_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rdp_io2x_gclk_if.l2clk; pce_ov__gclk clkgen_rdp_io2x_gclk_if.pce_ov; por___gclk clkgen_rdp_io2x_gclk_if.por_; rst_por___gclk clkgen_rdp_io2x_gclk_if.rst_por_; rst_wmr___gclk clkgen_rdp_io2x_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rdp_io2x_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rdp_io2x_gclk_if.scan_en; scan_in__gclk clkgen_rdp_io2x_gclk_if.scan_in; scan_out__gclk clkgen_rdp_io2x_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rdp_io2x_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rdp_io2x_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rdp_io2x_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rdp_io2x_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rdp_io2x_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rdp_io2x_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rdp_io2x_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rdp_io2x_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rdp_io2x_gclk_if.wmr_; wmr_protect__gclk clkgen_rdp_io2x_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rdp_io2x_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rdp_io2x_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rdp_io2x_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rdp_io2x_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rdp_io2x_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rdp_io2x_l2clk_if.l2clk; pce_ov__l2clk clkgen_rdp_io2x_l2clk_if.pce_ov; por___l2clk clkgen_rdp_io2x_l2clk_if.por_; scan_out__l2clk clkgen_rdp_io2x_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rdp_io2x_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rdp_io2x_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rdp_io2x_l2clk_if.wmr_protect; } //----- port binding for clkgen_rtx_io ----- bind CLKGEN_port clkgen_rtx_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rtx_io_gclk_if.aclk; aclk_wmr__gclk clkgen_rtx_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rtx_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rtx_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rtx_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rtx_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rtx_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rtx_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rtx_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rtx_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rtx_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rtx_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rtx_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rtx_io_gclk_if.l2clk; pce_ov__gclk clkgen_rtx_io_gclk_if.pce_ov; por___gclk clkgen_rtx_io_gclk_if.por_; rst_por___gclk clkgen_rtx_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_rtx_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rtx_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rtx_io_gclk_if.scan_en; scan_in__gclk clkgen_rtx_io_gclk_if.scan_in; scan_out__gclk clkgen_rtx_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rtx_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rtx_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rtx_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rtx_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rtx_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rtx_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rtx_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rtx_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rtx_io_gclk_if.wmr_; wmr_protect__gclk clkgen_rtx_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rtx_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rtx_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rtx_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rtx_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rtx_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rtx_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_rtx_io_l2clk_if.pce_ov; por___l2clk clkgen_rtx_io_l2clk_if.por_; scan_out__l2clk clkgen_rtx_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rtx_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rtx_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rtx_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_rtx_io2x ----- bind CLKGEN_port clkgen_rtx_io2x_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_rtx_io2x_gclk_if.aclk; aclk_wmr__gclk clkgen_rtx_io2x_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_rtx_io2x_gclk_if.array_wr_inhibit; bclk__gclk clkgen_rtx_io2x_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_rtx_io2x_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_rtx_io2x_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_rtx_io2x_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_rtx_io2x_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_rtx_io2x_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_rtx_io2x_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_rtx_io2x_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_rtx_io2x_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_rtx_io2x_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_rtx_io2x_gclk_if.l2clk; pce_ov__gclk clkgen_rtx_io2x_gclk_if.pce_ov; por___gclk clkgen_rtx_io2x_gclk_if.por_; rst_por___gclk clkgen_rtx_io2x_gclk_if.rst_por_; rst_wmr___gclk clkgen_rtx_io2x_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_rtx_io2x_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_rtx_io2x_gclk_if.scan_en; scan_in__gclk clkgen_rtx_io2x_gclk_if.scan_in; scan_out__gclk clkgen_rtx_io2x_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_rtx_io2x_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_rtx_io2x_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_rtx_io2x_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_rtx_io2x_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_rtx_io2x_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_rtx_io2x_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_rtx_io2x_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_rtx_io2x_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_rtx_io2x_gclk_if.wmr_; wmr_protect__gclk clkgen_rtx_io2x_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_rtx_io2x_l2clk_if.aclk; aclk_wmr__l2clk clkgen_rtx_io2x_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_rtx_io2x_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_rtx_io2x_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_rtx_io2x_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_rtx_io2x_l2clk_if.l2clk; pce_ov__l2clk clkgen_rtx_io2x_l2clk_if.pce_ov; por___l2clk clkgen_rtx_io2x_l2clk_if.por_; scan_out__l2clk clkgen_rtx_io2x_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_rtx_io2x_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_rtx_io2x_l2clk_if.wmr_; wmr_protect__l2clk clkgen_rtx_io2x_l2clk_if.wmr_protect; } #endif #endif //----- port binding for clkgen_sii_cmp ----- bind CLKGEN_port clkgen_sii_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_sii_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_sii_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_sii_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_sii_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_sii_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_sii_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_sii_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_sii_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_sii_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_sii_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_sii_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_sii_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_sii_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_sii_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_sii_cmp_gclk_if.pce_ov; por___gclk clkgen_sii_cmp_gclk_if.por_; rst_por___gclk clkgen_sii_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_sii_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_sii_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_sii_cmp_gclk_if.scan_en; scan_in__gclk clkgen_sii_cmp_gclk_if.scan_in; scan_out__gclk clkgen_sii_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_sii_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_sii_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_sii_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_sii_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_sii_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_sii_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_sii_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_sii_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_sii_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_sii_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_sii_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_sii_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_sii_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_sii_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_sii_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_sii_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_sii_cmp_l2clk_if.pce_ov; por___l2clk clkgen_sii_cmp_l2clk_if.por_; scan_out__l2clk clkgen_sii_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_sii_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_sii_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_sii_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_sii_io ----- bind CLKGEN_port clkgen_sii_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_sii_io_gclk_if.aclk; aclk_wmr__gclk clkgen_sii_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_sii_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_sii_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_sii_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_sii_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_sii_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_sii_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_sii_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_sii_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_sii_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_sii_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_sii_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_sii_io_gclk_if.l2clk; pce_ov__gclk clkgen_sii_io_gclk_if.pce_ov; por___gclk clkgen_sii_io_gclk_if.por_; rst_por___gclk clkgen_sii_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_sii_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_sii_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_sii_io_gclk_if.scan_en; scan_in__gclk clkgen_sii_io_gclk_if.scan_in; scan_out__gclk clkgen_sii_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_sii_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_sii_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_sii_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_sii_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_sii_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_sii_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_sii_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_sii_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_sii_io_gclk_if.wmr_; wmr_protect__gclk clkgen_sii_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_sii_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_sii_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_sii_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_sii_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_sii_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_sii_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_sii_io_l2clk_if.pce_ov; por___l2clk clkgen_sii_io_l2clk_if.por_; scan_out__l2clk clkgen_sii_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_sii_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_sii_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_sii_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_sio_cmp ----- bind CLKGEN_port clkgen_sio_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_sio_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_sio_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_sio_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_sio_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_sio_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_sio_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_sio_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_sio_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_sio_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_sio_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_sio_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_sio_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_sio_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_sio_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_sio_cmp_gclk_if.pce_ov; por___gclk clkgen_sio_cmp_gclk_if.por_; rst_por___gclk clkgen_sio_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_sio_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_sio_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_sio_cmp_gclk_if.scan_en; scan_in__gclk clkgen_sio_cmp_gclk_if.scan_in; scan_out__gclk clkgen_sio_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_sio_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_sio_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_sio_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_sio_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_sio_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_sio_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_sio_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_sio_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_sio_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_sio_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_sio_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_sio_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_sio_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_sio_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_sio_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_sio_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_sio_cmp_l2clk_if.pce_ov; por___l2clk clkgen_sio_cmp_l2clk_if.por_; scan_out__l2clk clkgen_sio_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_sio_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_sio_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_sio_cmp_l2clk_if.wmr_protect; } //----- port binding for clkgen_sio_io ----- bind CLKGEN_port clkgen_sio_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_sio_io_gclk_if.aclk; aclk_wmr__gclk clkgen_sio_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_sio_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_sio_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_sio_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_sio_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_sio_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_sio_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_sio_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_sio_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_sio_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_sio_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_sio_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_sio_io_gclk_if.l2clk; pce_ov__gclk clkgen_sio_io_gclk_if.pce_ov; por___gclk clkgen_sio_io_gclk_if.por_; rst_por___gclk clkgen_sio_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_sio_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_sio_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_sio_io_gclk_if.scan_en; scan_in__gclk clkgen_sio_io_gclk_if.scan_in; scan_out__gclk clkgen_sio_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_sio_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_sio_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_sio_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_sio_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_sio_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_sio_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_sio_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_sio_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_sio_io_gclk_if.wmr_; wmr_protect__gclk clkgen_sio_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_sio_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_sio_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_sio_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_sio_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_sio_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_sio_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_sio_io_l2clk_if.pce_ov; por___l2clk clkgen_sio_io_l2clk_if.por_; scan_out__l2clk clkgen_sio_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_sio_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_sio_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_sio_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_spc0_cmp ----- #ifndef RTL_NO_SPC0 bind CLKGEN_port clkgen_spc0_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc0_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc0_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc0_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc0_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc0_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc0_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc0_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc0_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc0_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc0_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc0_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc0_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc0_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc0_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc0_cmp_gclk_if.pce_ov; por___gclk clkgen_spc0_cmp_gclk_if.por_; rst_por___gclk clkgen_spc0_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc0_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc0_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc0_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc0_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc0_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc0_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc0_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc0_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc0_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc0_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc0_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc0_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc0_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc0_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc0_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc0_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc0_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc0_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc0_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc0_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc0_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc0_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc0_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc0_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc0_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc0_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc0_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc1_cmp ----- #ifndef RTL_NO_SPC1 bind CLKGEN_port clkgen_spc1_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc1_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc1_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc1_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc1_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc1_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc1_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc1_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc1_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc1_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc1_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc1_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc1_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc1_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc1_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc1_cmp_gclk_if.pce_ov; por___gclk clkgen_spc1_cmp_gclk_if.por_; rst_por___gclk clkgen_spc1_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc1_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc1_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc1_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc1_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc1_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc1_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc1_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc1_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc1_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc1_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc1_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc1_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc1_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc1_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc1_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc1_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc1_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc1_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc1_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc1_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc1_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc1_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc1_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc1_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc1_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc1_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc1_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc2_cmp ----- #ifndef RTL_NO_SPC2 bind CLKGEN_port clkgen_spc2_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc2_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc2_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc2_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc2_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc2_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc2_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc2_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc2_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc2_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc2_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc2_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc2_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc2_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc2_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc2_cmp_gclk_if.pce_ov; por___gclk clkgen_spc2_cmp_gclk_if.por_; rst_por___gclk clkgen_spc2_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc2_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc2_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc2_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc2_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc2_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc2_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc2_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc2_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc2_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc2_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc2_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc2_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc2_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc2_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc2_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc2_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc2_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc2_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc2_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc2_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc2_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc2_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc2_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc2_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc2_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc2_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc2_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc3_cmp ----- #ifndef RTL_NO_SPC3 bind CLKGEN_port clkgen_spc3_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc3_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc3_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc3_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc3_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc3_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc3_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc3_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc3_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc3_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc3_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc3_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc3_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc3_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc3_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc3_cmp_gclk_if.pce_ov; por___gclk clkgen_spc3_cmp_gclk_if.por_; rst_por___gclk clkgen_spc3_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc3_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc3_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc3_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc3_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc3_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc3_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc3_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc3_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc3_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc3_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc3_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc3_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc3_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc3_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc3_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc3_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc3_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc3_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc3_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc3_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc3_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc3_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc3_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc3_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc3_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc3_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc3_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc4_cmp ----- #ifndef RTL_NO_SPC4 bind CLKGEN_port clkgen_spc4_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc4_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc4_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc4_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc4_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc4_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc4_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc4_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc4_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc4_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc4_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc4_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc4_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc4_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc4_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc4_cmp_gclk_if.pce_ov; por___gclk clkgen_spc4_cmp_gclk_if.por_; rst_por___gclk clkgen_spc4_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc4_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc4_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc4_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc4_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc4_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc4_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc4_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc4_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc4_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc4_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc4_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc4_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc4_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc4_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc4_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc4_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc4_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc4_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc4_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc4_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc4_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc4_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc4_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc4_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc4_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc4_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc4_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc5_cmp ----- #ifndef RTL_NO_SPC5 bind CLKGEN_port clkgen_spc5_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc5_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc5_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc5_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc5_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc5_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc5_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc5_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc5_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc5_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc5_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc5_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc5_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc5_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc5_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc5_cmp_gclk_if.pce_ov; por___gclk clkgen_spc5_cmp_gclk_if.por_; rst_por___gclk clkgen_spc5_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc5_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc5_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc5_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc5_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc5_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc5_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc5_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc5_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc5_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc5_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc5_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc5_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc5_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc5_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc5_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc5_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc5_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc5_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc5_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc5_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc5_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc5_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc5_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc5_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc5_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc5_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc5_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc6_cmp ----- #ifndef RTL_NO_SPC6 bind CLKGEN_port clkgen_spc6_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc6_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc6_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc6_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc6_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc6_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc6_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc6_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc6_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc6_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc6_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc6_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc6_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc6_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc6_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc6_cmp_gclk_if.pce_ov; por___gclk clkgen_spc6_cmp_gclk_if.por_; rst_por___gclk clkgen_spc6_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc6_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc6_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc6_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc6_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc6_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc6_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc6_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc6_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc6_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc6_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc6_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc6_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc6_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc6_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc6_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc6_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc6_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc6_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc6_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc6_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc6_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc6_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc6_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc6_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc6_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc6_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc6_cmp_l2clk_if.wmr_protect; } #endif //----- port binding for clkgen_spc7_cmp ----- #ifndef RTL_NO_SPC7 bind CLKGEN_port clkgen_spc7_cmp_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_spc7_cmp_gclk_if.aclk; aclk_wmr__gclk clkgen_spc7_cmp_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_spc7_cmp_gclk_if.array_wr_inhibit; bclk__gclk clkgen_spc7_cmp_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_spc7_cmp_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_spc7_cmp_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_spc7_cmp_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_spc7_cmp_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_spc7_cmp_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_spc7_cmp_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_spc7_cmp_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_spc7_cmp_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_spc7_cmp_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_spc7_cmp_gclk_if.l2clk; pce_ov__gclk clkgen_spc7_cmp_gclk_if.pce_ov; por___gclk clkgen_spc7_cmp_gclk_if.por_; rst_por___gclk clkgen_spc7_cmp_gclk_if.rst_por_; rst_wmr___gclk clkgen_spc7_cmp_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_spc7_cmp_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_spc7_cmp_gclk_if.scan_en; scan_in__gclk clkgen_spc7_cmp_gclk_if.scan_in; scan_out__gclk clkgen_spc7_cmp_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_spc7_cmp_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_spc7_cmp_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_spc7_cmp_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_spc7_cmp_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_spc7_cmp_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_spc7_cmp_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_spc7_cmp_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_spc7_cmp_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_spc7_cmp_gclk_if.wmr_; wmr_protect__gclk clkgen_spc7_cmp_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_spc7_cmp_l2clk_if.aclk; aclk_wmr__l2clk clkgen_spc7_cmp_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_spc7_cmp_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_spc7_cmp_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_spc7_cmp_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_spc7_cmp_l2clk_if.l2clk; pce_ov__l2clk clkgen_spc7_cmp_l2clk_if.pce_ov; por___l2clk clkgen_spc7_cmp_l2clk_if.por_; scan_out__l2clk clkgen_spc7_cmp_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_spc7_cmp_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_spc7_cmp_l2clk_if.wmr_; wmr_protect__l2clk clkgen_spc7_cmp_l2clk_if.wmr_protect; } #endif #ifndef FC_NO_NIU_T2 #ifndef NIU_SYSTEMC_T2 //----- port binding for clkgen_tds_io ----- bind CLKGEN_port clkgen_tds_io_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_tds_io_gclk_if.aclk; aclk_wmr__gclk clkgen_tds_io_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_tds_io_gclk_if.array_wr_inhibit; bclk__gclk clkgen_tds_io_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_tds_io_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_tds_io_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_tds_io_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_tds_io_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_tds_io_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_tds_io_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_tds_io_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_tds_io_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_tds_io_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_tds_io_gclk_if.l2clk; pce_ov__gclk clkgen_tds_io_gclk_if.pce_ov; por___gclk clkgen_tds_io_gclk_if.por_; rst_por___gclk clkgen_tds_io_gclk_if.rst_por_; rst_wmr___gclk clkgen_tds_io_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_tds_io_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_tds_io_gclk_if.scan_en; scan_in__gclk clkgen_tds_io_gclk_if.scan_in; scan_out__gclk clkgen_tds_io_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_tds_io_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_tds_io_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_tds_io_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_tds_io_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_tds_io_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_tds_io_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_tds_io_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_tds_io_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_tds_io_gclk_if.wmr_; wmr_protect__gclk clkgen_tds_io_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_tds_io_l2clk_if.aclk; aclk_wmr__l2clk clkgen_tds_io_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_tds_io_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_tds_io_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_tds_io_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_tds_io_l2clk_if.l2clk; pce_ov__l2clk clkgen_tds_io_l2clk_if.pce_ov; por___l2clk clkgen_tds_io_l2clk_if.por_; scan_out__l2clk clkgen_tds_io_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_tds_io_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_tds_io_l2clk_if.wmr_; wmr_protect__l2clk clkgen_tds_io_l2clk_if.wmr_protect; } //----- port binding for clkgen_tds_io2x ----- bind CLKGEN_port clkgen_tds_io2x_bind { //---gclk is Vera interface CLOCK--- aclk__gclk clkgen_tds_io2x_gclk_if.aclk; aclk_wmr__gclk clkgen_tds_io2x_gclk_if.aclk_wmr; array_wr_inhibit__gclk clkgen_tds_io2x_gclk_if.array_wr_inhibit; bclk__gclk clkgen_tds_io2x_gclk_if.bclk; ccu_cmp_slow_sync_en__gclk clkgen_tds_io2x_gclk_if.ccu_cmp_slow_sync_en; ccu_div_ph__gclk clkgen_tds_io2x_gclk_if.ccu_div_ph; ccu_dr_sync_en__gclk void; ccu_io2x_sync_en__gclk void; ccu_serdes_dtm__gclk clkgen_tds_io2x_gclk_if.ccu_serdes_dtm; ccu_slow_cmp_sync_en__gclk clkgen_tds_io2x_gclk_if.ccu_slow_cmp_sync_en; clk_ext__gclk clkgen_tds_io2x_gclk_if.clk_ext; cluster_arst_l__gclk clkgen_tds_io2x_gclk_if.cluster_arst_l; cluster_div_en__gclk clkgen_tds_io2x_gclk_if.cluster_div_en; cmp_slow_sync_en__gclk clkgen_tds_io2x_gclk_if.cmp_slow_sync_en; dr_sync_en__gclk void; gclk clkgen_tds_io2x_gclk_if.gclk; io2x_sync_en__gclk void; l2clk__gclk clkgen_tds_io2x_gclk_if.l2clk; pce_ov__gclk clkgen_tds_io2x_gclk_if.pce_ov; por___gclk clkgen_tds_io2x_gclk_if.por_; rst_por___gclk clkgen_tds_io2x_gclk_if.rst_por_; rst_wmr___gclk clkgen_tds_io2x_gclk_if.rst_wmr_; rst_wmr_protect__gclk clkgen_tds_io2x_gclk_if.rst_wmr_protect; scan_en__gclk clkgen_tds_io2x_gclk_if.scan_en; scan_in__gclk clkgen_tds_io2x_gclk_if.scan_in; scan_out__gclk clkgen_tds_io2x_gclk_if.scan_out; slow_cmp_sync_en__gclk clkgen_tds_io2x_gclk_if.slow_cmp_sync_en; tcu_aclk__gclk clkgen_tds_io2x_gclk_if.tcu_aclk; tcu_atpg_mode__gclk clkgen_tds_io2x_gclk_if.tcu_atpg_mode; tcu_bclk__gclk clkgen_tds_io2x_gclk_if.tcu_bclk; tcu_clk_stop__gclk clkgen_tds_io2x_gclk_if.tcu_clk_stop; tcu_div_bypass__gclk clkgen_tds_io2x_gclk_if.tcu_div_bypass; tcu_pce_ov__gclk clkgen_tds_io2x_gclk_if.tcu_pce_ov; tcu_wr_inhibit__gclk clkgen_tds_io2x_gclk_if.tcu_wr_inhibit; wmr___gclk clkgen_tds_io2x_gclk_if.wmr_; wmr_protect__gclk clkgen_tds_io2x_gclk_if.wmr_protect; pc_clk__gclk void; pc_clk_sel__gclk void; test_clk__gclk void; test_clk_sel__gclk void; //---l2clk is Vera interface CLOCK--- aclk__l2clk clkgen_tds_io2x_l2clk_if.aclk; aclk_wmr__l2clk clkgen_tds_io2x_l2clk_if.aclk_wmr; array_wr_inhibit__l2clk clkgen_tds_io2x_l2clk_if.array_wr_inhibit; bclk__l2clk clkgen_tds_io2x_l2clk_if.bclk; cmp_slow_sync_en__l2clk clkgen_tds_io2x_l2clk_if.cmp_slow_sync_en; dr_sync_en__l2clk void; io2x_sync_en__l2clk void; l2clk clkgen_tds_io2x_l2clk_if.l2clk; pce_ov__l2clk clkgen_tds_io2x_l2clk_if.pce_ov; por___l2clk clkgen_tds_io2x_l2clk_if.por_; scan_out__l2clk clkgen_tds_io2x_l2clk_if.scan_out; slow_cmp_sync_en__l2clk clkgen_tds_io2x_l2clk_if.slow_cmp_sync_en; wmr___l2clk clkgen_tds_io2x_l2clk_if.wmr_; wmr_protect__l2clk clkgen_tds_io2x_l2clk_if.wmr_protect; } #endif #endif #endif // #ifdef FC_BENCH #endif // #ifndef INC_CLUSTER_HDR_BIND_VRI