// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: diag_ccu_clks_vars.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ CCU_clk_port ccu_clk_port = ccu_clk_bind; CCU_mon_port ccu_mon_port = ccu_mon_bind; UCB_port ccu_ucb_port = ccu_ucb_mon_bind; //--- ports for cluster headers in ccu_mon.v ----- //added to remove NIU related signals #ifndef FC_NO_NIU_T2 CLKGEN_port clkgen_ccumon_dr_port = clkgen_ccumon_dr_bind; CLKGEN_port clkgen_ccumon_io2x_port = clkgen_ccumon_io2x_bind; #endif //--- ports for cluster headers of blocks in TCU_SAT (listed in alphabetical order) ----- CLKGEN_port clkgen_ccu_cmp_port = clkgen_ccu_cmp_bind; CLKGEN_port clkgen_ccu_io_port = clkgen_ccu_io_bind; CLKGEN_port clkgen_db0_cmp_port = clkgen_db0_cmp_bind; CLKGEN_port clkgen_db0_io_port = clkgen_db0_io_bind; CLKGEN_port clkgen_db1_cmp_port = clkgen_db1_cmp_bind; CLKGEN_port clkgen_db1_io_port = clkgen_db1_io_bind; CLKGEN_port clkgen_efu_cmp_port = clkgen_efu_cmp_bind; CLKGEN_port clkgen_efu_io_port = clkgen_efu_io_bind; CLKGEN_port clkgen_mio_0_cmp_port = clkgen_mio_0_cmp_bind; CLKGEN_port clkgen_mio_1_cmp_port = clkgen_mio_1_cmp_bind; CLKGEN_port clkgen_mio_2_cmp_port = clkgen_mio_2_cmp_bind; CLKGEN_port clkgen_mio_3_cmp_port = clkgen_mio_3_cmp_bind; CLKGEN_port clkgen_mio_io_port = clkgen_mio_io_bind; CLKGEN_port clkgen_ncu_cmp_port = clkgen_ncu_cmp_bind; CLKGEN_port clkgen_ncu_io_port = clkgen_ncu_io_bind; CLKGEN_port clkgen_rst_cmp_port = clkgen_rst_cmp_bind; CLKGEN_port clkgen_rst_io_port = clkgen_rst_io_bind; CLKGEN_port clkgen_tcu_cmp_port = clkgen_tcu_cmp_bind; CLKGEN_port clkgen_tcu_io_port = clkgen_tcu_io_bind; //--- ports for cluster headers of blocks not in TCU_SAT (listed in alphabetical order) --- //--- WARNING: this file is intended for TCU SAT and fc_scan benches only (ie. fc bench)--- #ifdef FC_SCAN_BENCH CLKGEN_port clkgen_ccx_cmp_port = clkgen_ccx_cmp_bind; CLKGEN_port clkgen_dmu_io_port = clkgen_dmu_io_bind; CLKGEN_port clkgen_l2b0_cmp_port = clkgen_l2b0_cmp_bind; CLKGEN_port clkgen_l2b1_cmp_port = clkgen_l2b1_cmp_bind; CLKGEN_port clkgen_l2b2_cmp_port = clkgen_l2b2_cmp_bind; CLKGEN_port clkgen_l2b3_cmp_port = clkgen_l2b3_cmp_bind; CLKGEN_port clkgen_l2b4_cmp_port = clkgen_l2b4_cmp_bind; CLKGEN_port clkgen_l2b5_cmp_port = clkgen_l2b5_cmp_bind; CLKGEN_port clkgen_l2b6_cmp_port = clkgen_l2b6_cmp_bind; CLKGEN_port clkgen_l2b7_cmp_port = clkgen_l2b7_cmp_bind; CLKGEN_port clkgen_l2d0_cmp_port = clkgen_l2d0_cmp_bind; CLKGEN_port clkgen_l2d1_cmp_port = clkgen_l2d1_cmp_bind; CLKGEN_port clkgen_l2d2_cmp_port = clkgen_l2d2_cmp_bind; CLKGEN_port clkgen_l2d3_cmp_port = clkgen_l2d3_cmp_bind; CLKGEN_port clkgen_l2d4_cmp_port = clkgen_l2d4_cmp_bind; CLKGEN_port clkgen_l2d5_cmp_port = clkgen_l2d5_cmp_bind; CLKGEN_port clkgen_l2d6_cmp_port = clkgen_l2d6_cmp_bind; CLKGEN_port clkgen_l2d7_cmp_port = clkgen_l2d7_cmp_bind; CLKGEN_port clkgen_l2t0_cmp_port = clkgen_l2t0_cmp_bind; CLKGEN_port clkgen_l2t1_cmp_port = clkgen_l2t1_cmp_bind; CLKGEN_port clkgen_l2t2_cmp_port = clkgen_l2t2_cmp_bind; CLKGEN_port clkgen_l2t3_cmp_port = clkgen_l2t3_cmp_bind; CLKGEN_port clkgen_l2t4_cmp_port = clkgen_l2t4_cmp_bind; CLKGEN_port clkgen_l2t5_cmp_port = clkgen_l2t5_cmp_bind; CLKGEN_port clkgen_l2t6_cmp_port = clkgen_l2t6_cmp_bind; CLKGEN_port clkgen_l2t7_cmp_port = clkgen_l2t7_cmp_bind; CLKGEN_port clkgen_mac_io_port = clkgen_mac_io_bind; CLKGEN_port clkgen_mcu0_cmp_port = clkgen_mcu0_cmp_bind; CLKGEN_port clkgen_mcu0_dr_port = clkgen_mcu0_dr_bind; CLKGEN_port clkgen_mcu0_io_port = clkgen_mcu0_io_bind; CLKGEN_port clkgen_mcu1_cmp_port = clkgen_mcu1_cmp_bind; CLKGEN_port clkgen_mcu1_dr_port = clkgen_mcu1_dr_bind; CLKGEN_port clkgen_mcu1_io_port = clkgen_mcu1_io_bind; CLKGEN_port clkgen_mcu2_cmp_port = clkgen_mcu2_cmp_bind; CLKGEN_port clkgen_mcu2_dr_port = clkgen_mcu2_dr_bind; CLKGEN_port clkgen_mcu2_io_port = clkgen_mcu2_io_bind; CLKGEN_port clkgen_mcu3_cmp_port = clkgen_mcu3_cmp_bind; CLKGEN_port clkgen_mcu3_dr_port = clkgen_mcu3_dr_bind; CLKGEN_port clkgen_mcu3_io_port = clkgen_mcu3_io_bind; CLKGEN_port clkgen_peu_io_port = clkgen_peu_io_bind; CLKGEN_port clkgen_peu_pc_port = clkgen_peu_pc_bind; #ifndef FC_NO_NIU_T2 CLKGEN_port clkgen_rdp_io_port = clkgen_rdp_io_bind; CLKGEN_port clkgen_rdp_io2x_port = clkgen_rdp_io2x_bind; CLKGEN_port clkgen_rtx_io_port = clkgen_rtx_io_bind; CLKGEN_port clkgen_rtx_io2x_port = clkgen_rtx_io2x_bind; #endif CLKGEN_port clkgen_sii_cmp_port = clkgen_sii_cmp_bind; CLKGEN_port clkgen_sii_io_port = clkgen_sii_io_bind; CLKGEN_port clkgen_sio_cmp_port = clkgen_sio_cmp_bind; CLKGEN_port clkgen_sio_io_port = clkgen_sio_io_bind; CLKGEN_port clkgen_spc0_cmp_port = clkgen_spc0_cmp_bind; CLKGEN_port clkgen_spc1_cmp_port = clkgen_spc1_cmp_bind; CLKGEN_port clkgen_spc2_cmp_port = clkgen_spc2_cmp_bind; CLKGEN_port clkgen_spc3_cmp_port = clkgen_spc3_cmp_bind; CLKGEN_port clkgen_spc4_cmp_port = clkgen_spc4_cmp_bind; CLKGEN_port clkgen_spc5_cmp_port = clkgen_spc5_cmp_bind; CLKGEN_port clkgen_spc6_cmp_port = clkgen_spc6_cmp_bind; CLKGEN_port clkgen_spc7_cmp_port = clkgen_spc7_cmp_bind; #ifndef FC_NO_NIU_T2 CLKGEN_port clkgen_tds_io_port = clkgen_tds_io_bind; CLKGEN_port clkgen_tds_io2x_port = clkgen_tds_io2x_bind; #endif #endif // end of '#ifdef FC_SCAN_BENCH' //---- vars for packets (ie. data structures) ------ CCU_clk_packet ccu_clk_pkt; CCU_clks_states ccu_states; //--- var for CCU checker --- CCU_checker ccu_checker; //--- vars for cluster header checkers of blks in TCU SAT (listed in alphabetical order)--- CLUSTER_hdr_chkr clkgen_ccu_cmp_chkr; CLUSTER_hdr_chkr clkgen_ccu_io_chkr; CLUSTER_hdr_chkr clkgen_db0_cmp_chkr; CLUSTER_hdr_chkr clkgen_db0_io_chkr; CLUSTER_hdr_chkr clkgen_db1_cmp_chkr; CLUSTER_hdr_chkr clkgen_db1_io_chkr; CLUSTER_hdr_chkr clkgen_efu_cmp_chkr; CLUSTER_hdr_chkr clkgen_efu_io_chkr; CLUSTER_hdr_chkr clkgen_mio_0_cmp_chkr; CLUSTER_hdr_chkr clkgen_mio_1_cmp_chkr; CLUSTER_hdr_chkr clkgen_mio_2_cmp_chkr; CLUSTER_hdr_chkr clkgen_mio_3_cmp_chkr; CLUSTER_hdr_chkr clkgen_mio_io_chkr; CLUSTER_hdr_chkr clkgen_ncu_cmp_chkr; CLUSTER_hdr_chkr clkgen_ncu_io_chkr; CLUSTER_hdr_chkr clkgen_rst_cmp_chkr; CLUSTER_hdr_chkr clkgen_rst_io_chkr; CLUSTER_hdr_chkr clkgen_tcu_cmp_chkr; CLUSTER_hdr_chkr clkgen_tcu_io_chkr; //--- vars for cluster header checkers of blks not in TCU SAT (listed in alphabetical order)--- CLUSTER_hdr_chkr clkgen_ccx_cmp_chkr; CLUSTER_hdr_chkr clkgen_dmu_io_chkr; CLUSTER_hdr_chkr clkgen_l2b0_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b1_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b2_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b3_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b4_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b5_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b6_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2b7_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d0_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d1_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d2_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d3_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d4_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d5_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d6_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2d7_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t0_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t1_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t2_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t3_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t4_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t5_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t6_cmp_chkr; CLUSTER_hdr_chkr clkgen_l2t7_cmp_chkr; CLUSTER_hdr_chkr clkgen_mac_io_chkr; CLUSTER_hdr_chkr clkgen_mcu0_cmp_chkr; CLUSTER_hdr_chkr clkgen_mcu0_dr_chkr; CLUSTER_hdr_chkr clkgen_mcu0_io_chkr; CLUSTER_hdr_chkr clkgen_mcu1_cmp_chkr; CLUSTER_hdr_chkr clkgen_mcu1_dr_chkr; CLUSTER_hdr_chkr clkgen_mcu1_io_chkr; CLUSTER_hdr_chkr clkgen_mcu2_cmp_chkr; CLUSTER_hdr_chkr clkgen_mcu2_dr_chkr; CLUSTER_hdr_chkr clkgen_mcu2_io_chkr; CLUSTER_hdr_chkr clkgen_mcu3_cmp_chkr; CLUSTER_hdr_chkr clkgen_mcu3_dr_chkr; CLUSTER_hdr_chkr clkgen_mcu3_io_chkr; CLUSTER_hdr_chkr clkgen_peu_io_chkr; CLUSTER_hdr_chkr clkgen_peu_pc_chkr; #ifndef FC_NO_NIU_T2 CLUSTER_hdr_chkr clkgen_rdp_io_chkr; CLUSTER_hdr_chkr clkgen_rdp_io2x_chkr; CLUSTER_hdr_chkr clkgen_rtx_io_chkr; CLUSTER_hdr_chkr clkgen_rtx_io2x_chkr; #endif CLUSTER_hdr_chkr clkgen_sii_cmp_chkr; CLUSTER_hdr_chkr clkgen_sii_io_chkr; CLUSTER_hdr_chkr clkgen_sio_cmp_chkr; CLUSTER_hdr_chkr clkgen_sio_io_chkr; CLUSTER_hdr_chkr clkgen_spc0_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc1_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc2_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc3_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc4_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc5_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc6_cmp_chkr; CLUSTER_hdr_chkr clkgen_spc7_cmp_chkr; #ifndef FC_NO_NIU_T2 CLUSTER_hdr_chkr clkgen_tds_io_chkr; CLUSTER_hdr_chkr clkgen_tds_io2x_chkr; #endif