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920dae64 AT |
1 | /* |
2 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
3 | * Use is subject to license terms. | |
4 | */ | |
5 | ||
6 | /* | |
7 | * The machine description files are derived from machine description | |
8 | * binaries in OpenSPARC T2 legion simulation directory. | |
9 | */ | |
10 | ||
11 | #include "xilinx_t1_system_config.h" | |
12 | ||
13 | node root root { | |
14 | ||
15 | content-version = 0x100000000; | |
16 | stick-frequency = T1_FPGA_STICK_FREQ; | |
17 | fwd -> platform; | |
18 | fwd -> guests; | |
19 | fwd -> cpus; | |
20 | fwd -> memory; | |
21 | fwd -> maus; | |
22 | fwd -> cwqs; | |
23 | fwd -> devices; | |
24 | fwd -> ldc_endpoints; | |
25 | fwd -> consoles; | |
26 | fwd -> frag_space; | |
27 | hvuart = T1_FPGA_UART_BASE; | |
28 | tod = 0x0; | |
29 | } | |
30 | ||
31 | ||
32 | node platform platform { | |
33 | ||
34 | back -> root; | |
35 | stick-frequency = T1_FPGA_STICK_FREQ; | |
36 | } | |
37 | ||
38 | ||
39 | node guests guests { | |
40 | ||
41 | back -> root; | |
42 | fwd -> guest; | |
43 | } | |
44 | ||
45 | ||
46 | node cpus cpus { | |
47 | ||
48 | back -> root; | |
49 | fwd -> cpu; | |
50 | fwd -> cpu_1; | |
51 | fwd -> cpu_2; | |
52 | fwd -> cpu_3; | |
53 | } | |
54 | ||
55 | ||
56 | node memory memory { | |
57 | ||
58 | back -> root; | |
59 | fwd -> mblock; | |
60 | } | |
61 | ||
62 | ||
63 | node maus maus { | |
64 | ||
65 | back -> root; | |
66 | } | |
67 | ||
68 | ||
69 | node cwqs cwqs { | |
70 | ||
71 | back -> root; | |
72 | } | |
73 | ||
74 | ||
75 | node devices devices { | |
76 | ||
77 | back -> root; | |
78 | fwd -> pcie_bus; | |
79 | } | |
80 | ||
81 | ||
82 | node ldc_endpoints ldc_endpoints { | |
83 | ||
84 | back -> root; | |
85 | fwd -> ldc_endpoint; | |
86 | fwd -> ldc_endpoint_1; | |
87 | fwd -> ldc_endpoint_2; | |
88 | fwd -> ldc_endpoint_3; | |
89 | } | |
90 | ||
91 | ||
92 | node consoles consoles { | |
93 | ||
94 | back -> root; | |
95 | fwd -> console; | |
96 | } | |
97 | ||
98 | ||
99 | node guest guest { | |
100 | ||
101 | back -> guests; | |
102 | name = "domain0"; | |
103 | gid = 0x0; | |
104 | resource_id = 0x0; | |
105 | pid = 0x1; | |
106 | tod-offset = 0x0; | |
107 | reset-reason = 0x0; | |
108 | perfctraccess = 0x0; | |
109 | perfctrhtaccess = 0x0; | |
110 | rngctlaccessible = 0x0; | |
111 | diagpriv = 0x0; | |
112 | fwd -> virtual_devices; | |
113 | fwd -> channel_devices; | |
114 | fwd -> pcie_bus; | |
115 | fwd -> cpu; | |
116 | fwd -> cpu_1; | |
117 | fwd -> cpu_2; | |
118 | fwd -> cpu_3; | |
119 | fwd -> mblock; | |
120 | mdpa = T1_FPGA_GUEST_MD_ADDR; | |
121 | fwd -> ldc_endpoint; | |
122 | fwd -> ldc_endpoint_1; | |
123 | fwd -> ldc_endpoint_3; | |
124 | rombase = ROMBASE; | |
125 | romsize = ROMSIZE; | |
126 | nvbase = T1_FPGA_NVRAM_ADDR; | |
127 | nvsize = T1_FPGA_NVRAM_SIZE; | |
128 | diskpa = T1_FPGA_RAM_DISK_ADDR; | |
129 | fwd -> console; | |
130 | fwd -> snet; | |
131 | } | |
132 | ||
133 | ||
134 | node virtual_devices virtual_devices { | |
135 | ||
136 | back -> guest; | |
137 | cfghandle = 0x100; | |
138 | } | |
139 | ||
140 | ||
141 | node channel_devices channel_devices { | |
142 | ||
143 | back -> guest; | |
144 | cfghandle = 0x200; | |
145 | } | |
146 | ||
147 | ||
148 | node pcie_bus pcie_bus { | |
149 | ||
150 | back -> guest; | |
151 | back -> devices; | |
152 | resource_id = 0x0; | |
153 | cfghandle = 0x0; | |
154 | gid = 0x0; | |
155 | } | |
156 | ||
157 | ||
158 | node cpu cpu { | |
159 | ||
160 | back -> cpus; | |
161 | back -> guest; | |
162 | pid = 0x0; | |
163 | vid = 0x0; | |
164 | resource_id = 0x0; | |
165 | gid = 0x0; | |
166 | partid = 0x1; | |
167 | } | |
168 | ||
169 | node cpu cpu_1 { | |
170 | ||
171 | back -> cpus; | |
172 | back -> guest; | |
173 | pid = 0x1; | |
174 | vid = 0x1; | |
175 | resource_id = 0x1; | |
176 | gid = 0x0; | |
177 | partid = 0x1; | |
178 | } | |
179 | ||
180 | ||
181 | node cpu cpu_2 { | |
182 | ||
183 | back -> cpus; | |
184 | back -> guest; | |
185 | pid = 0x2; | |
186 | vid = 0x2; | |
187 | resource_id = 0x2; | |
188 | gid = 0x0; | |
189 | partid = 0x1; | |
190 | } | |
191 | ||
192 | ||
193 | node cpu cpu_3 { | |
194 | ||
195 | back -> cpus; | |
196 | back -> guest; | |
197 | pid = 0x3; | |
198 | vid = 0x3; | |
199 | resource_id = 0x3; | |
200 | gid = 0x0; | |
201 | partid = 0x1; | |
202 | } | |
203 | ||
204 | node mblock mblock { | |
205 | ||
206 | back -> memory; | |
207 | back -> guest; | |
208 | membase = T1_FPGA_GUEST_MEMBASE; | |
209 | memsize = T1_FPGA_GUEST_MEMSIZE; | |
210 | realbase = T1_FPGA_GUEST_REALBASE; | |
211 | resource_id = 0x0; | |
212 | } | |
213 | ||
214 | ||
215 | node ldc_endpoint ldc_endpoint { | |
216 | ||
217 | back -> ldc_endpoints; | |
218 | back -> guest; | |
219 | target_type = 0x1; | |
220 | channel = 0x0; | |
221 | resource_id = 0x0; | |
222 | tx-ino = 0x0; | |
223 | rx-ino = 0x1; | |
224 | target_channel = 0x0; | |
225 | server_name = "hvctl"; | |
226 | server_ldom_name = "domain0"; | |
227 | server_instance = 0x0; | |
228 | } | |
229 | ||
230 | ||
231 | node ldc_endpoint ldc_endpoint_1 { | |
232 | ||
233 | back -> ldc_endpoints; | |
234 | back -> guest; | |
235 | target_type = 0x0; | |
236 | channel = 0x1; | |
237 | resource_id = 0x2; | |
238 | tx-ino = 0x2; | |
239 | rx-ino = 0x3; | |
240 | target_guest = 0x0; | |
241 | target_channel = 0x2; | |
242 | server_name = "vldc"; | |
243 | server_ldom_name = "domain0"; | |
244 | server_instance = 0x0; | |
245 | client_ldom_name = "domain0"; | |
246 | } | |
247 | ||
248 | ||
249 | node ldc_endpoint ldc_endpoint_2 { | |
250 | ||
251 | back -> ldc_endpoints; | |
252 | target_type = 0x0; | |
253 | channel = 0x0; | |
254 | resource_id = 0x1; | |
255 | target_guest = 0x0; | |
256 | target_channel = 0x0; | |
257 | server_name = "hvctl"; | |
258 | server_ldom_name = "domain0"; | |
259 | svc_id = 0x1; | |
260 | } | |
261 | ||
262 | ||
263 | node ldc_endpoint ldc_endpoint_3 { | |
264 | ||
265 | back -> ldc_endpoints; | |
266 | back -> guest; | |
267 | target_type = 0x0; | |
268 | channel = 0x2; | |
269 | resource_id = 0x3; | |
270 | tx-ino = 0x4; | |
271 | rx-ino = 0x5; | |
272 | target_guest = 0x0; | |
273 | target_channel = 0x1; | |
274 | server_name = "vldc"; | |
275 | server_ldom_name = "domain0"; | |
276 | server_instance = 0x0; | |
277 | client_ldom_name = "domain0"; | |
278 | } | |
279 | ||
280 | ||
281 | node frag_space frag_space { | |
282 | ||
283 | back -> root; | |
284 | fragsize = 0x80000; | |
285 | fwd -> frag_mblock; | |
286 | } | |
287 | ||
288 | ||
289 | node frag_mblock frag_mblock { | |
290 | ||
291 | back -> frag_space; | |
292 | base = 0x80000; | |
293 | size = 0x180000; | |
294 | } | |
295 | ||
296 | ||
297 | node console console { | |
298 | ||
299 | back -> consoles; | |
300 | back -> guest; | |
301 | ino = 0x11; | |
302 | resource_id = 0x0; | |
303 | uartbase = T1_FPGA_UART_BASE; | |
304 | } | |
305 | ||
306 | ||
307 | node snet snet { | |
308 | back -> guest; | |
309 | snet_ino = T1_FPGA_SNET_INO; | |
310 | resource_id = 0x0; | |
311 | snet_pa = T1_FPGA_SNET_BASE; | |
312 | } |