| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: mmu.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _NIAGARA2_MMU_H |
| 50 | #define _NIAGARA2_MMU_H |
| 51 | |
| 52 | #pragma ident "@(#)mmu.h 1.3 07/05/17 SMI" |
| 53 | |
| 54 | #ifdef __cplusplus |
| 55 | extern "C" { |
| 56 | #endif |
| 57 | |
| 58 | #include <segments.h> |
| 59 | |
| 60 | /* |
| 61 | * Niagara2 MMU properties |
| 62 | */ |
| 63 | #define NCTXS 8192 |
| 64 | #define NVABITS 48 |
| 65 | |
| 66 | #define PADDR_IO_BIT 39 |
| 67 | |
| 68 | /* |
| 69 | * MMU Register Array |
| 70 | */ |
| 71 | #define MAX_NMRA 8 |
| 72 | #define MRA_ENTRIES 8 |
| 73 | |
| 74 | /* |
| 75 | * Only support TSBs for the two hardware TSB page size indexes. |
| 76 | */ |
| 77 | #define MAX_NTSB 4 |
| 78 | |
| 79 | /* |
| 80 | * Support two sets of context registers. |
| 81 | */ |
| 82 | #define MAX_NCTX_INDEX 1 |
| 83 | |
| 84 | /* |
| 85 | * ASI_[DI]MMU registers |
| 86 | */ |
| 87 | #define MMU_SFSR 0x18 |
| 88 | #define MMU_SFAR 0x20 |
| 89 | #define MMU_TAG_ACCESS 0x30 |
| 90 | #define MMU_TAG_TARGET 0x00 |
| 91 | #define TAGACC_CTX_LSHIFT (64-13) |
| 92 | #define TAGTRG_CTX_RSHIFT 48 |
| 93 | #define TAGTRG_VA_LSHIFT 22 |
| 94 | #define MMU_PCONTEXT0 MMU_PCONTEXT |
| 95 | #define MMU_PCONTEXT1 0x108 |
| 96 | #define MMU_SCONTEXT0 MMU_SCONTEXT |
| 97 | #define MMU_SCONTEXT1 0x110 |
| 98 | |
| 99 | /* |
| 100 | * N2 HWTW |
| 101 | * |
| 102 | * RA bits[55:40} must be zero |
| 103 | */ |
| 104 | #define RA_55_40_SHIFT 40 |
| 105 | #define RA_55_40_MASK 0xffff |
| 106 | |
| 107 | /* |
| 108 | * I-/D-TSB Pointer registers |
| 109 | */ |
| 110 | #define MMU_ITSB_PTR_0 0x50 |
| 111 | #define MMU_ITSB_PTR_1 0x58 |
| 112 | #define MMU_ITSB_PTR_2 0x60 |
| 113 | #define MMU_ITSB_PTR_3 0x68 |
| 114 | #define MMU_DTSB_PTR_0 0x70 |
| 115 | #define MMU_DTSB_PTR_1 0x78 |
| 116 | #define MMU_DTSB_PTR_2 0x80 |
| 117 | #define MMU_DTSB_PTR_3 0x88 |
| 118 | |
| 119 | /* |
| 120 | * ASI_[ID]TSBBASE_CTX* |
| 121 | */ |
| 122 | #define TSB_SZ0_ENTRIES 512 |
| 123 | #define TSB_SZ0_SHIFT 9 /* LOG2(TSB_SZ0_ENTRIES) */ |
| 124 | #define TSB_MAX_SZCODE 15 |
| 125 | |
| 126 | /* |
| 127 | * ASI_[ID]TSB_CONFIG_CTX* |
| 128 | */ |
| 129 | #define ASI_TSB_CONFIG_PS1_SHIFT 8 |
| 130 | |
| 131 | #define ITLB_ENTRIES 64 |
| 132 | #define DTLB_ENTRIES 128 |
| 133 | |
| 134 | #define USE_TSB_PRIMARY_CTX 2 |
| 135 | #define USE_TSB_SECONDARY_CTX 1 |
| 136 | /* |
| 137 | * ASI_[DI]MMU_DEMAP |
| 138 | */ |
| 139 | #define DEMAP_ALL 0x2 |
| 140 | |
| 141 | /* |
| 142 | * ASI_TLB_INVALIDATE |
| 143 | */ |
| 144 | #define I_INVALIDATE 0x0 |
| 145 | #define D_INVALIDATE 0x8 |
| 146 | |
| 147 | /* |
| 148 | * ASI_MMU_CFG |
| 149 | */ |
| 150 | #define HWTW_CFG 0x40 |
| 151 | #define HWTW_BURST_MODE 0x1 |
| 152 | #define HWTW_PREDICT_MODE 0x2 |
| 153 | |
| 154 | /* |
| 155 | * ASI_HWTW_RANGE |
| 156 | */ |
| 157 | #define MMU_REAL_RANGE_0 0x108 |
| 158 | #define MMU_REAL_RANGE_1 0x110 |
| 159 | #define MMU_REAL_RANGE_2 0x118 |
| 160 | #define MMU_REAL_RANGE_3 0x120 |
| 161 | #define REALRANGE_BOUNDS_SHIFT 27 |
| 162 | #define REALRANGE_BASE_SHIFT 0 |
| 163 | #define MMU_PHYS_OFF_0 0x208 |
| 164 | #define MMU_PHYS_OFF_1 0x210 |
| 165 | #define MMU_PHYS_OFF_2 0x218 |
| 166 | #define MMU_PHYS_OFF_3 0x220 |
| 167 | #define PHYSOFF_SHIFT 13 |
| 168 | |
| 169 | /* |
| 170 | * ASI_MMU_TSB |
| 171 | */ |
| 172 | #define TSB_CFG_CTX0_0 0x10 |
| 173 | #define TSB_CFG_CTX0_1 0x18 |
| 174 | #define TSB_CFG_CTX0_2 0x20 |
| 175 | #define TSB_CFG_CTX0_3 0x28 |
| 176 | #define TSB_CFG_CTXN_0 0x30 |
| 177 | #define TSB_CFG_CTXN_1 0x38 |
| 178 | #define TSB_CFG_CTXN_2 0x40 |
| 179 | #define TSB_CFG_CTXN_3 0x48 |
| 180 | #define TSB_CFG_USE_CTX1_SHIFT 61 |
| 181 | #define TSB_CFG_USE_CTX0_SHIFT 62 |
| 182 | #define TSB_CFG_PGSZ_SHIFT 4 |
| 183 | #define TSB_CFG_RA_NOT_PA 0x100 |
| 184 | |
| 185 | #define MMU_VALID_FLAGS_MASK (MAP_ITLB | MAP_DTLB) |
| 186 | |
| 187 | /* |
| 188 | * Check that only valid flags bits are set and that at least |
| 189 | * one TLB selector is set. If optional flags are added, |
| 190 | * the simplistic 'brz' will have to be changed. |
| 191 | */ |
| 192 | /* BEGIN CSTYLED */ |
| 193 | #define CHECK_MMU_FLAGS(flags, fail_label) \ |
| 194 | brz,pn flags, fail_label ;\ |
| 195 | andncc flags, MMU_VALID_FLAGS_MASK, %g0 ;\ |
| 196 | bnz,pn %xcc, fail_label ;\ |
| 197 | nop |
| 198 | |
| 199 | /* |
| 200 | * Check the virtual address and context for validity |
| 201 | * on Niagara2 |
| 202 | */ |
| 203 | #define CHECK_CTX(ctx, fail_label, scr) \ |
| 204 | set NCTXS, scr ;\ |
| 205 | cmp ctx, scr ;\ |
| 206 | bgeu,pn %xcc, fail_label ;\ |
| 207 | nop |
| 208 | #define CHECK_VA_CTX(va, ctx, fail_label, scr) \ |
| 209 | sllx va, (64 - NVABITS), scr ;\ |
| 210 | srax scr, (64 - NVABITS), scr ;\ |
| 211 | cmp va, scr ;\ |
| 212 | bne,pn %xcc, fail_label ;\ |
| 213 | CHECK_CTX(ctx, fail_label, scr) |
| 214 | |
| 215 | #define SET_TTE_LOCK_BIT(reg, scr) |
| 216 | #define CLEAR_TTE_LOCK_BIT(reg, scr) |
| 217 | |
| 218 | /* END CSTYLED */ |
| 219 | |
| 220 | /* |
| 221 | * Supported page size encodings for Niagara2 |
| 222 | */ |
| 223 | #define TTE_VALIDSIZEARRAY \ |
| 224 | ((1 << 0) | /* 8K */ \ |
| 225 | (1 << 1) | /* 64k */ \ |
| 226 | (1 << 3) | /* 4M */ \ |
| 227 | (1 << 5)) /* 256M */ |
| 228 | |
| 229 | /* Largest page size is 28bits */ |
| 230 | #define LARGEST_PG_SIZE_BITS 28 |
| 231 | |
| 232 | #ifdef __cplusplus |
| 233 | } |
| 234 | #endif |
| 235 | |
| 236 | #endif /* _NIAGARA2_MMU_H */ |