| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: niu.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _NIAGARA2_NIU_H |
| 50 | #define _NIAGARA2_NIU_H |
| 51 | |
| 52 | #pragma ident "@(#)niu.h 1.7 07/08/16 SMI" |
| 53 | |
| 54 | #ifdef __cplusplus |
| 55 | extern "C" { |
| 56 | #endif |
| 57 | |
| 58 | #include <vdev_intr.h> |
| 59 | #include <error_defs.h> |
| 60 | |
| 61 | /* |
| 62 | * Niagara2 NIU definitions |
| 63 | */ |
| 64 | |
| 65 | #define NIU_ADDR_BASE 0x8100000000 |
| 66 | |
| 67 | #define NIU_ADDR_LIMIT (NIU_ADDR_BASE + 0x4000000) |
| 68 | |
| 69 | #define NIU_RX_DMA_N_CH 16 |
| 70 | #define NIU_TX_DMA_N_CH 16 |
| 71 | |
| 72 | #define NIU_LDN_RX_DMA_CH0 0 |
| 73 | #define NIU_LDN_RX_DMA_CH1 1 |
| 74 | #define NIU_LDN_RX_DMA_CH2 2 |
| 75 | #define NIU_LDN_RX_DMA_CH3 3 |
| 76 | #define NIU_LDN_RX_DMA_CH4 4 |
| 77 | #define NIU_LDN_RX_DMA_CH5 5 |
| 78 | #define NIU_LDN_RX_DMA_CH6 6 |
| 79 | #define NIU_LDN_RX_DMA_CH7 7 |
| 80 | #define NIU_LDN_RX_DMA_CH8 8 |
| 81 | #define NIU_LDN_RX_DMA_CH9 9 |
| 82 | #define NIU_LDN_RX_DMA_CH10 10 |
| 83 | #define NIU_LDN_RX_DMA_CH11 11 |
| 84 | #define NIU_LDN_RX_DMA_CH12 12 |
| 85 | #define NIU_LDN_RX_DMA_CH13 13 |
| 86 | #define NIU_LDN_RX_DMA_CH14 14 |
| 87 | #define NIU_LDN_RX_DMA_CH15 15 |
| 88 | #define NIU_LDN_TX_DMA_CH0 32 |
| 89 | #define NIU_LDN_TX_DMA_CH1 33 |
| 90 | #define NIU_LDN_TX_DMA_CH2 34 |
| 91 | #define NIU_LDN_TX_DMA_CH3 35 |
| 92 | #define NIU_LDN_TX_DMA_CH4 36 |
| 93 | #define NIU_LDN_TX_DMA_CH5 37 |
| 94 | #define NIU_LDN_TX_DMA_CH6 38 |
| 95 | #define NIU_LDN_TX_DMA_CH7 39 |
| 96 | #define NIU_LDN_TX_DMA_CH8 40 |
| 97 | #define NIU_LDN_TX_DMA_CH9 41 |
| 98 | #define NIU_LDN_TX_DMA_CH10 42 |
| 99 | #define NIU_LDN_TX_DMA_CH11 43 |
| 100 | #define NIU_LDN_TX_DMA_CH12 44 |
| 101 | #define NIU_LDN_TX_DMA_CH13 45 |
| 102 | #define NIU_LDN_TX_DMA_CH14 46 |
| 103 | #define NIU_LDN_TX_DMA_CH15 47 |
| 104 | #define NIU_LDN_MIF 63 |
| 105 | #define NIU_LDN_MAC0 64 |
| 106 | #define NIU_LDN_MAC1 65 |
| 107 | #define NIU_LDN_SYSERR 68 |
| 108 | |
| 109 | |
| 110 | /* |
| 111 | * PIO region |
| 112 | */ |
| 113 | #define NIU_PIO_BASE (NIU_ADDR_BASE + 0x0) |
| 114 | |
| 115 | |
| 116 | /* |
| 117 | * PIO function zero control (PIO_FZC) region |
| 118 | */ |
| 119 | #define NIU_PIO_FZC_BASE (NIU_PIO_BASE + 0x80000) |
| 120 | |
| 121 | /* |
| 122 | * DMA channel binding registers |
| 123 | */ |
| 124 | #define NIU_DMA_BIND_REG (NIU_PIO_FZC_BASE + 0x10000) |
| 125 | #define NIU_DMA_BIND_REG_STEP 0x8 |
| 126 | #define NIU_DMA_BIND_N_REG 64 |
| 127 | |
| 128 | /* |
| 129 | * System interrupt data registers |
| 130 | */ |
| 131 | #define NIU_SID_REG (NIU_PIO_FZC_BASE + 0x10200) |
| 132 | #define NIU_SID_REG_STEP 0x8 |
| 133 | #define NIU_SID_N_REG 64 |
| 134 | |
| 135 | /* |
| 136 | * Logical device group registers |
| 137 | */ |
| 138 | #define NIU_LDG_NUM_REG (NIU_PIO_FZC_BASE + 0x20000) |
| 139 | #define NIU_LDG_NUM_REG_STEP 0x8 |
| 140 | #define NIU_LDG_NUM_REG_SHIFT 3 /* log2(NIU_LDG_NUM_REG_STEP) */ |
| 141 | #define NIU_LDG_NUM_N_REG 69 |
| 142 | |
| 143 | |
| 144 | /* |
| 145 | * PIO media adaptation controller (PIO_MAC) region |
| 146 | */ |
| 147 | #define NIU_PIO_MAC_BASE (NIU_PIO_BASE + 0x180000) |
| 148 | |
| 149 | /* |
| 150 | * xMAC configuration register |
| 151 | */ |
| 152 | #define NIU_XMAC_CFG_REG (NIU_PIO_MAC_BASE + 0x60) |
| 153 | #define NIU_XMAC_CFG_REG_STEP 0x6000 |
| 154 | #define NIU_XMAC_CFG_REG_0 (NIU_XMAC_CFG_REG) |
| 155 | #define NIU_XMAC_CFG_REG_1 (NIU_XMAC_CFG_REG + NIU_XMAC_CFG_REG_STEP) |
| 156 | #define XMAC_TX_ENABLE (1 << 0) |
| 157 | #define XMAC_RX_ENABLE (1 << 8) |
| 158 | |
| 159 | /* |
| 160 | * xMAC state machines register |
| 161 | */ |
| 162 | #define NIU_XMAC_SM_REG (NIU_PIO_MAC_BASE + 0x1A8) |
| 163 | #define NIU_XMAC_SM_REG_STEP 0x6000 |
| 164 | #define NIU_XMAC_SM_REG_0 (NIU_XMAC_SM_REG) |
| 165 | #define NIU_XMAC_SM_REG_1 (NIU_XMAC_SM_REG + NIU_XMAC_SM_REG_STEP) |
| 166 | #define XMAC_SM_RX_QST_ST (1<<8) |
| 167 | |
| 168 | /* |
| 169 | * TxMAC Software Reset Register |
| 170 | */ |
| 171 | #define NIU_XTXMAC_RST_REG (NIU_PIO_MAC_BASE + 0x0) |
| 172 | #define NIU_XTXMAC_RST_REG_STEP 0x6000 |
| 173 | #define NIU_XTXMAC_RST_REG_0 (NIU_XTXMAC_RST_REG) |
| 174 | #define NIU_XTXMAC_RST_REG_1 (NIU_XTXMAC_RST_REG + NIU_XTXMAC_RST_REG_STEP) |
| 175 | #define XTXMAC_REG_RST (1 << 1) |
| 176 | #define XTXMAC_SM_RST (1 << 0) |
| 177 | |
| 178 | /* |
| 179 | * RxMAC software reset register |
| 180 | */ |
| 181 | #define NIU_XRXMAC_RST_REG (NIU_PIO_MAC_BASE + 0x8) |
| 182 | #define NIU_XRXMAC_RST_REG_STEP 0x6000 |
| 183 | #define NIU_XRXMAC_RST_REG_0 (NIU_XRXMAC_RST_REG) |
| 184 | #define NIU_XRXMAC_RST_REG_1 (NIU_XRXMAC_RST_REG + NIU_XRXMAC_RST_REG_STEP) |
| 185 | #define XRXMAC_REG_RST (1 << 1) |
| 186 | #define XRXMAC_SM_RST (1 << 0) |
| 187 | |
| 188 | |
| 189 | /* |
| 190 | * PIO inport packet processor (PIO_IPP) region |
| 191 | */ |
| 192 | #define NIU_PIO_IPP_BASE (NIU_PIO_BASE + 0x280000) |
| 193 | |
| 194 | /* |
| 195 | * IPP configuration register |
| 196 | */ |
| 197 | #define NIU_IPP_CFG_REG (NIU_PIO_IPP_BASE + 0x0) |
| 198 | #define NIU_IPP_CFG_REG_STEP 0x8000 |
| 199 | #define NIU_IPP_CFG_REG_0 (NIU_IPP_CFG_REG) |
| 200 | #define NIU_IPP_CFG_REG_1 (NIU_IPP_CFG_REG + NIU_IPP_CFG_REG_STEP) |
| 201 | #define IPP_ENABLE (1 << 0) |
| 202 | #define IPP_RESET (1 << 31) |
| 203 | |
| 204 | /* |
| 205 | * PIO zero copy processor (PIO_ZCP) region |
| 206 | */ |
| 207 | #define NIU_PIO_ZCP_BASE (NIU_PIO_BASE + 0x580000) |
| 208 | |
| 209 | /* |
| 210 | * Control FIFO Reset register |
| 211 | */ |
| 212 | #define NIU_CFIFO_RESET_REG (NIU_PIO_ZCP_BASE + 0x98) |
| 213 | #define RESET_CFIFO1 (1 << 1) |
| 214 | #define RESET_CFIFO0 (1 << 0) |
| 215 | |
| 216 | /* |
| 217 | * PIO DMA control (DMC) region |
| 218 | */ |
| 219 | #define NIU_PIO_DMC_BASE (NIU_PIO_BASE + 0x600000) |
| 220 | |
| 221 | /* |
| 222 | * Receive DMA configuration register 1 |
| 223 | */ |
| 224 | #define NIU_RX_CFG1_REG (NIU_PIO_DMC_BASE + 0x0) |
| 225 | #define NIU_RX_CFG1_REG_STEP 0x200 |
| 226 | #define NIU_RX_CFG1_N_REG 16 |
| 227 | #define RX_DMA_ENABLE (1 << 31) |
| 228 | #define RX_DMA_RESET (1 << 30) |
| 229 | #define RX_DMA_QUIESCED (1 << 29) |
| 230 | |
| 231 | /* |
| 232 | * Transmit DMA control and status register |
| 233 | */ |
| 234 | #define NIU_TX_CTL_ST_REG (NIU_PIO_DMC_BASE + 0x40028) |
| 235 | #define NIU_TX_CTL_ST_REG_STEP 0x200 |
| 236 | #define NIU_TX_CTL_ST_REG_SHIFT 9 |
| 237 | #define NIU_TX_CTL_ST_N_REG 16 |
| 238 | #define TX_CTL_RESET (1 << 31) |
| 239 | #define TX_CTL_RESET_STS (1 << 30) |
| 240 | #define TX_CTL_STOP_N_GO (1 << 28) |
| 241 | #define TX_CTL_SNG_STS (1 << 27) |
| 242 | |
| 243 | |
| 244 | /* |
| 245 | * PIO function zero DMA control (FZC_DMC) region |
| 246 | */ |
| 247 | #define NIU_PIO_FZC_DMC_BASE (NIU_PIO_BASE + 0x680000) |
| 248 | |
| 249 | /* |
| 250 | * Recieve DMA channel logical page registers |
| 251 | */ |
| 252 | #define NIU_RX_LPG_VALID_REG (NIU_PIO_FZC_DMC_BASE + 0x20000) |
| 253 | #define NIU_RX_LPG_V_PG0_VALUE 0x1 /* page 0, valid */ |
| 254 | #define NIU_RX_LPG_V_PG1_VALUE 0x2 /* page 1, valid */ |
| 255 | |
| 256 | #define NIU_RX_LPG_MASK1_REG (NIU_PIO_FZC_DMC_BASE + 0x20008) |
| 257 | #define NIU_RX_LPG_MASK2_REG (NIU_PIO_FZC_DMC_BASE + 0x20018) |
| 258 | |
| 259 | #define NIU_RX_LPG_VALUE1_REG (NIU_PIO_FZC_DMC_BASE + 0x20010) |
| 260 | #define NIU_RX_LPG_VALUE2_REG (NIU_PIO_FZC_DMC_BASE + 0x20020) |
| 261 | |
| 262 | #define NIU_RX_LPG_RELO1_REG (NIU_PIO_FZC_DMC_BASE + 0x20028) |
| 263 | #define NIU_RX_LPG_RELO2_REG (NIU_PIO_FZC_DMC_BASE + 0x20030) |
| 264 | |
| 265 | #define NIU_RX_LPG_REG_STEP 0x40 |
| 266 | #define NIU_RX_LPG_REG_SHIFT 6 /* log2(NIU_RX_LPG_REG_STEP) */ |
| 267 | #define NIU_RX_LPG_CH_N_REG 2 |
| 268 | |
| 269 | #define NIU_RX_LPG_SHIFT 12 |
| 270 | |
| 271 | /* |
| 272 | * Transmit DMA channel logical page registers |
| 273 | */ |
| 274 | #define NIU_TX_LPG_VALID_REG (NIU_PIO_FZC_DMC_BASE + 0x40000) |
| 275 | #define NIU_TX_LPG_V_PG0_VALUE 0x1 /* page 0, valid */ |
| 276 | #define NIU_TX_LPG_V_PG1_VALUE 0x2 /* page 1, valid */ |
| 277 | |
| 278 | #define NIU_TX_LPG_MASK1_REG (NIU_PIO_FZC_DMC_BASE + 0x40008) |
| 279 | #define NIU_TX_LPG_MASK2_REG (NIU_PIO_FZC_DMC_BASE + 0x40018) |
| 280 | |
| 281 | #define NIU_TX_LPG_VALUE1_REG (NIU_PIO_FZC_DMC_BASE + 0x40010) |
| 282 | #define NIU_TX_LPG_VALUE2_REG (NIU_PIO_FZC_DMC_BASE + 0x40020) |
| 283 | |
| 284 | #define NIU_TX_LPG_RELO1_REG (NIU_PIO_FZC_DMC_BASE + 0x40028) |
| 285 | #define NIU_TX_LPG_RELO2_REG (NIU_PIO_FZC_DMC_BASE + 0x40030) |
| 286 | |
| 287 | #define NIU_TX_LPG_REG_STEP 0x200 |
| 288 | #define NIU_TX_LPG_REG_SHIFT 9 /* log2(NIU_TX_LPG_REG_STEP) */ |
| 289 | #define NIU_TX_LPG_CH_N_REG 2 |
| 290 | |
| 291 | #define NIU_TX_LPG_SHIFT 12 |
| 292 | |
| 293 | |
| 294 | /* |
| 295 | * PIO "TXC" block registers region |
| 296 | */ |
| 297 | #define NIU_PIO_FZC_TXC_BASE (NIU_PIO_BASE + 0x780000) |
| 298 | |
| 299 | /* |
| 300 | * Transmit DMA port binding register |
| 301 | */ |
| 302 | #define NIU_TX_PORT_REG (NIU_PIO_FZC_TXC_BASE + 0x20028) |
| 303 | #define NIU_TX_PORT_REG_STEP 0x100 |
| 304 | #define NIU_TX_PORT0_REG (NIU_TX_PORT_REG) |
| 305 | #define NIU_TX_PORT1_REG (NIU_TX_PORT_REG + NIU_TX_PORT_REG_STEP) |
| 306 | |
| 307 | |
| 308 | /* |
| 309 | * PIO logical devices interrupt state vector and management region |
| 310 | * |
| 311 | * (Now why there are three mask regions is way beyond comprehension because it |
| 312 | * makes things so really ugly. Compounding this the register layouts aren't |
| 313 | * even consistent!) |
| 314 | */ |
| 315 | #define NIU_PIO_LDSV_BASE (NIU_PIO_BASE + 0x800000) |
| 316 | |
| 317 | /* |
| 318 | * Interrupt state vector 0 registers |
| 319 | */ |
| 320 | #define NIU_LDSV0_REG (NIU_PIO_LDSV_BASE + 0x0) |
| 321 | #define NIU_LDSV0_REG_STEP 0x2000 |
| 322 | #define NIU_LDSV0_REG_SHIFT 13 /* log2(NIU_PIO_LDSV0_REG_STEP) */ |
| 323 | |
| 324 | /* |
| 325 | * Interrupt state vector 1 registers |
| 326 | */ |
| 327 | #define NIU_LDSV1_REG (NIU_PIO_LDSV_BASE + 0x8) |
| 328 | #define NIU_LDSV1_REG_STEP 0x2000 |
| 329 | #define NIU_LDSV1_REG_SHIFT 13 /* log2(NIU_PIO_LDSV1_REG_STEP) */ |
| 330 | |
| 331 | /* |
| 332 | * Interrupt state vector 2 registers |
| 333 | */ |
| 334 | #define NIU_LDSV2_REG (NIU_PIO_LDSV_BASE + 0x10) |
| 335 | #define NIU_LDSV2_REG_STEP 0x2000 |
| 336 | #define NIU_LDSV2_REG_SHIFT 13 /* log2(NIU_PIO_LDSV2_REG_STEP) */ |
| 337 | |
| 338 | |
| 339 | /* |
| 340 | * PIO logical devices interrupt mask0 region |
| 341 | */ |
| 342 | #define NIU_PIO_IMASK0_BASE (NIU_PIO_BASE + 0xA00000) |
| 343 | |
| 344 | #define NIU_INTR_MASK0_REG (NIU_PIO_IMASK0_BASE + 0x0) |
| 345 | #define NIU_INTR_MASK0_REG_STEP 0x2000 |
| 346 | #define NIU_INTR_MASK0_REG_SHIFT 13 /* log2(NIU_INTR_MASK0_REG_STEP) */ |
| 347 | #define NIU_INTR_MASK0_N_REG 64 |
| 348 | |
| 349 | /* |
| 350 | * PIO logical devices interrupt mask1 region |
| 351 | * |
| 352 | * (Now why there are two mask regions is way beyond comprehension because it |
| 353 | * makes things so really ugly.) |
| 354 | */ |
| 355 | #define NIU_PIO_IMASK1_BASE (NIU_PIO_BASE + 0xB00000) |
| 356 | |
| 357 | #define NIU_INTR_MASK1_REG (NIU_PIO_IMASK1_BASE + 0x0) |
| 358 | #define NIU_INTR_MASK1_REG_STEP 0x2000 |
| 359 | #define NIU_INTR_MASK1_REG_SHIFT 13 /* log2(NIU_INTR_MASK1_REG_STEP) */ |
| 360 | #define NIU_INTR_MASK1_N_REG 5 |
| 361 | |
| 362 | |
| 363 | #define NIU_INTR_MASK_VALUE 0x3 /* normal datapath and error events */ |
| 364 | |
| 365 | #ifndef _ASM |
| 366 | |
| 367 | extern void niu_devino2vino(void); |
| 368 | extern void niu_mondo_receive(void); |
| 369 | extern void niu_intr_getvalid(void); |
| 370 | extern void niu_intr_setvalid(void); |
| 371 | extern void niu_intr_getstate(void); |
| 372 | extern void niu_intr_setstate(void); |
| 373 | extern void niu_intr_gettarget(void); |
| 374 | extern void niu_intr_settarget(void); |
| 375 | |
| 376 | struct niu_cookie { |
| 377 | uint64_t *ldg2ldn_table; |
| 378 | uint64_t *vec2ldg_table; |
| 379 | }; |
| 380 | |
| 381 | /* |
| 382 | * N.B. Keep the size of struct niu_mapreg a power of 2 so the offset |
| 383 | * can be computed via 'sllx' versus 'mulx'. |
| 384 | * Also pad the struct so each instance maps to a unique cacheline to |
| 385 | * avoid store buffer collisions. |
| 386 | */ |
| 387 | struct niu_mapreg { |
| 388 | uint32_t state; |
| 389 | uint32_t valid; |
| 390 | uint64_t vcpup; |
| 391 | uint64_t pad1; |
| 392 | uint64_t pad2; |
| 393 | uint64_t pad3; |
| 394 | uint64_t pad4; |
| 395 | uint64_t pad5; |
| 396 | uint64_t pad6; |
| 397 | }; |
| 398 | |
| 399 | struct niu_state { |
| 400 | struct niu_mapreg mapreg[NUM_VINTRS]; |
| 401 | }; |
| 402 | |
| 403 | extern void niu_init(void); |
| 404 | extern void niu_reset(void); |
| 405 | extern void xaui_reset(void); |
| 406 | |
| 407 | #endif /* !_ASM */ |
| 408 | |
| 409 | #define NIU_INO_RXDMA_BASE 0 |
| 410 | #define NIU_INO_TXDMA_BASE 16 |
| 411 | #define NIU_INO_MIF_BASE 32 |
| 412 | #define NIU_INO_MAC_BASE 33 |
| 413 | #define NIU_INO_ERR_BASE 35 |
| 414 | |
| 415 | /* |
| 416 | * XXX this should come from the MD, no? |
| 417 | */ |
| 418 | #define NIU_DEVINST 0x2 |
| 419 | |
| 420 | #ifdef __cplusplus |
| 421 | } |
| 422 | #endif |
| 423 | |
| 424 | #endif /* _NIAGARA2_NIU_H */ |