| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: fpga_uart.s |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #pragma ident "@(#)fpga_uart.s 1.2 07/06/13 SMI" |
| 50 | |
| 51 | #include <sys/htypes.h> |
| 52 | #include <sys/asm_linkage.h> |
| 53 | #include <asi.h> |
| 54 | #include <offsets.h> |
| 55 | #include <util.h> |
| 56 | #include <fpga.h> |
| 57 | #include <ldc.h> |
| 58 | #include <intr.h> |
| 59 | #include <vdev_ops.h> |
| 60 | #include <devices/pc16550.h> |
| 61 | |
| 62 | #if defined(CONFIG_FPGA) && defined(CONFIG_PIU) && defined(CONFIG_FPGA_UART) |
| 63 | |
| 64 | #define FPGA_INT(n) (1 << FPGA_INT_/**/n/**/_BIT) |
| 65 | #define UART_SYSINO ((PIU_AID << PIU_DEVINO_SHIFT) | 0x13) |
| 66 | |
| 67 | /* |
| 68 | * fpga_uart_intr_getvalid |
| 69 | * |
| 70 | * %g1 FPGA Uart Cookie Pointer |
| 71 | * arg0 Virtual INO (%o0) |
| 72 | * -- |
| 73 | * ret0 status (%o0) |
| 74 | * ret1 intr valid state (%o1) |
| 75 | */ |
| 76 | ENTRY_NP(fpga_uart_intr_getvalid) |
| 77 | !! %g1 pointer to FPGA_UART_COOKIE |
| 78 | ldub [%g1 + FPGA_UART_COOKIE_VALID], %o1 |
| 79 | HCALL_RET(EOK) |
| 80 | SET_SIZE(fpga_uart_intr_getvalid) |
| 81 | |
| 82 | /* |
| 83 | * fpga_uart_intr_setvalid |
| 84 | * |
| 85 | * %g1 FPGA Uart Cookie Pointer |
| 86 | * arg0 Virtual INO (%o0) |
| 87 | * arg1 intr valid state (%o1) 1: Valid 0: Invalid |
| 88 | * -- |
| 89 | * ret0 status (%o0) |
| 90 | */ |
| 91 | ENTRY_NP(fpga_uart_intr_setvalid) |
| 92 | !! %g1 pointer to FPGA_UART_COOKIE |
| 93 | cmp %o1, INTR_ENABLED |
| 94 | bgu,pn %xcc, herr_inval |
| 95 | mov FPGA_INT(UART), %g5 |
| 96 | stb %o1, [%g1 + FPGA_UART_COOKIE_VALID] ! save state |
| 97 | ldx [%g1 + FPGA_UART_COOKIE_ENABLE], %g3 |
| 98 | ldx [%g1 + FPGA_UART_COOKIE_DISABLE], %g4 |
| 99 | movrz %o1, %g4, %g6 |
| 100 | movrnz %o1, %g3, %g6 |
| 101 | stb %g5, [%g6] |
| 102 | HCALL_RET(EOK) |
| 103 | SET_SIZE(fpga_uart_intr_setvalid) |
| 104 | |
| 105 | /* |
| 106 | * fpga_uart_intr_getstate |
| 107 | * |
| 108 | * %g1 FPGA Uart Cookie Pointer |
| 109 | * arg0 Virtual INO (%o0) |
| 110 | * -- |
| 111 | * ret0 status (%o0) |
| 112 | * ret1 (%o1) 2: Delivered 1: Received 0: Idle |
| 113 | */ |
| 114 | ENTRY_NP(fpga_uart_intr_getstate) |
| 115 | !! %g1 pointer to FPGA_UART_COOKIE |
| 116 | ldub [%g1 + FPGA_UART_COOKIE_STATE], %o1 |
| 117 | HCALL_RET(EOK) |
| 118 | SET_SIZE(fpga_uart_intr_getstate) |
| 119 | |
| 120 | /* |
| 121 | * fpga_uart_intr_setstate |
| 122 | * |
| 123 | * %g1 FPGA Uart Cookie Pointer |
| 124 | * arg0 Virtual INO (%o0) |
| 125 | * arg1 (%o1) 2: Delivered, 1: Received, 0: Idle |
| 126 | * -- |
| 127 | * ret0 status (%o0) |
| 128 | */ |
| 129 | ENTRY_NP(fpga_uart_intr_setstate) |
| 130 | !! %g1 pointer to FPGA_UART_COOKIE |
| 131 | cmp %o1, INTR_DELIVERED |
| 132 | bgu,pn %xcc, herr_inval |
| 133 | mov FPGA_INT(UART), %g5 |
| 134 | stb %o1, [%g1 + FPGA_UART_COOKIE_STATE] ! save state |
| 135 | ldx [%g1 + FPGA_UART_COOKIE_ENABLE], %g3 |
| 136 | ldx [%g1 + FPGA_UART_COOKIE_DISABLE], %g4 |
| 137 | movrz %o1, %g3, %g6 |
| 138 | movrnz %o1, %g4, %g6 |
| 139 | stb %g5, [%g6] |
| 140 | HCALL_RET(EOK) |
| 141 | SET_SIZE(fpga_uart_intr_setstate) |
| 142 | |
| 143 | /* |
| 144 | * fpga_uart_intr_gettarget |
| 145 | * |
| 146 | * %g1 FPGA Uart Cookie Pointer |
| 147 | * arg0 Virtual INO (%o0) |
| 148 | * -- |
| 149 | * ret0 status (%o0) |
| 150 | * ret1 cpuid (%o1) |
| 151 | */ |
| 152 | ENTRY_NP(fpga_uart_intr_gettarget) |
| 153 | !! %g1 pointer to FPGA_UART_COOKIE |
| 154 | ldub [%g1 + FPGA_UART_COOKIE_TARGET], %g4 |
| 155 | !! %g4 = Physical CPU number |
| 156 | PID2VCPUP(%g4, %g3, %g5, %g6) |
| 157 | !! %g3 = CPU struct |
| 158 | ldub [%g3 + CPU_VID], %o1 |
| 159 | HCALL_RET(EOK) |
| 160 | SET_SIZE(fpga_uart_intr_gettarget) |
| 161 | |
| 162 | /* |
| 163 | * fpga_uart_intr_settarget |
| 164 | * |
| 165 | * %g1 FPGA Uart Cookie Pointer |
| 166 | * arg0 Virtual INO (%o0) |
| 167 | * arg1 cpuid (%o1) |
| 168 | * -- |
| 169 | * ret0 status (%o0) |
| 170 | */ |
| 171 | ENTRY_NP(fpga_uart_intr_settarget) |
| 172 | !! %g1 pointer to FPGA_UART_COOKIE |
| 173 | GUEST_STRUCT(%g2) |
| 174 | VCPUID2CPUP(%g2, %o1, %g3, herr_nocpu, %g6) |
| 175 | !! %g3 = target cpup |
| 176 | IS_CPU_IN_ERROR(%g3, %g6) |
| 177 | be,pn %xcc, herr_cpuerror |
| 178 | VCPU2STRAND_STRUCT(%g3, %g6) |
| 179 | ldub [%g6 + STRAND_ID], %g6 |
| 180 | !! %g6 = Physical Target CPU number |
| 181 | stb %g6, [%g1 + FPGA_UART_COOKIE_TARGET] |
| 182 | HCALL_RET(EOK) |
| 183 | SET_SIZE(fpga_uart_intr_settarget) |
| 184 | |
| 185 | |
| 186 | /* |
| 187 | * fpga_uart_mondo_receive |
| 188 | * |
| 189 | * Since the ssi interrupt is shared amoung many sources, a few tests must be made |
| 190 | * before it is determined that this mondo is to be sent. |
| 191 | * |
| 192 | * 1) test the pending bit for the uart, if set then |
| 193 | * 2) test the state for IDLE, if IDLE then |
| 194 | * 3) test the interrupt enable bit for the UART, if set then send mondo |
| 195 | * If any condition above fails, then return, this ssi int was not meant |
| 196 | * for a UART interrupt to be sent to the guest. |
| 197 | * |
| 198 | * %g1 - FPGA Uart Cookie Pointer |
| 199 | */ |
| 200 | ENTRY_NP(fpga_uart_mondo_receive) |
| 201 | !! %g1 pointer to FPGA_UART_COOKIE |
| 202 | mov FPGA_INT(UART), %g5 |
| 203 | ldx [%g1 + FPGA_UART_COOKIE_STATUS], %g3 |
| 204 | ldub [%g3], %g4 |
| 205 | !! %g4 = Pending FPGA interrupts |
| 206 | !! %g5 = UART interrupt bit |
| 207 | btst %g5, %g4 |
| 208 | bz %xcc, 1f ! is pending set? |
| 209 | ldub [%g1 + FPGA_UART_COOKIE_STATE], %g3 |
| 210 | cmp %g3, INTR_IDLE ! is state idle? |
| 211 | bne,pt %xcc, 1f |
| 212 | ldx [%g1 + FPGA_UART_COOKIE_ENABLE], %g3 |
| 213 | ldub [%g3], %g3 |
| 214 | btst %g5, %g3 ! is int enabled? |
| 215 | mov UART_SYSINO, %g2 |
| 216 | bnz %xcc, send_guest_uart_interrupt |
| 217 | nop |
| 218 | 1: HVRET |
| 219 | |
| 220 | send_guest_uart_interrupt: |
| 221 | !! Deliver interrupt locally if current cpu is the same as target. |
| 222 | !! %g1 pointer to FPGA_UART_COOKIE |
| 223 | ldx [%g1 + FPGA_UART_COOKIE_DISABLE], %g3 |
| 224 | stb %g5, [%g3] ! disable |
| 225 | |
| 226 | ldub [%g1 + FPGA_UART_COOKIE_VALID], %g6 |
| 227 | mov INTR_RECEIVED, %g3 |
| 228 | movrnz %g6, INTR_DELIVERED, %g3 |
| 229 | stb %g3, [%g1 + FPGA_UART_COOKIE_STATE] ! update state |
| 230 | brz %g6, 3f |
| 231 | nop |
| 232 | |
| 233 | mov %g1, %g4 |
| 234 | ldub [%g4 + FPGA_UART_COOKIE_TARGET], %g1 |
| 235 | PID2VCPUP(%g1, %g5, %g6, %g3) |
| 236 | mov %g5, %g1 ! %g1 = vcpup |
| 237 | mov %g2, %g3 ! %g3 = mondo |
| 238 | mov 1, %g2 ! %g2 = flag, 1 = mondo |
| 239 | ba,a send_dev_mondo |
| 240 | nop |
| 241 | |
| 242 | 3: HVRET |
| 243 | SET_SIZE(fpga_uart_mondo_receive) |
| 244 | |
| 245 | /* |
| 246 | * fpga_uart_intr_redistribute |
| 247 | * |
| 248 | * %g1 this strand |
| 249 | * %g2 target strand |
| 250 | */ |
| 251 | ENTRY_NP(fpga_uart_intr_redistribute) |
| 252 | !! |
| 253 | mov DEVOPS_FPGA, %g3 |
| 254 | GUEST_STRUCT(%g4) |
| 255 | DEVINST2COOKIE(%g4, %g3, %g3, %g5, uart_fail) |
| 256 | ldub [%g3 + FPGA_UART_COOKIE_TARGET], %g4 |
| 257 | cmp %g1, %g4 |
| 258 | be,pt %xcc, 1f |
| 259 | nop |
| 260 | HVRET |
| 261 | 1: |
| 262 | stb %g2, [%g3 + FPGA_UART_COOKIE_TARGET] |
| 263 | HVRET |
| 264 | SET_SIZE(fpga_uart_intr_redistribute) |
| 265 | |
| 266 | ! When DEBUG is defined badtrap is too far away for |
| 267 | ! "DEVINST2COOKIE()", branch here instead |
| 268 | uart_fail: |
| 269 | nop |
| 270 | ba,a badtrap |
| 271 | |
| 272 | #endif /* CONFIG_FPGA && CONFIG_PIU && CONFIG_FPGA_UART */ |