| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: config.c |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #pragma ident "@(#)config.c 1.4 07/08/01 SMI" |
| 50 | |
| 51 | /* |
| 52 | * Guest configuration |
| 53 | */ |
| 54 | |
| 55 | #include <sys/htypes.h> |
| 56 | #include <hprivregs.h> |
| 57 | #include <hypervisor.h> |
| 58 | #include <traps.h> |
| 59 | #include <cache.h> |
| 60 | #include <mmu.h> |
| 61 | #include <vpiu_errs_defs.h> |
| 62 | #include <vdev_ops.h> |
| 63 | #include <vdev_intr.h> |
| 64 | #include <ncs.h> |
| 65 | #include <rng.h> |
| 66 | #include <cyclic.h> |
| 67 | #include <vcpu.h> |
| 68 | #include <strand.h> |
| 69 | #include <guest.h> |
| 70 | #include <vdev_ops.h> |
| 71 | #include <pcie.h> |
| 72 | #ifdef STANDALONE_NET_DEVICES |
| 73 | #include <network.h> |
| 74 | #endif |
| 75 | #include <memory.h> |
| 76 | #include <fpga.h> |
| 77 | |
| 78 | #define DEVOPS(n) DEVOPS_##n |
| 79 | |
| 80 | #define _VINO_HANDLER(n) \ |
| 81 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 82 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 83 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 84 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 85 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 86 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 87 | (n), (n), (n), (n), (n), (n), (n), (n), \ |
| 88 | (n), (n), (n), (n), (n), (n), (n), (n) |
| 89 | |
| 90 | #define VINO_HANDLER(n) _VINO_HANDLER(DEVOPS_##n) |
| 91 | |
| 92 | extern void vdev_devino2vino(void); |
| 93 | extern void vdev_intr_getvalid(void); |
| 94 | extern void vdev_intr_setvalid(void); |
| 95 | extern void vdev_intr_settarget(void); |
| 96 | extern void vdev_intr_gettarget(void); |
| 97 | extern void vdev_intr_getstate(void); |
| 98 | extern void vdev_intr_setstate(void); |
| 99 | |
| 100 | extern void ldc_vintr_getcookie(void); |
| 101 | extern void ldc_vintr_setcookie(void); |
| 102 | extern void ldc_vintr_getvalid(void); |
| 103 | extern void ldc_vintr_setvalid(void); |
| 104 | extern void ldc_vintr_gettarget(void); |
| 105 | extern void ldc_vintr_settarget(void); |
| 106 | extern void ldc_vintr_getstate(void); |
| 107 | extern void ldc_vintr_setstate(void); |
| 108 | |
| 109 | #if defined(CONFIG_PIU) |
| 110 | |
| 111 | extern const uint64_t piu_iotsb0; |
| 112 | extern const uint64_t piu_iotsb1; |
| 113 | extern const uint64_t piu_0_equeue; |
| 114 | extern const uint64_t piu_virtual_intmap; |
| 115 | |
| 116 | #define PIU_EQ(chip, eq) \ |
| 117 | .base = (uint64_t *)&piu_##chip##_equeue+(eq*0x400), \ |
| 118 | .eqmask = PIU_EQMASK |
| 119 | |
| 120 | #define PIU_MSI_COOKIE_SETUP(chip) \ |
| 121 | { \ |
| 122 | .piu = PIU_DEV_COOKIE(0), \ |
| 123 | .eq = { \ |
| 124 | { PIU_EQ(chip, 0) }, { PIU_EQ(chip, 1) }, \ |
| 125 | { PIU_EQ(chip, 2) }, { PIU_EQ(chip, 3) }, \ |
| 126 | { PIU_EQ(chip, 4) }, { PIU_EQ(chip, 5) }, \ |
| 127 | { PIU_EQ(chip, 6) }, { PIU_EQ(chip, 7) }, \ |
| 128 | { PIU_EQ(chip, 8) }, { PIU_EQ(chip, 9) }, \ |
| 129 | { PIU_EQ(chip, 10) }, { PIU_EQ(chip, 11) }, \ |
| 130 | { PIU_EQ(chip, 12) }, { PIU_EQ(chip, 13) }, \ |
| 131 | { PIU_EQ(chip, 14) }, { PIU_EQ(chip, 15) }, \ |
| 132 | { PIU_EQ(chip, 16) }, { PIU_EQ(chip, 17) }, \ |
| 133 | { PIU_EQ(chip, 18) }, { PIU_EQ(chip, 19) }, \ |
| 134 | { PIU_EQ(chip, 20) }, { PIU_EQ(chip, 21) }, \ |
| 135 | { PIU_EQ(chip, 22) }, { PIU_EQ(chip, 23) }, \ |
| 136 | { PIU_EQ(chip, 24) }, { PIU_EQ(chip, 25) }, \ |
| 137 | { PIU_EQ(chip, 26) }, { PIU_EQ(chip, 27) }, \ |
| 138 | { PIU_EQ(chip, 28) }, { PIU_EQ(chip, 29) }, \ |
| 139 | { PIU_EQ(chip, 30) }, { PIU_EQ(chip, 31) }, \ |
| 140 | { PIU_EQ(chip, 32) }, { PIU_EQ(chip, 33) }, \ |
| 141 | { PIU_EQ(chip, 34) }, { PIU_EQ(chip, 35) }, \ |
| 142 | } \ |
| 143 | }, |
| 144 | |
| 145 | const struct piu_msi_cookie piu_msi[NPIUS] = { |
| 146 | PIU_MSI_COOKIE_SETUP(0) |
| 147 | }; |
| 148 | |
| 149 | #define PIU_ERR_COOKIE_SETUP(chip) \ |
| 150 | { .piu = PIU_DEV_COOKIE(chip), } |
| 151 | |
| 152 | const struct piu_err_cookie piu_err[NPIUS] = { |
| 153 | PIU_ERR_COOKIE_SETUP(0) |
| 154 | }; |
| 155 | |
| 156 | #define PIU_COOKIE_SETUP(chip) \ |
| 157 | { \ |
| 158 | /* PIU(chip) */ \ |
| 159 | .inomax = NPIUDEVINO, \ |
| 160 | .vino = AID2VINO(chip), \ |
| 161 | .handle = AID2HANDLE(chip), \ |
| 162 | .ncu = AID2JBUS(chip), \ |
| 163 | .intclr = AID2INTCLR(chip), \ |
| 164 | .intmap = AID2INTMAP(chip), \ |
| 165 | .virtual_intmap = (void *)&piu_virtual_intmap, \ |
| 166 | .mmu = AID2MMU(chip), \ |
| 167 | .mmuflush = AID2MMUFLUSH(chip), \ |
| 168 | .pcie = AID2PCIE(chip), \ |
| 169 | .cfg = AID2PCIECFG(chip), \ |
| 170 | .eqctlset = AID2PCIE(chip)|PIU_DLC_IMU_EQS_EQ_CTRL_SET(0),\ |
| 171 | .eqctlclr = AID2PCIE(chip)|PIU_DLC_IMU_EQS_EQ_CTRL_CLR(0),\ |
| 172 | .eqstate = AID2PCIE(chip)|PIU_DLC_IMU_EQS_EQ_STATE(0), \ |
| 173 | .eqtail = AID2PCIE(chip)|PIU_DLC_IMU_EQS_EQ_TAIL(0), \ |
| 174 | .eqhead = AID2PCIE(chip)|PIU_DLC_IMU_EQS_EQ_HEAD(0), \ |
| 175 | .msimap = AID2PCIE(chip)|PIU_DLC_IMU_RDS_MSI_MSI_MAPPING(0),\ |
| 176 | .msiclr = AID2PCIE(chip)|PIU_DLC_IMU_RDS_MSI_MSI_CLEAR_REG(0),\ |
| 177 | .msgmap = AID2PCIE(chip)|PIU_DLC_IMU_RDS_MESS_ERR_COR_MAPPING,\ |
| 178 | .msieqbase = (void *)&piu_##chip##_equeue, /* RELOC */ \ |
| 179 | .iotsb0 = (void *)&piu_iotsb0, /* RELOC */ \ |
| 180 | .iotsb1 = (void *)&piu_iotsb1, /* RELOC */ \ |
| 181 | .msicookie = PIU_MSI_COOKIE(chip), /* RELOC */ \ |
| 182 | .errcookie = PIU_ERR_COOKIE(chip), /* RELOC */ \ |
| 183 | .perfregs = PIU_PERF_REGS(chip), \ |
| 184 | } |
| 185 | |
| 186 | const piu_dev_t piu_dev[NPIUS] = { |
| 187 | PIU_COOKIE_SETUP(0) |
| 188 | }; |
| 189 | |
| 190 | #else /* !CONFIG_PIU */ |
| 191 | |
| 192 | #define VINO_HANDLER_PIU(n) VINO_HANDLER(RESERVED) |
| 193 | |
| 194 | #endif /* !CONFIG_PIU */ |
| 195 | |
| 196 | extern const uint64_t niu_ldg2ldn_table; |
| 197 | extern const uint64_t niu_vec2ldg_table; |
| 198 | |
| 199 | const struct niu_cookie niu_dev = { |
| 200 | .ldg2ldn_table = (void *)&niu_ldg2ldn_table, |
| 201 | .vec2ldg_table = (void *)&niu_vec2ldg_table |
| 202 | }; |
| 203 | |
| 204 | #ifdef CONFIG_FPGA_UART |
| 205 | |
| 206 | const struct fpga_cookie fpga_uart_dev = { |
| 207 | .status = FPGA_INTR_BASE + FPGA_OTHER_INTR_STATUS, |
| 208 | .enable = FPGA_INTR_BASE + FPGA_OTHER_INTR_ENABLE, |
| 209 | .disable = FPGA_INTR_BASE + FPGA_OTHER_INTR_DISABLE |
| 210 | }; |
| 211 | |
| 212 | #endif /* CONFIG_FPGA_UART */ |
| 213 | |
| 214 | struct config config; |
| 215 | |
| 216 | #ifdef CONFIG_CRYPTO |
| 217 | struct mau maus[NMAUS]; |
| 218 | struct cwq cwqs[NCWQS]; |
| 219 | struct rng rng; |
| 220 | #endif /* CONFIG_CRYPTO */ |
| 221 | |
| 222 | vcpu_t vcpus[NVCPUS]; |
| 223 | strand_t strands[NSTRANDS]; |
| 224 | mblock_t mblocks[NMBLOCKS]; |
| 225 | |
| 226 | #ifdef CONFIG_PIU |
| 227 | pcie_device_t pcie_bus[NUM_PCIE_BUSSES]; |
| 228 | #endif |
| 229 | |
| 230 | #ifdef STANDALONE_NET_DEVICES |
| 231 | network_device_t network_device[NUM_NETWORK_DEVICES]; |
| 232 | #endif |
| 233 | |
| 234 | struct guest guests[NGUESTS]; |
| 235 | |
| 236 | uint8_t hcall_tables[NGUESTS * HCALL_TABLE_SIZE + L2_LINE_SIZE-1]; |
| 237 | struct ldc_endpoint hv_ldcs[MAX_HV_LDC_CHANNELS]; |
| 238 | struct sp_ldc_endpoint sp_ldcs[MAX_SP_LDC_CHANNELS]; |
| 239 | |
| 240 | /* BEGIN CSTYLED */ |
| 241 | #pragma align 64 (cons_queues) |
| 242 | struct guest_console_queues cons_queues[NGUESTS]; |
| 243 | /* END CSTYLED */ |
| 244 | |
| 245 | struct devopsvec piu_dev_ops = { PIU_DEV_OPS }; |
| 246 | struct devopsvec piu_int_ops = { PIU_INT_OPS }; |
| 247 | struct devopsvec piu_msi_ops = { PIU_MSI_OPS }; |
| 248 | struct devopsvec piu_err_int_ops = { PIU_ERR_OPS }; |
| 249 | |
| 250 | struct devopsvec vdev_ops = { VDEV_OPS }; |
| 251 | |
| 252 | struct devopsvec cdev_ops = { CDEV_OPS }; |
| 253 | |
| 254 | struct devopsvec niu_ops = { NIU_OPS }; |
| 255 | |
| 256 | #ifdef CONFIG_FPGA_UART |
| 257 | struct devopsvec fpga_uart_ops = { FPGA_UART_OPS }; |
| 258 | #endif /* CONFIG_FPGA_UART */ |
| 259 | |
| 260 | /* |
| 261 | * vino2inst and dev2inst arrays contain indexes |
| 262 | * into this struct devinst. |
| 263 | * |
| 264 | * vino2inst array is used to go from vINO => inst |
| 265 | * |
| 266 | * dev2inst array is used to go from devID => inst |
| 267 | */ |
| 268 | struct devinst devinstances[NDEV_INSTS] = { |
| 269 | { 0, 0 }, |
| 270 | { .cookie = PIU_DEV_COOKIE(0), .ops = &piu_dev_ops }, |
| 271 | |
| 272 | { .cookie = PIU_DEV_COOKIE(0), .ops = &piu_int_ops }, |
| 273 | |
| 274 | { .cookie = PIU_DEV_COOKIE(0), .ops = &piu_msi_ops }, |
| 275 | |
| 276 | { .cookie = PIU_DEV_COOKIE(0), .ops = &piu_err_int_ops }, |
| 277 | |
| 278 | { .cookie = NIU_COOKIE, .ops = &niu_ops }, |
| 279 | |
| 280 | { .cookie = 0, .ops = &vdev_ops }, |
| 281 | |
| 282 | { .cookie = 0, .ops = &cdev_ops }, |
| 283 | |
| 284 | #ifdef CONFIG_FPGA_UART |
| 285 | |
| 286 | { .cookie = FPGA_UART_COOKIE, .ops = &fpga_uart_ops }, |
| 287 | |
| 288 | #endif /* CONFIG_FPGA_UART */ |
| 289 | |
| 290 | { 0, 0 }, |
| 291 | |
| 292 | }; |
| 293 | |
| 294 | const struct vino_pcie config_pcie_vinos = { |
| 295 | VINO_HANDLER_PIU(A), |
| 296 | }; |