projects / vvhitespace / blame
| Commit | Line | Data |
|---|---|---|
| 24e4f91b AT |
1 | @ All zeros to all ones |
| 2 | SSSSN | PUSH 0 | |
| 3 | NSTTSTSSSN | JSR > 101000 (not) | |
| 4fba07dc | 4 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 24e4f91b AT |
5 | |
| 6 | @ All ones to all zeros | |
| 7 | SSTTN | PUSH -1 | |
| 8 | NSTTSTSSSN | JSR > 101000 (not) | |
| 4fba07dc | 9 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 24e4f91b AT |
10 | |
| 11 | @ Test alternating bits, leading zero. | |
| 12 | @ Note that 6148914691236517205 = 0101...0101 | |
| 13 | SSSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTN | PUSH +6148914691236517205 | |
| 14 | NSTTSTSSSN | JSR > 101000 (not) | |
| 4fba07dc | 15 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 24e4f91b AT |
16 | |
| 17 | @ Test alternating bits, leading one. | |
| 18 | @ Note that -6148914691236517206 = 1010...1010 in twos-complement but we | |
| 19 | @ enter it in sign magnitude format so the bit pattern appears different. | |
| 20 | SSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTTSN | PUSH -6148914691236517206 | |
| 21 | NSTTSTSSSN | JSR > 101000 (not) | |
| 4fba07dc | 22 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 24e4f91b AT |
23 | |
| 24 | @ All done. | |
| 25 | NNN | DIE | |
| 26 | ||
| 27 | #include <logic.pvvs> | |
| 4fba07dc | 28 | #include <debug.pvvs> |