stdlib_tests/3005_or.pvvs

@ Test 0 v 0 = 0
SSSSN           | PUSH 0
SSSSN           | PUSH 0
NSTTSTSTSN      | JSR > 101010 (or)
NSTTTTTSTN      | JSR > 111101 (debug:printsignednumber)

@ Test 0 v 1 = 1
SSSSN           | PUSH 0
SSSTN           | PUSH +1
NSTTSTSTSN      | JSR > 101010 (or)
NSTTTTTSTN      | JSR > 111101 (debug:printsignednumber)

@ Test 1 v 1 = 1
SSSTN           | PUSH +1
SSSTN           | PUSH +1
NSTTSTSTSN      | JSR > 101010 (or)
NSTTTTTSTN      | JSR > 111101 (debug:printsignednumber)

@ Test 1 v 1...1 = 1...1
SSSTN           | PUSH +1
SSTTN           | PUSH -1
NSTTSTSTSN      | JSR > 101010 (or)
NSTTTTTSTN      | JSR > 111101 (debug:printsignednumber)

@ Test 1010...1010 v 0101...0101 = 1...1
@ Note that -6148914691236517206 = 1010...1010 in twos-complement but we
@ enter it in sign magnitude format so the bit pattern appears different.
SSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTTSN | PUSH -6148914691236517206
SSSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTN  | PUSH +6148914691236517205
NSTTSTSTSN      | JSR > 101010 (or)
NSTTTTTSTN      | JSR > 111101 (debug:printsignednumber)

@ All done.
NNN             | DIE

#include <logic.pvvs>
#include <debug.pvvs>