// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: dmc_rxc_drv_ports.vri // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ #include "rxc_defines.vri" #define RXC_CK_IN_TIMING PSAMPLE #-1 #define RXC_CK_OUT_TIMING PHOLD #0 #define RXC_CK_CLK_TIMING CLOCK interface dmc_rxc_port0_if{ input [129:0] rxc_dmc_pkt_data RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_data0"; input rxc_dmc_ful_pkt RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_ful_pkt0"; input rxc_dmc_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_emp0"; input rxc_dmc_err RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_err0"; input rxc_dmc_ack RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_ack0"; output dmc_rxc_req RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_ipp_dat_req0"; input clk RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; } interface dmc_rxc_port1_if{ input [129:0] rxc_dmc_pkt_data RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_data1"; input rxc_dmc_ful_pkt RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_ful_pkt1"; input rxc_dmc_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_emp1"; input rxc_dmc_err RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_err1"; input rxc_dmc_ack RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.ipp_dmc_dat_ack1"; output dmc_rxc_req RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_ipp_dat_req1"; input clk RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; } port dmc_rxc_drv_port{ rxc_dmc_pkt_data; rxc_dmc_ful_pkt; rxc_dmc_empty; rxc_dmc_err; rxc_dmc_ack; dmc_rxc_req; clk; } bind dmc_rxc_drv_port dmc_rxc_drv0{ rxc_dmc_pkt_data dmc_rxc_port0_if.rxc_dmc_pkt_data; rxc_dmc_ful_pkt dmc_rxc_port0_if.rxc_dmc_ful_pkt; rxc_dmc_empty dmc_rxc_port0_if.rxc_dmc_empty; rxc_dmc_err dmc_rxc_port0_if.rxc_dmc_err; rxc_dmc_ack dmc_rxc_port0_if.rxc_dmc_ack; dmc_rxc_req dmc_rxc_port0_if.dmc_rxc_req; clk dmc_rxc_port0_if.clk; } bind dmc_rxc_drv_port dmc_rxc_drv1{ rxc_dmc_pkt_data dmc_rxc_port1_if.rxc_dmc_pkt_data; rxc_dmc_ful_pkt dmc_rxc_port1_if.rxc_dmc_ful_pkt; rxc_dmc_empty dmc_rxc_port1_if.rxc_dmc_empty; rxc_dmc_err dmc_rxc_port1_if.rxc_dmc_err; rxc_dmc_ack dmc_rxc_port1_if.rxc_dmc_ack; dmc_rxc_req dmc_rxc_port1_if.dmc_rxc_req; clk dmc_rxc_port0_if.clk; }