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// 
// OpenSPARC T2 Processor File: fc_inc.flist
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/////////////////////////////////////////////////////////////////////////
//
// Testbench Include Files for fc Bench
// these defines must be incluced before compiling any of the RTL
// otherwise 0-in or dispmon will report undefined macros
//
/////////////////////////////////////////////////////////////////////////

$DV_ROOT/verif/env/common/verilog/misc/defines.vh
+incdir++
+incdir+../common/verilog/checkers+
+incdir+../common/coverage+
+incdir+../../../design/sys/iop/cpu/rtl+
+incdir+../../../verif/env/tcu+

//-----------------------------------------------------------------------
// DMU (ILU) defines.
//-----------------------------------------------------------------------
$DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h