X-Git-Url: https://git.subgeniuskitty.com/unix-history/.git/blobdiff_plain/88a7e859201a547c4795f23cd4aef10b3927485f..5ff7c8570ab09cdf05bd09944407e0996e2fe218:/usr/src/sys/hp300/include/cpu.h diff --git a/usr/src/sys/hp300/include/cpu.h b/usr/src/sys/hp300/include/cpu.h index 0b4ad5f51e..ca37b2b6bb 100644 --- a/usr/src/sys/hp300/include/cpu.h +++ b/usr/src/sys/hp300/include/cpu.h @@ -1,7 +1,7 @@ /* * Copyright (c) 1988 University of Utah. - * Copyright (c) 1982, 1990 The Regents of the University of California. - * All rights reserved. + * Copyright (c) 1982, 1990, 1993 + * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * the Systems Programming Group of the University of Utah Computer @@ -9,38 +9,134 @@ * * %sccs.include.redist.c% * - * from: Utah $Hdr: cpu.h 1.13 89/06/23$ + * from: Utah $Hdr: cpu.h 1.16 91/03/25$ * - * @(#)cpu.h 7.1 (Berkeley) %G% + * @(#)cpu.h 8.3 (Berkeley) %G% + */ + +/* + * Exported definitions unique to hp300/68k cpu support. + */ + +/* + * definitions of cpu-dependent requirements + * referenced in generic code + */ +#define COPY_SIGCODE /* copy sigcode above user stack in exec */ + +#define cpu_exec(p) /* nothing */ +#define cpu_wait(p) /* nothing */ +#define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap +#define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp + +/* + * Arguments to hardclock and gatherstats encapsulate the previous + * machine state in an opaque clockframe. One the hp300, we use + * what the hardware pushes on an interrupt (frame format 0). + */ +struct clockframe { + u_short sr; /* sr at time of interrupt */ + u_long pc; /* pc at time of interrupt */ + u_short vo; /* vector offset (4-word frame) */ +}; + +#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) +#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) +#define CLKF_PC(framep) ((framep)->pc) +#if 0 +/* We would like to do it this way... */ +#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) +#else +/* but until we start using PSL_M, we have to do this instead */ +#define CLKF_INTR(framep) (0) /* XXX */ +#endif + + +/* + * Preempt the current process if in interrupt from user mode, + * or after the current trap/syscall if in system mode. + */ +#define need_resched() { want_resched++; aston(); } + +/* + * Give a profiling tick to the current process when the user profiling + * buffer pages are invalid. On the hp300, request an ast to send us + * through trap, marking the proc as needing a profiling tick. + */ +#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } + +/* + * Notify the current process (p) that it has a signal pending, + * process as soon as possible. + */ +#define signotify(p) aston() + +#define aston() (astpending++) + +int astpending; /* need to trap before returning to user mode */ +int want_resched; /* resched() was called */ + + +/* + * simulated software interrupt register + */ +extern unsigned char ssir; + +#define SIR_NET 0x1 +#define SIR_CLOCK 0x2 + +#define siroff(x) ssir &= ~(x) +#define setsoftnet() ssir |= SIR_NET +#define setsoftclock() ssir |= SIR_CLOCK + +/* + * CTL_MACHDEP definitions. + */ +#define CPU_CONSDEV 1 /* dev_t: console terminal device */ +#define CPU_MAXID 2 /* number of valid machdep ids */ + +#define CTL_MACHDEP_NAMES { \ + { 0, 0 }, \ + { "console_device", CTLTYPE_STRUCT }, \ +} + +/* + * The rest of this should probably be moved to ../hp300/hp300cpu.h, + * although some of it could probably be put into generic 68k headers. */ /* values for machineid */ -#define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ -#define HP_330 1 /* 16Mhz 68020+68851 MMU */ -#define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ -#define HP_360 3 /* 25Mhz 68030 */ -#define HP_370 4 /* 33Mhz 68030+64K external cache */ -#define HP_340 5 /* 16Mhz 68030 */ +#define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ +#define HP_330 1 /* 16Mhz 68020+68851 MMU */ +#define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ +#define HP_360 3 /* 25Mhz 68030 */ +#define HP_370 4 /* 33Mhz 68030+64K external cache */ +#define HP_340 5 /* 16Mhz 68030 */ +#define HP_375 6 /* 50Mhz 68030+32K external cache */ +#define HP_380 7 /* 25Mhz 68040 */ +#define HP_433 8 /* 33Mhz 68040 */ /* values for mmutype (assigned for quick testing) */ -#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ -#define MMU_HP 0 /* HP proprietary */ -#define MMU_68851 1 /* Motorola 68851 */ +#define MMU_68040 -2 /* 68040 on-chip MMU */ +#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ +#define MMU_HP 0 /* HP proprietary */ +#define MMU_68851 1 /* Motorola 68851 */ /* values for ectype */ -#define EC_PHYS -1 /* external physical address cache */ -#define EC_NONE 0 /* no external cache */ -#define EC_VIRT 1 /* external virtual address cache */ +#define EC_PHYS -1 /* external physical address cache */ +#define EC_NONE 0 /* no external cache */ +#define EC_VIRT 1 /* external virtual address cache */ /* values for cpuspeed (not really related to clock speed due to caches) */ -#define MHZ_8 1 -#define MHZ_16 2 -#define MHZ_25 3 -#define MHZ_33 4 +#define MHZ_8 1 +#define MHZ_16 2 +#define MHZ_25 3 +#define MHZ_33 4 +#define MHZ_50 6 #ifdef KERNEL extern int machineid, mmutype, ectype; -extern int IObase; +extern char *intiobase, *intiolimit; /* what is this supposed to do? i.e. how is it different than startrtclock? */ #define enablertclock() @@ -48,76 +144,135 @@ extern int IObase; #endif /* physical memory sections */ -#define ROMBASE (0x00000000) -#define IOBASE (0x00200000) -#define IOTOP (0x01000000) -#define MAXADDR (0xFFFFF000) - -/* IO space stuff */ -#define EXTIOBASE (0x00600000) -#define IOCARDSIZE (0x10000) -#define IOMAPSIZE (btoc(IOTOP-IOBASE)) -#define IOP(x) ((x) - IOBASE) -#define IOV(x) (((x) - IOBASE) + (int)&IObase) -#define UNIOV(x) ((x) - (int)&IObase + IOBASE) - -/* DIO II uncached address space */ -#define DIOIIBASE (0x01000000) -#define DIOIITOP (0x20000000) -#define DIOIICSIZE (0x00400000) - -/* offsets for longword read/write */ -#define MMUSSTP IOP(0x5F4000) -#define MMUUSTP IOP(0x5F4004) -#define MMUTBINVAL IOP(0x5F4008) -#define MMUSTAT IOP(0x5F400C) +#define ROMBASE (0x00000000) +#define INTIOBASE (0x00400000) +#define INTIOTOP (0x00600000) +#define EXTIOBASE (0x00600000) +#define EXTIOTOP (0x20000000) +#define MAXADDR (0xFFFFF000) + +/* + * Internal IO space: + * + * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). + * + * Internal IO space is mapped in the kernel from ``intiobase'' to + * ``intiolimit'' (defined in locore.s). Since it is always mapped, + * conversion between physical and kernel virtual addresses is easy. + */ +#define ISIIOVA(va) \ + ((char *)(va) >= intiobase && (char *)(va) < intiolimit) +#define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) +#define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) +#define IIOPOFF(pa) ((int)(pa)-INTIOBASE) +#define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ + +/* + * External IO space: + * + * DIO ranges from select codes 0-63 at physical addresses given by: + * 0x600000 + (sc - 32) * 0x10000 + * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for + * their control space and the remaining areas, [0x200000-0x400000) and + * [0x800000-0x1000000), are for additional space required by a card; + * e.g. a display framebuffer. + * + * DIO-II ranges from select codes 132-255 at physical addresses given by: + * 0x1000000 + (sc - 132) * 0x400000 + * The address range of DIO-II space is thus [0x1000000-0x20000000). + * + * DIO/DIO-II space is too large to map in its entirety, instead devices + * are mapped into kernel virtual address space allocated from a range + * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. + */ +#define DIOBASE (0x600000) +#define DIOTOP (0x1000000) +#define DIOCSIZE (0x10000) +#define DIOIIBASE (0x01000000) +#define DIOIITOP (0x20000000) +#define DIOIICSIZE (0x00400000) + +/* + * HP MMU + */ +#define MMUBASE IIOPOFF(0x5F4000) +#define MMUSSTP 0x0 +#define MMUUSTP 0x4 +#define MMUTBINVAL 0x8 +#define MMUSTAT 0xC #define MMUCMD MMUSTAT -#define MMU_UMEN 0x0001 /* enable user mapping */ -#define MMU_SMEN 0x0002 /* enable supervisor mapping */ -#define MMU_CEN 0x0004 /* enable data cache */ -#define MMU_BERR 0x0008 /* bus error */ -#define MMU_IEN 0x0020 /* enable instruction cache */ -#define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ -#define MMU_WPF 0x2000 /* write protect fault */ -#define MMU_PF 0x4000 /* page fault */ -#define MMU_PTF 0x8000 /* page table fault */ - -#define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) -#define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) - -#define PMMU_LVLMASK 0x0007 -#define PMMU_INV 0x0400 -#define PMMU_WP 0x0800 -#define PMMU_ALV 0x1000 -#define PMMU_SO 0x2000 -#define PMMU_LV 0x4000 -#define PMMU_BE 0x8000 - -#define PMMU_FAULT (PMMU_WP|PMMU_INV) - -/* function code for user data space */ -#define FC_USERD 1 -/* methinks the following is used to selectively clear TLB entries */ -#define FC_PURGE 3 +#define MMU_UMEN 0x0001 /* enable user mapping */ +#define MMU_SMEN 0x0002 /* enable supervisor mapping */ +#define MMU_CEN 0x0004 /* enable data cache */ +#define MMU_BERR 0x0008 /* bus error */ +#define MMU_IEN 0x0020 /* enable instruction cache */ +#define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ +#define MMU_WPF 0x2000 /* write protect fault */ +#define MMU_PF 0x4000 /* page fault */ +#define MMU_PTF 0x8000 /* page table fault */ + +#define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) +#define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) + +/* + * 68851 and 68030 MMU + */ +#define PMMU_LVLMASK 0x0007 +#define PMMU_INV 0x0400 +#define PMMU_WP 0x0800 +#define PMMU_ALV 0x1000 +#define PMMU_SO 0x2000 +#define PMMU_LV 0x4000 +#define PMMU_BE 0x8000 +#define PMMU_FAULT (PMMU_WP|PMMU_INV) + +/* + * 68040 MMU + */ +#define MMU4_RES 0x001 +#define MMU4_TTR 0x002 +#define MMU4_WP 0x004 +#define MMU4_MOD 0x010 +#define MMU4_CMMASK 0x060 +#define MMU4_SUP 0x080 +#define MMU4_U0 0x100 +#define MMU4_U1 0x200 +#define MMU4_GLB 0x400 +#define MMU4_BE 0x800 + +/* 680X0 function codes */ +#define FC_USERD 1 /* user data space */ +#define FC_USERP 2 /* user program space */ +#define FC_PURGE 3 /* HPMMU: clear TLB entries */ +#define FC_SUPERD 5 /* supervisor data space */ +#define FC_SUPERP 6 /* supervisor program space */ +#define FC_CPU 7 /* CPU space */ /* fields in the 68020 cache control register */ -#define IC_ENABLE 0x0001 /* enable instruction cache */ -#define IC_FREEZE 0x0002 /* freeze instruction cache */ -#define IC_CE 0x0004 /* clear instruction cache entry */ -#define IC_CLR 0x0008 /* clear entire instruction cache */ +#define IC_ENABLE 0x0001 /* enable instruction cache */ +#define IC_FREEZE 0x0002 /* freeze instruction cache */ +#define IC_CE 0x0004 /* clear instruction cache entry */ +#define IC_CLR 0x0008 /* clear entire instruction cache */ /* additional fields in the 68030 cache control register */ -#define IC_BE 0x0010 /* instruction burst enable */ -#define DC_ENABLE 0x0100 /* data cache enable */ -#define DC_FREEZE 0x0200 /* data cache freeze */ -#define DC_CE 0x0400 /* clear data cache entry */ -#define DC_CLR 0x0800 /* clear entire data cache */ -#define DC_BE 0x1000 /* data burst enable */ -#define DC_WA 0x2000 /* write allocate */ - -#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) -#define CACHE_OFF (DC_CLR|IC_CLR) -#define CACHE_CLR (CACHE_ON) -#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) -#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) +#define IC_BE 0x0010 /* instruction burst enable */ +#define DC_ENABLE 0x0100 /* data cache enable */ +#define DC_FREEZE 0x0200 /* data cache freeze */ +#define DC_CE 0x0400 /* clear data cache entry */ +#define DC_CLR 0x0800 /* clear entire data cache */ +#define DC_BE 0x1000 /* data burst enable */ +#define DC_WA 0x2000 /* write allocate */ + +#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) +#define CACHE_OFF (DC_CLR|IC_CLR) +#define CACHE_CLR (CACHE_ON) +#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) +#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) + +/* 68040 cache control register */ +#define IC4_ENABLE 0x8000 /* instruction cache enable bit */ +#define DC4_ENABLE 0x80000000 /* data cache enable bit */ + +#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) +#define CACHE4_OFF (0)