From c49dc82a53135e4eef937ac5dbd18b560e36abe8 Mon Sep 17 00:00:00 2001 From: Akito Fujita Date: Mon, 15 Jun 1992 13:28:17 -0800 Subject: [PATCH] date and time created 92/06/15 06:28:17 by fujita SCCS-vsn: sys/luna68k/include/cpu.h 7.1 --- usr/src/sys/luna68k/include/cpu.h | 169 ++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 usr/src/sys/luna68k/include/cpu.h diff --git a/usr/src/sys/luna68k/include/cpu.h b/usr/src/sys/luna68k/include/cpu.h new file mode 100644 index 0000000000..03a230c1aa --- /dev/null +++ b/usr/src/sys/luna68k/include/cpu.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1992 OMRON Corporation. + * Copyright (c) 1982, 1990, 1992 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department. + * + * %sccs.include.redist.c% + * + * from: Utah $Hdr: cpu.h 1.16 91/03/25$ + * OMRON: $Id: cpu.h,v 1.2 92/06/14 06:27:54 moti Exp $ + * + * @(#)cpu.h 7.1 (Berkeley) %G% + */ + +/* + * Exported definitions unique to luna/68k cpu support, taken from: + * hp300/68k. + */ + +/* + * definitions of cpu-dependent requirements + * referenced in generic code + */ +#define COPY_SIGCODE /* copy sigcode above user stack in exec */ + +/* + * function vs. inline configuration; + * these are defined to get generic functions + * rather than inline or machine-dependent implementations + */ +#define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ +#undef NEED_FFS /* don't need ffs function */ +#undef NEED_BCMP /* don't need bcmp function */ +#undef NEED_STRLEN /* don't need strlen function */ + +#define cpu_exec(p) /* nothing */ +#define cpu_wait(p) /* nothing */ +#define cpu_setstack(p, ap) \ + (p)->p_md.md_regs[SP] = ap + +/* + * Arguments to hardclock, softclock and gatherstats + * encapsulate the previous machine state in an opaque + * clockframe; for 68k, use just what the hardware + * leaves on the stack. + */ +typedef struct intrframe { + char *pc; + int ps; +} clockframe; + +#define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) +#define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) +#define CLKF_PC(framep) ((framep)->pc) + + +/* + * Preempt the current process if in interrupt from user mode, + * or after the current trap/syscall if in system mode. + */ +#define need_resched() { want_resched++; aston(); } + +/* + * Give a profiling tick to the current process from the softclock + * interrupt. On 68k, request an ast to send us through trap(), + * marking the proc as needing a profiling tick. + */ +#define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } + +/* + * Notify the current process (p) that it has a signal pending, + * process as soon as possible. + */ +#define signotify(p) aston() + +#define aston() (astpending++) + +int astpending; /* need to trap before returning to user mode */ +int want_resched; /* resched() was called */ + + +/* + * simulated software interrupt register + */ +extern unsigned char ssir; + +#define SIR_NET 0x1 +#define SIR_CLOCK 0x2 + +#define siroff(x) ssir &= ~(x) +#define setsoftnet() ssir |= SIR_NET +#define setsoftclock() ssir |= SIR_CLOCK + +/* values for mmutype (assigned for quick testing) */ +#define MMU_68040 -2 /* 68040 on-chip MMU */ +#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ + +/* values for cpuspeed (not really related to clock speed due to caches) */ +#define MHZ_8 1 +#define MHZ_16 2 +#define MHZ_25 3 +#define MHZ_33 4 +#define MHZ_50 6 + +/* + * 68851 and 68030 MMU + */ +#define PMMU_LVLMASK 0x0007 +#define PMMU_INV 0x0400 +#define PMMU_WP 0x0800 +#define PMMU_ALV 0x1000 +#define PMMU_SO 0x2000 +#define PMMU_LV 0x4000 +#define PMMU_BE 0x8000 +#define PMMU_FAULT (PMMU_WP|PMMU_INV) + +/* + * 68040 MMU + */ +#define MMU4_RES 0x001 +#define MMU4_TTR 0x002 +#define MMU4_WP 0x004 +#define MMU4_MOD 0x010 +#define MMU4_CMMASK 0x060 +#define MMU4_SUP 0x080 +#define MMU4_U0 0x100 +#define MMU4_U1 0x200 +#define MMU4_GLB 0x400 +#define MMU4_BE 0x800 + +/* 680X0 function codes */ +#define FC_USERD 1 /* user data space */ +#define FC_USERP 2 /* user program space */ +#define FC_PURGE 3 /* HPMMU: clear TLB entries */ +#define FC_SUPERD 5 /* supervisor data space */ +#define FC_SUPERP 6 /* supervisor program space */ +#define FC_CPU 7 /* CPU space */ + +/* fields in the 68020 cache control register */ +#define IC_ENABLE 0x0001 /* enable instruction cache */ +#define IC_FREEZE 0x0002 /* freeze instruction cache */ +#define IC_CE 0x0004 /* clear instruction cache entry */ +#define IC_CLR 0x0008 /* clear entire instruction cache */ + +/* additional fields in the 68030 cache control register */ +#define IC_BE 0x0010 /* instruction burst enable */ +#define DC_ENABLE 0x0100 /* data cache enable */ +#define DC_FREEZE 0x0200 /* data cache freeze */ +#define DC_CE 0x0400 /* clear data cache entry */ +#define DC_CLR 0x0800 /* clear entire data cache */ +#define DC_BE 0x1000 /* data burst enable */ +#define DC_WA 0x2000 /* write allocate */ + +#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) +#define CACHE_OFF (DC_CLR|IC_CLR) +#define CACHE_CLR (CACHE_ON) +#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) +#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) + +/* 68040 cache control register */ +#define IC4_ENABLE 0x8000 /* instruction cache enable bit */ +#define DC4_ENABLE 0x80000000 /* data cache enable bit */ + +#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) +#define CACHE4_OFF (0) -- 2.20.1