projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / fpga / gate / fpga_gate_tb.flist
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fpga_gate_tb.flist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35+define+TOP=t2_fpga
36+define+FPGA_GATE
37+define+INITLATZERO
38+define+FPGA_SIM
39+define+LIB
40+define+FPGA
41+define+FPGA_MONITOR
42+incdir+$DV_ROOT/design/fpga/rtl
43$DV_ROOT/design/fpga/rtl/t2_fpga.v
44-y $DV_ROOT/design/fpga/opencores
45-y $DV_ROOT/design/fpga/rtl
46-v $DV_ROOT/design/sys/iop/spc/rtl/spc.v
47-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu.v
48-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf0_dp.v
49-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf1_dp.v
50-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
51-v $DV_ROOT/libs/clk/rtl/clkgen_ccx_cmp.v
52-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v
53-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx.v
54-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx.v
55-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_trep.v
56-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_tstg.v
57-v $DV_ROOT/libs/clk/rtl/clkgen_spc_cmp.v
58-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec.v
59-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
60-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_del_ctl.v
61-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dmo_dp.v
62-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu.v
63-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu.v
64-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt.v
65-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu.v
66-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
67-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu.v
68-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
69-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu.v
70-v $DV_ROOT/design/sys/iop/spc/rtl/spc_lb_ctl.v
71-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu.v
72-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb0_ctl.v
73-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb1_ctl.v
74-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb2_ctl.v
75-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
76-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu.v
77-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku.v
78-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu.v
79-v $DV_ROOT/design/sys/iop/spc/rtl/spc_rep1_dp.v
80-v $DV_ROOT/design/sys/iop/spc/spu/rtl/spu.v
81-v $DV_ROOT/design/sys/iop/spc/rtl/dmo_dp.v
82-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
83-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuad_ctl.v
84-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
85-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
86-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
87-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mar_dp.v
88-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mal_dp.v
89-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbl_dp.v
90-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcr_dp.v
91-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfd_dp.v
92-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_ob1_dp.v
93-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
94-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
95-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
96-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
97-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
98-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
99-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
100-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
101-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_ard_dp.v
102-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfd_dp.v
103-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfg_dp.v
104-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mal_dp.v
105-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbl_dp.v
106-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbr_dp.v
107-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcl_dp.v
108-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcr_dp.v
109-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob1_dp.v
110-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob2_dp.v
111-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_rep_dp.v
112-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
113-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
114-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
115-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
116-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
117-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
118-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
119-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
120-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
121-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
122-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
123-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
124-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
125-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
126-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
127-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
128-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
129-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
130-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
131-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
132-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
133-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
134-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
135-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
136-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
137-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
138-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
139-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
140-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
141-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
142-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
143-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
144-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
145-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
146-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
147-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
148-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
149-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v
150-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
151-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
152-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
153-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
154-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
155-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
156-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
157-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
158-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
159-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
160-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
161-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_edp_dp.v
162-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfg_dp.v
163-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbr_dp.v
164-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcl_dp.v
165-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_rep_dp.v
166-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
167-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
168-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
169-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
170-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
171-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
172-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
173-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
174-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
175-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
176-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
177-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
178-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
179-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
180-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
181-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
182-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
183-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
184-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
185-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
186-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
187-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
188-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
189-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
190-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
191-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
192-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
193-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
194-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
195-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
196-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
197-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
198-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
199-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
200-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
201-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
202-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
203-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
204-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
205-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
206-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
207-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
208-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
209-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
210-v $DV_ROOT/libs/rtl/n2_efuhdr1_ctl.v
211-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
212-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
213-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
214-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
215-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
216-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
217-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arc_ctl.v
218-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_srq_ctl.v
219-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
220-v $DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
221-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v
222-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v
223-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsd.v
224-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsa.v
225-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsc.v
226-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsg.v
227-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsf.v
228-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpse.v
229-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arb.v
230-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpa.v
231-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsb.v
232-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mar_dp.v
233-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpa.v
234-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsb.v
235-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsd.v
236-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpse.v
237-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsh.v
238-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsf.v
239-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_rep.v
240-v $DV_ROOT/libs/cl/cl_u1/cl_u1.v
241-v $DV_ROOT/libs/cl/cl_sc1/cl_sc1.v
242-v $DV_ROOT/libs/cl/cl_mc1/cl_mc1.v
243-v $DV_ROOT/libs/cl/cl_dp1/cl_dp1.v
244-v $DV_ROOT/libs/cl/cl_rtl_ext.v
245-v $DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl/n2_l2d_sp_512kb_cust.v
246-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsa.v
247-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsc.v
248-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsg.v
249-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v
250-v $DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
251-v $DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
252-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
253-v $DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
254-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
255-v $DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v
256-v $DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v
257-v $DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
258-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v
259-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
260-v $DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
261-v $DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v
Full OpenSPARC design & verification tarball including full HDL.