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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / fpga / rtl / fpga_rtl_synth.flist
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fpga_rtl_synth.flist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35+define+LIB
36+define+FPGA
37$DV_ROOT/design/fpga/opencores/timescale.v
38$DV_ROOT/design/fpga/opencores/mem_harness.v
39$DV_ROOT/design/fpga/opencores/raminfr.v
40$DV_ROOT/design/fpga/opencores/spc2wbm.v
41$DV_ROOT/design/fpga/opencores/uart_regs.v
42$DV_ROOT/design/fpga/opencores/uart_receiver.v
43$DV_ROOT/design/fpga/opencores/uart_rfifo.v
44$DV_ROOT/design/fpga/opencores/uart_sync_flops.v
45$DV_ROOT/design/fpga/opencores/uart_tfifo.v
46$DV_ROOT/design/fpga/opencores/uart_top.v
47$DV_ROOT/design/fpga/opencores/uart_transmitter.v
48$DV_ROOT/design/fpga/opencores/uart_wb.v
49$DV_ROOT/design/fpga/rtl/l2_dir.v
50$DV_ROOT/design/fpga/rtl/t2.v
51$DV_ROOT/design/fpga/rtl/t2_fpga.v
52$DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
53$DV_ROOT/design/sys/iop/ccx/rtl/ccx_arb.v
54$DV_ROOT/design/sys/iop/ccx/rtl/ccx_arc_ctl.v
55$DV_ROOT/design/sys/iop/ccx/rtl/ccx_ard_dp.v
56$DV_ROOT/design/sys/iop/ccx/rtl/ccx_rep.v
57$DV_ROOT/design/sys/iop/ccx/rtl/ccx_srq_ctl.v
58$DV_ROOT/design/sys/iop/ccx/rtl/ccx_trep.v
59$DV_ROOT/design/sys/iop/ccx/rtl/ccx_tstg.v
60$DV_ROOT/design/sys/iop/ccx/rtl/cpx.v
61$DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfd_dp.v
62$DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfg_dp.v
63$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpa.v
64$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsa.v
65$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsb.v
66$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsc.v
67$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsd.v
68$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpse.v
69$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsf.v
70$DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsg.v
71$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mal_dp.v
72$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mar_dp.v
73$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbl_dp.v
74$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbr_dp.v
75$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcl_dp.v
76$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcr_dp.v
77$DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob1_dp.v
78$DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob2_dp.v
79$DV_ROOT/design/sys/iop/ccx/rtl/cpx_rep_dp.v
80$DV_ROOT/design/sys/iop/ccx/rtl/pcx.v
81$DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfd_dp.v
82$DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfg_dp.v
83$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpa.v
84$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsa.v
85$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsb.v
86$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsc.v
87$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsd.v
88$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpse.v
89$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsf.v
90$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsg.v
91$DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsh.v
92$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mal_dp.v
93$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mar_dp.v
94$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbl_dp.v
95$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbr_dp.v
96$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcl_dp.v
97$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcr_dp.v
98$DV_ROOT/design/sys/iop/ccx/rtl/pcx_ob1_dp.v
99$DV_ROOT/design/sys/iop/ccx/rtl/pcx_rep_dp.v
100$DV_ROOT/design/sys/iop/l2t/rtl/l2t_dmo_dp.v
101$DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuad_ctl.v
102$DV_ROOT/design/sys/iop/spc/dec/rtl/dec.v
103$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
104$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
105$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_del_ctl.v
106$DV_ROOT/design/sys/iop/spc/exu/rtl/exu.v
107$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
108$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
109$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_edp_dp.v
110$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
111$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
112$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu.v
113$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
114$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
115$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
116$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
117$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
118$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
119$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
120$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
121$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
122$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
123$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
124$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
125$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt.v
126$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
127$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
128$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
129$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
130$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu.v
131$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
132$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
133$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
134$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
135$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
136$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
137$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu.v
138$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
139$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
140$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
141$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
142$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
143$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
144$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
145$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
146$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
147$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
148$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
149$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
150$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
151$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu.v
152$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
153$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
154$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu.v
155$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
156$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
157$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
158$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
159$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
160$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
161$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
162$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
163$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
164$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
165$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
166$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
167$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
168$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
169$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
170$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
171$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
172$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
173$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
174$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
175$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
176$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
177$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
178$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
179$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
180$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
181$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
182$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
183$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
184$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu.v
185$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
186$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
187$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
188$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
189$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
190$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
191$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
192$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
193$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
194$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
195$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
196$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
197$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
198$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
199$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
200$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
201$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
202$DV_ROOT/design/sys/iop/spc/pku/rtl/pku.v
203$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
204$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
205$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
206$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu.v
207$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
208$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
209$DV_ROOT/design/sys/iop/spc/rtl/dmo_dp.v
210$DV_ROOT/design/sys/iop/spc/rtl/spc.v
211$DV_ROOT/design/sys/iop/spc/rtl/spc_lb_ctl.v
212$DV_ROOT/design/sys/iop/spc/rtl/spc_mb0_ctl.v
213$DV_ROOT/design/sys/iop/spc/rtl/spc_mb1_ctl.v
214$DV_ROOT/design/sys/iop/spc/rtl/spc_mb2_ctl.v
215$DV_ROOT/design/sys/iop/spc/rtl/spc_msf0_dp.v
216$DV_ROOT/design/sys/iop/spc/rtl/spc_msf1_dp.v
217$DV_ROOT/design/sys/iop/spc/rtl/spc_rep1_dp.v
218$DV_ROOT/design/sys/iop/spc/spu/rtl/spu.v
219$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu.v
220$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
221$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
222$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
223$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
224$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
225$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
226$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
227$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
228$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
229$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
230$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
231$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
232$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
233$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
234$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
235$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
236$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
237$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
238$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
239$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
240$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
241$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v
242$DV_ROOT/libs/cl/cl_dp1/cl_dp1.v
243$DV_ROOT/libs/cl/cl_mc1/cl_mc1.v
244$DV_ROOT/libs/cl/cl_rtl_ext.v
245$DV_ROOT/libs/cl/cl_sc1/cl_sc1.v
246$DV_ROOT/libs/cl/cl_u1/cl_u1.v
247$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v
248$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v
249$DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
250$DV_ROOT/libs/clk/rtl/clkgen_ccx_cmp.v
251$DV_ROOT/libs/clk/rtl/clkgen_spc_cmp.v
252$DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
253$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
254$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v
255$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v
256$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
257$DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
258$DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v
259$DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v
260$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
261$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v
262$DV_ROOT/libs/rtl/n2_efuhdr1_ctl.v
263$DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
264$DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v
265$DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
266$DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
267$DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl/n2_l2d_sp_512kb_cust.v
Full OpenSPARC design & verification tarball including full HDL.