Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: t2_fpga.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1 ns / 100 ps | |
36 | module t2_fpga( | |
37 | clk, | |
38 | cts_pad_i, | |
39 | dsr_pad_i, | |
40 | efu_spc_fuse_ixfer_en, | |
41 | ri_pad_i, | |
42 | srx_pad_i, sys_interrupt_source_i, | |
43 | wbm_ack_i8, wbm_adr_uart, wbm_cycle_nc_not_uart, | |
44 | wbm_cycle_uart, wbm_data_i8, wbm_data_uart_i, wbm_sel_uart, | |
45 | wbm_strobe_nc_not_uart, wbm_strobe_uart, | |
46 | cpx_io_grant_cx, cpx_sctag0_grant_cx, | |
47 | cpx_sctag1_grant_cx, cpx_sctag2_grant_cx, cpx_sctag3_grant_cx, | |
48 | cpx_sctag4_grant_cx, cpx_sctag5_grant_cx, cpx_sctag6_grant_cx, | |
49 | cpx_sctag7_grant_cx, | |
50 | dmo_dout, dtr_pad_o, int_o, | |
51 | pcx_spc1_grant_px, pcx_spc2_grant_px, pcx_spc3_grant_px, | |
52 | pcx_spc4_grant_px, pcx_spc5_grant_px, pcx_spc6_grant_px, | |
53 | pcx_spc7_grant_px, rts_pad_o, | |
54 | spc_core_running_status, | |
55 | spc_dbg_instr_cmt_grp0, spc_dbg_instr_cmt_grp1, spc_efu_fuse_ddata, | |
56 | spc_efu_fuse_dxfer_en, spc_efu_fuse_idata, spc_efu_fuse_ixfer_en, | |
57 | spc_grant_o, spc_grant_o_8, spc_hardstop_request, spc_mbist_done, | |
58 | spc_mbist_fail, spc_shscan_scan_out, spc_softstop_request, | |
59 | spc_ss_complete, spc_tcu_lbist_done, spc_tcu_lbist_scan_out, | |
60 | spc_tcu_mbist_scan_out, spc_trigger_pulse, stx_pad_o, | |
61 | wbm_ack_nc_not_uart, wbm_ack_uart, wbm_cycle_o8, wbm_data_nc_not_uart, | |
62 | wbm_data_uart, wbm_strobe_o8, | |
63 | mem_harness0_wbs_addr_i , | |
64 | mem_harness1_wbs_addr_i , | |
65 | wbm_ack_i0 , | |
66 | wbm_ack_i1 , | |
67 | wbm_addr_o0 , | |
68 | wbm_addr_o1 , | |
69 | wbm_addr_o8 , | |
70 | wbm_cycle_o0 , | |
71 | wbm_cycle_o1 , | |
72 | wbm_data_i0 , | |
73 | wbm_data_i1 , | |
74 | wbm_data_o0 , | |
75 | wbm_data_o1 , | |
76 | wbm_data_o8 , | |
77 | wbm_sel_o0 , | |
78 | wbm_sel_o1 , | |
79 | wbm_sel_o8, | |
80 | wbm_strobe_o0 , | |
81 | wbm_strobe_o1 , | |
82 | wbm_we_o0 , | |
83 | wbm_we_o1 | |
84 | ); | |
85 | ||
86 | wire [159:0] ccx_lstg_in = 0; | |
87 | wire [159:0] ccx_rstg_in = 0; | |
88 | input clk; | |
89 | wire [191:0] cpu_rep0_in = 0; | |
90 | wire [191:0] cpu_rep1_in = 0; | |
91 | input cts_pad_i; | |
92 | input dsr_pad_i; | |
93 | input efu_spc_fuse_ixfer_en; | |
94 | input ri_pad_i; | |
95 | wire sctag2_cpx_atom_cq = 0; | |
96 | wire [145:0] sctag2_cpx_data_ca = 0; | |
97 | wire [7:0] sctag2_cpx_req_cq = 0; | |
98 | wire sctag2_pcx_stall_pq = 0; | |
99 | wire sctag3_cpx_atom_cq = 0; | |
100 | wire [145:0] sctag3_cpx_data_ca = 0; | |
101 | wire [7:0] sctag3_cpx_req_cq = 0; | |
102 | wire sctag3_pcx_stall_pq = 0; | |
103 | wire sctag4_cpx_atom_cq = 0; | |
104 | wire [145:0] sctag4_cpx_data_ca = 0; | |
105 | wire [7:0] sctag4_cpx_req_cq = 0; | |
106 | wire sctag4_pcx_stall_pq = 0; | |
107 | wire sctag5_cpx_atom_cq = 0; | |
108 | wire [145:0] sctag5_cpx_data_ca = 0; | |
109 | wire [7:0] sctag5_cpx_req_cq = 0; | |
110 | wire sctag5_pcx_stall_pq = 0; | |
111 | wire sctag6_cpx_atom_cq = 0; | |
112 | wire [145:0] sctag6_cpx_data_ca = 0; | |
113 | wire [7:0] sctag6_cpx_req_cq = 0; | |
114 | wire sctag6_pcx_stall_pq = 0; | |
115 | wire sctag7_cpx_atom_cq = 0; | |
116 | wire [145:0] sctag7_cpx_data_ca = 0; | |
117 | wire [7:0] sctag7_cpx_req_cq = 0; | |
118 | ||
119 | ||
120 | wire sctag7_pcx_stall_pq; | |
121 | wire [8:0] spc1_pcx_atm_pq; | |
122 | wire [129:0] spc1_pcx_data_pa = 0; | |
123 | wire [8:0] spc1_pcx_req_pq = 0; | |
124 | wire [8:0] spc2_pcx_atm_pq = 0; | |
125 | wire [129:0] spc2_pcx_data_pa = 0; | |
126 | wire [8:0] spc2_pcx_req_pq = 0; | |
127 | wire [8:0] spc3_pcx_atm_pq = 0; | |
128 | wire [129:0] spc3_pcx_data_pa = 0; | |
129 | wire [8:0] spc3_pcx_req_pq = 0; | |
130 | wire [8:0] spc4_pcx_atm_pq = 0; | |
131 | wire [129:0] spc4_pcx_data_pa = 0; | |
132 | wire [8:0] spc4_pcx_req_pq = 0; | |
133 | wire [8:0] spc5_pcx_atm_pq = 0; | |
134 | wire [129:0] spc5_pcx_data_pa = 0; | |
135 | wire [8:0] spc5_pcx_req_pq = 0; | |
136 | wire [8:0] spc6_pcx_atm_pq = 0; | |
137 | wire [129:0] spc6_pcx_data_pa = 0; | |
138 | wire [8:0] spc6_pcx_req_pq = 0; | |
139 | wire [8:0] spc7_pcx_atm_pq = 0; | |
140 | wire [129:0] spc7_pcx_data_pa = 0; | |
141 | wire [8:0] spc7_pcx_req_pq = 0; | |
142 | ||
143 | input srx_pad_i; | |
144 | input [5:0] sys_interrupt_source_i; | |
145 | output wbm_ack_i8; | |
146 | output [(3 - 1):0] wbm_adr_uart; | |
147 | output wbm_cycle_nc_not_uart; | |
148 | output wbm_cycle_uart; | |
149 | output [(64 - 1):0] wbm_data_i8; | |
150 | output [7:0] wbm_data_uart_i; | |
151 | input [3:0] wbm_sel_uart; | |
152 | output wbm_strobe_nc_not_uart; | |
153 | output wbm_strobe_uart; | |
154 | wire [159:0] ccx_lstg_out; | |
155 | wire [159:0] ccx_rstg_out; | |
156 | wire [191:0] cpu_rep0_out; | |
157 | wire [191:0] cpu_rep1_out; | |
158 | output [7:0] cpx_io_grant_cx; | |
159 | output [7:0] cpx_sctag0_grant_cx; | |
160 | output [7:0] cpx_sctag1_grant_cx; | |
161 | output [7:0] cpx_sctag2_grant_cx; | |
162 | output [7:0] cpx_sctag3_grant_cx; | |
163 | output [7:0] cpx_sctag4_grant_cx; | |
164 | output [7:0] cpx_sctag5_grant_cx; | |
165 | output [7:0] cpx_sctag6_grant_cx; | |
166 | output [7:0] cpx_sctag7_grant_cx; | |
167 | wire [145:0] cpx_spc1_data_cx2; | |
168 | wire [145:0] cpx_spc2_data_cx2; | |
169 | wire [145:0] cpx_spc3_data_cx2; | |
170 | wire [145:0] cpx_spc4_data_cx2; | |
171 | wire [145:0] cpx_spc5_data_cx2; | |
172 | wire [145:0] cpx_spc6_data_cx2; | |
173 | wire [145:0] cpx_spc7_data_cx2; | |
174 | output [35:0] dmo_dout; | |
175 | output dtr_pad_o; | |
176 | output int_o; | |
177 | wire pcx_sctag2_atm_px1; | |
178 | wire [129:0] pcx_sctag2_data_px2; | |
179 | wire pcx_sctag2_data_rdy_px1; | |
180 | wire pcx_sctag3_atm_px1; | |
181 | wire [129:0] pcx_sctag3_data_px2; | |
182 | wire pcx_sctag3_data_rdy_px1; | |
183 | wire pcx_sctag4_atm_px1; | |
184 | wire [129:0] pcx_sctag4_data_px2; | |
185 | wire pcx_sctag4_data_rdy_px1; | |
186 | wire pcx_sctag5_atm_px1; | |
187 | wire [129:0] pcx_sctag5_data_px2; | |
188 | wire pcx_sctag5_data_rdy_px1; | |
189 | wire pcx_sctag6_atm_px1; | |
190 | wire [129:0] pcx_sctag6_data_px2; | |
191 | wire pcx_sctag6_data_rdy_px1; | |
192 | wire pcx_sctag7_atm_px1; | |
193 | wire [129:0] pcx_sctag7_data_px2; | |
194 | wire pcx_sctag7_data_rdy_px1; | |
195 | output [8:0] pcx_spc1_grant_px; | |
196 | output [8:0] pcx_spc2_grant_px; | |
197 | output [8:0] pcx_spc3_grant_px; | |
198 | output [8:0] pcx_spc4_grant_px; | |
199 | output [8:0] pcx_spc5_grant_px; | |
200 | output [8:0] pcx_spc6_grant_px; | |
201 | output [8:0] pcx_spc7_grant_px; | |
202 | output rts_pad_o; | |
203 | output [7:0] spc_core_running_status; | |
204 | output [1:0] spc_dbg_instr_cmt_grp0; | |
205 | output [1:0] spc_dbg_instr_cmt_grp1; | |
206 | output spc_efu_fuse_ddata; | |
207 | output spc_efu_fuse_dxfer_en; | |
208 | output spc_efu_fuse_idata; | |
209 | output spc_efu_fuse_ixfer_en; | |
210 | output [4:0] spc_grant_o; | |
211 | output spc_grant_o_8; | |
212 | output spc_hardstop_request; | |
213 | output spc_mbist_done; | |
214 | output spc_mbist_fail; | |
215 | output spc_shscan_scan_out; | |
216 | output spc_softstop_request; | |
217 | output spc_ss_complete; | |
218 | output spc_tcu_lbist_done; | |
219 | output spc_tcu_lbist_scan_out; | |
220 | output spc_tcu_mbist_scan_out; | |
221 | output spc_trigger_pulse; | |
222 | output stx_pad_o; | |
223 | output wbm_ack_nc_not_uart; | |
224 | output wbm_ack_uart; | |
225 | output wbm_cycle_o8; | |
226 | output [(64 - 1):0] wbm_data_nc_not_uart; | |
227 | output [31:0] wbm_data_uart; | |
228 | output wbm_strobe_o8; | |
229 | ||
230 | output [63:0] mem_harness0_wbs_addr_i ; | |
231 | output [63:0] mem_harness1_wbs_addr_i ; | |
232 | output wbm_ack_i0 ; | |
233 | output wbm_ack_i1 ; | |
234 | output [(64 - 1):0] wbm_addr_o0 ; | |
235 | output [(64 - 1):0] wbm_addr_o1 ; | |
236 | output [(64 - 1):0] wbm_addr_o8 ; | |
237 | output wbm_cycle_o0 ; | |
238 | output wbm_cycle_o1 ; | |
239 | output [(64 - 1):0] wbm_data_i0 ; | |
240 | output [(64 - 1):0] wbm_data_i1 ; | |
241 | output [(64 - 1):0] wbm_data_o0 ; | |
242 | output [(64 - 1):0] wbm_data_o1 ; | |
243 | output [(64 - 1):0] wbm_data_o8 ; | |
244 | output [((64 / 8) - 1):0] wbm_sel_o0 ; | |
245 | output [((64 / 8) - 1):0] wbm_sel_o1 ; | |
246 | output [((64 / 8) - 1):0] wbm_sel_o8; | |
247 | output wbm_strobe_o0 ; | |
248 | output wbm_strobe_o1 ; | |
249 | output wbm_we_o0 ; | |
250 | output wbm_we_o1 ; | |
251 | ||
252 | ||
253 | wire gclk; | |
254 | wire [63:0] mem_harness0_wbs_addr_i; | |
255 | wire [63:0] mem_harness1_wbs_addr_i; | |
256 | wire reset; | |
257 | wire wbm_ack_i0; | |
258 | wire wbm_ack_i1; | |
259 | wire [(64 - 1):0] wbm_addr_o0; | |
260 | wire [(64 - 1):0] wbm_addr_o1; | |
261 | wire [(64 - 1):0] wbm_addr_o8; | |
262 | wire wbm_cycle_o0; | |
263 | wire wbm_cycle_o1; | |
264 | wire [(64 - 1):0] wbm_data_i0; | |
265 | wire [(64 - 1):0] wbm_data_i1; | |
266 | wire [(64 - 1):0] wbm_data_o0; | |
267 | wire [(64 - 1):0] wbm_data_o1; | |
268 | wire [(64 - 1):0] wbm_data_o8; | |
269 | wire [((64 / 8) - 1):0] | |
270 | wbm_sel_o0; | |
271 | wire [((64 / 8) - 1):0] | |
272 | wbm_sel_o1; | |
273 | wire [((64 / 8) - 1):0] | |
274 | wbm_sel_o8; | |
275 | wire wbm_strobe_o0; | |
276 | wire wbm_strobe_o1; | |
277 | wire wbm_we_o0; | |
278 | wire wbm_we_o1; | |
279 | wire wbm_we_o8; | |
280 | reg [7:0] count; | |
281 | ||
282 | `ifdef FPGA_SIM | |
283 | reg cmp_refclk ; | |
284 | assign GlobalReset = 1'b1; | |
285 | initial begin // generate cmp ref clock (100 MHZ) | |
286 | count = 0; | |
287 | cmp_refclk = 1'b0; | |
288 | end | |
289 | ||
290 | initial begin // generate cmp ref clock (100 MHZ) | |
291 | #7; | |
292 | forever #(100) cmp_refclk = ~cmp_refclk; | |
293 | end | |
294 | `else | |
295 | wire cmp_refclk; | |
296 | `endif | |
297 | ||
298 | wire clk1; | |
299 | wire clk2; | |
300 | reg [7:0] uart_dat; | |
301 | reg [2:0] adr_uart; | |
302 | reg rst; | |
303 | ||
304 | assign gclk = clk; | |
305 | ||
306 | ||
307 | // synopsys translate_off | |
308 | assign sys_interrupt_source_i = 6'h0 ; | |
309 | ||
310 | defparam mem_harness0.memfilename = "memory0.hex"; | |
311 | defparam mem_harness1.memfilename = "memory1.hex"; | |
312 | defparam mem_harness2.initmem = 1; | |
313 | defparam mem_harness2.loadmem = 1; | |
314 | defparam mem_harness2.memfilename = "memory2.hex"; | |
315 | defparam mem_harness0.addr_bits = 26; | |
316 | defparam mem_harness1.addr_bits = 26; | |
317 | defparam mem_harness2.addr_bits = 20; | |
318 | // synopsys translate_on | |
319 | ||
320 | assign mem_harness0_wbs_addr_i = {wbm_addr_o0[(64 - 1):7], | |
321 | wbm_addr_o0[5:0]}; | |
322 | assign mem_harness1_wbs_addr_i = {wbm_addr_o1[(64 - 1):7], | |
323 | wbm_addr_o1[5:0]}; | |
324 | assign clk = cmp_refclk; | |
325 | assign reset = rst; | |
326 | assign wbm_strobe_nc_not_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 0 | |
327 | : wbm_strobe_o8); | |
328 | assign wbm_strobe_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? | |
329 | wbm_strobe_o8 : 0); | |
330 | assign wbm_cycle_nc_not_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 0 | |
331 | : wbm_cycle_o8); | |
332 | assign wbm_cycle_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? | |
333 | wbm_cycle_o8 : 0); | |
334 | assign wbm_ack_i8 = (wbm_ack_nc_not_uart | wbm_ack_uart); | |
335 | assign wbm_data_i8 = (wbm_ack_nc_not_uart ? wbm_data_nc_not_uart : {8 { | |
336 | wbm_data_uart[7:0]}}); | |
337 | assign wbm_data_uart_i = wbm_data_o8[7:0]; | |
338 | assign wbm_adr_uart[2:0] = (wbm_sel_o8[0] ? 3'b0 : (wbm_sel_o8[1] ? 3'b1 | |
339 | : (wbm_sel_o8[2] ? 3'd2 : (wbm_sel_o8[3] ? 3'd3 : (wbm_sel_o8[4] | |
340 | ? 3'd4 : (wbm_sel_o8[5] ? 3'd5 : (wbm_sel_o8[6] ? 3'd6 : 3'd7))) | |
341 | )))); | |
342 | ||
343 | t2 t2( .ccx_lstg_in (ccx_lstg_in[159:0]), | |
344 | .ccx_rstg_in (ccx_rstg_in[159:0]), | |
345 | .cluster_arst_l ((~reset)), | |
346 | .cpu_rep0_in (cpu_rep0_in[191:0]), | |
347 | .cpu_rep1_in (cpu_rep1_in[191:0]), | |
348 | .gclk (clk), | |
349 | .sctag2_cpx_atom_cq (sctag2_cpx_atom_cq), | |
350 | .sctag2_cpx_data_ca (sctag2_cpx_data_ca[145:0]), | |
351 | .sctag2_cpx_req_cq (sctag2_cpx_req_cq[7:0]), | |
352 | .sctag2_pcx_stall_pq (sctag2_pcx_stall_pq), | |
353 | .sctag3_cpx_atom_cq (sctag3_cpx_atom_cq), | |
354 | .sctag3_cpx_data_ca (sctag3_cpx_data_ca[145:0]), | |
355 | .sctag3_cpx_req_cq (sctag3_cpx_req_cq[7:0]), | |
356 | .sctag3_pcx_stall_pq (sctag3_pcx_stall_pq), | |
357 | .sctag4_cpx_atom_cq (sctag4_cpx_atom_cq), | |
358 | .sctag4_cpx_data_ca (sctag4_cpx_data_ca[145:0]), | |
359 | .sctag4_cpx_req_cq (sctag4_cpx_req_cq[7:0]), | |
360 | .sctag4_pcx_stall_pq (sctag4_pcx_stall_pq), | |
361 | .sctag5_cpx_atom_cq (sctag5_cpx_atom_cq), | |
362 | .sctag5_cpx_data_ca (sctag5_cpx_data_ca[145:0]), | |
363 | .sctag5_cpx_req_cq (sctag5_cpx_req_cq[7:0]), | |
364 | .sctag5_pcx_stall_pq (sctag5_pcx_stall_pq), | |
365 | .sctag6_cpx_atom_cq (sctag6_cpx_atom_cq), | |
366 | .sctag6_cpx_data_ca (sctag6_cpx_data_ca[145:0]), | |
367 | .sctag6_cpx_req_cq (sctag6_cpx_req_cq[7:0]), | |
368 | .sctag6_pcx_stall_pq (sctag6_pcx_stall_pq), | |
369 | .sctag7_cpx_atom_cq (sctag7_cpx_atom_cq), | |
370 | .sctag7_cpx_data_ca (sctag7_cpx_data_ca[145:0]), | |
371 | .sctag7_cpx_req_cq (sctag7_cpx_req_cq[7:0]), | |
372 | .sctag7_pcx_stall_pq (sctag7_pcx_stall_pq), | |
373 | .spc1_pcx_atm_pq (spc1_pcx_atm_pq[8:0]), | |
374 | .spc1_pcx_data_pa (spc1_pcx_data_pa[129:0]), | |
375 | .spc1_pcx_req_pq (spc1_pcx_req_pq[8:0]), | |
376 | .spc2_pcx_atm_pq (spc2_pcx_atm_pq[8:0]), | |
377 | .spc2_pcx_data_pa (spc2_pcx_data_pa[129:0]), | |
378 | .spc2_pcx_req_pq (spc2_pcx_req_pq[8:0]), | |
379 | .spc3_pcx_atm_pq (spc3_pcx_atm_pq[8:0]), | |
380 | .spc3_pcx_data_pa (spc3_pcx_data_pa[129:0]), | |
381 | .spc3_pcx_req_pq (spc3_pcx_req_pq[8:0]), | |
382 | .spc4_pcx_atm_pq (spc4_pcx_atm_pq[8:0]), | |
383 | .spc4_pcx_data_pa (spc4_pcx_data_pa[129:0]), | |
384 | .spc4_pcx_req_pq (spc4_pcx_req_pq[8:0]), | |
385 | .spc5_pcx_atm_pq (spc5_pcx_atm_pq[8:0]), | |
386 | .spc5_pcx_data_pa (spc5_pcx_data_pa[129:0]), | |
387 | .spc5_pcx_req_pq (spc5_pcx_req_pq[8:0]), | |
388 | .spc6_pcx_atm_pq (spc6_pcx_atm_pq[8:0]), | |
389 | .spc6_pcx_data_pa (spc6_pcx_data_pa[129:0]), | |
390 | .spc6_pcx_req_pq (spc6_pcx_req_pq[8:0]), | |
391 | .spc7_pcx_atm_pq (spc7_pcx_atm_pq[8:0]), | |
392 | .spc7_pcx_data_pa (spc7_pcx_data_pa[129:0]), | |
393 | .spc7_pcx_req_pq (spc7_pcx_req_pq[8:0]), | |
394 | .sys_interrupt_source_i (sys_interrupt_source_i[5:0]), | |
395 | .tcu_aclk (reset), | |
396 | .wbm_ack_i0 (wbm_ack_i0), | |
397 | .wbm_ack_i1 (wbm_ack_i1), | |
398 | .wbm_ack_i8 (wbm_ack_i8), | |
399 | .wbm_data_i0 (wbm_data_i0[(64 - 1):0]), | |
400 | .wbm_data_i1 (wbm_data_i1[(64 - 1):0]), | |
401 | .wbm_data_i8 (wbm_data_i8[(64 - 1):0]), | |
402 | .ccx_lstg_out (ccx_lstg_out[159:0]), | |
403 | .ccx_rstg_out (ccx_rstg_out[159:0]), | |
404 | .cpu_rep0_out (cpu_rep0_out[191:0]), | |
405 | .cpu_rep1_out (cpu_rep1_out[191:0]), | |
406 | .cpx_io_grant_cx (cpx_io_grant_cx[7:0]), | |
407 | .cpx_sctag0_grant_cx (cpx_sctag0_grant_cx[7:0]), | |
408 | .cpx_sctag1_grant_cx (cpx_sctag1_grant_cx[7:0]), | |
409 | .cpx_sctag2_grant_cx (cpx_sctag2_grant_cx[7:0]), | |
410 | .cpx_sctag3_grant_cx (cpx_sctag3_grant_cx[7:0]), | |
411 | .cpx_sctag4_grant_cx (cpx_sctag4_grant_cx[7:0]), | |
412 | .cpx_sctag5_grant_cx (cpx_sctag5_grant_cx[7:0]), | |
413 | .cpx_sctag6_grant_cx (cpx_sctag6_grant_cx[7:0]), | |
414 | .cpx_sctag7_grant_cx (cpx_sctag7_grant_cx[7:0]), | |
415 | .cpx_spc1_data_cx2 (cpx_spc1_data_cx2[145:0]), | |
416 | .cpx_spc2_data_cx2 (cpx_spc2_data_cx2[145:0]), | |
417 | .cpx_spc3_data_cx2 (cpx_spc3_data_cx2[145:0]), | |
418 | .cpx_spc4_data_cx2 (cpx_spc4_data_cx2[145:0]), | |
419 | .cpx_spc5_data_cx2 (cpx_spc5_data_cx2[145:0]), | |
420 | .cpx_spc6_data_cx2 (cpx_spc6_data_cx2[145:0]), | |
421 | .cpx_spc7_data_cx2 (cpx_spc7_data_cx2[145:0]), | |
422 | .dmo_dout (dmo_dout[35:0]), | |
423 | .pcx_sctag2_atm_px1 (pcx_sctag2_atm_px1), | |
424 | .pcx_sctag2_data_px2 (pcx_sctag2_data_px2[129:0]), | |
425 | .pcx_sctag2_data_rdy_px1 (pcx_sctag2_data_rdy_px1), | |
426 | .pcx_sctag3_atm_px1 (pcx_sctag3_atm_px1), | |
427 | .pcx_sctag3_data_px2 (pcx_sctag3_data_px2[129:0]), | |
428 | .pcx_sctag3_data_rdy_px1 (pcx_sctag3_data_rdy_px1), | |
429 | .pcx_sctag4_atm_px1 (pcx_sctag4_atm_px1), | |
430 | .pcx_sctag4_data_px2 (pcx_sctag4_data_px2[129:0]), | |
431 | .pcx_sctag4_data_rdy_px1 (pcx_sctag4_data_rdy_px1), | |
432 | .pcx_sctag5_atm_px1 (pcx_sctag5_atm_px1), | |
433 | .pcx_sctag5_data_px2 (pcx_sctag5_data_px2[129:0]), | |
434 | .pcx_sctag5_data_rdy_px1 (pcx_sctag5_data_rdy_px1), | |
435 | .pcx_sctag6_atm_px1 (pcx_sctag6_atm_px1), | |
436 | .pcx_sctag6_data_px2 (pcx_sctag6_data_px2[129:0]), | |
437 | .pcx_sctag6_data_rdy_px1 (pcx_sctag6_data_rdy_px1), | |
438 | .pcx_sctag7_atm_px1 (pcx_sctag7_atm_px1), | |
439 | .pcx_sctag7_data_px2 (pcx_sctag7_data_px2[129:0]), | |
440 | .pcx_sctag7_data_rdy_px1 (pcx_sctag7_data_rdy_px1), | |
441 | .pcx_spc1_grant_px (pcx_spc1_grant_px[8:0]), | |
442 | .pcx_spc2_grant_px (pcx_spc2_grant_px[8:0]), | |
443 | .pcx_spc3_grant_px (pcx_spc3_grant_px[8:0]), | |
444 | .pcx_spc4_grant_px (pcx_spc4_grant_px[8:0]), | |
445 | .pcx_spc5_grant_px (pcx_spc5_grant_px[8:0]), | |
446 | .pcx_spc6_grant_px (pcx_spc6_grant_px[8:0]), | |
447 | .pcx_spc7_grant_px (pcx_spc7_grant_px[8:0]), | |
448 | .scan_out (), | |
449 | .spc_core_running_status (spc_core_running_status[7:0]), | |
450 | .spc_dbg_instr_cmt_grp0 (spc_dbg_instr_cmt_grp0[1:0]), | |
451 | .spc_dbg_instr_cmt_grp1 (spc_dbg_instr_cmt_grp1[1:0]), | |
452 | .spc_efu_fuse_ddata (spc_efu_fuse_ddata), | |
453 | .spc_efu_fuse_dxfer_en (spc_efu_fuse_dxfer_en), | |
454 | .spc_efu_fuse_idata (spc_efu_fuse_idata), | |
455 | .spc_efu_fuse_ixfer_en (spc_efu_fuse_ixfer_en), | |
456 | .spc_grant_o (spc_grant_o[4:0]), | |
457 | .spc_grant_o_8 (spc_grant_o_8), | |
458 | .spc_hardstop_request (spc_hardstop_request), | |
459 | .spc_mbist_done (spc_mbist_done), | |
460 | .spc_mbist_fail (spc_mbist_fail), | |
461 | .spc_shscan_scan_out (spc_shscan_scan_out), | |
462 | .spc_softstop_request (spc_softstop_request), | |
463 | .spc_ss_complete (spc_ss_complete), | |
464 | .spc_tcu_lbist_done (spc_tcu_lbist_done), | |
465 | .spc_tcu_lbist_scan_out (spc_tcu_lbist_scan_out), | |
466 | .spc_tcu_mbist_scan_out (spc_tcu_mbist_scan_out), | |
467 | .spc_trigger_pulse (spc_trigger_pulse), | |
468 | .wbm_addr_o0 (wbm_addr_o0[(64 - 1):0]), | |
469 | .wbm_addr_o1 (wbm_addr_o1[(64 - 1):0]), | |
470 | .wbm_addr_o8 (wbm_addr_o8[(64 - 1):0]), | |
471 | .wbm_cycle_o0 (wbm_cycle_o0), | |
472 | .wbm_cycle_o1 (wbm_cycle_o1), | |
473 | .wbm_cycle_o8 (wbm_cycle_o8), | |
474 | .wbm_data_o0 (wbm_data_o0[(64 - 1):0]), | |
475 | .wbm_data_o1 (wbm_data_o1[(64 - 1):0]), | |
476 | .wbm_data_o8 (wbm_data_o8[(64 - 1):0]), | |
477 | .wbm_sel_o0 (wbm_sel_o0[((64 / 8) - 1):0]), | |
478 | .wbm_sel_o1 (wbm_sel_o1[((64 / 8) - 1):0]), | |
479 | .wbm_sel_o8 (wbm_sel_o8[((64 / 8) - 1):0]), | |
480 | .wbm_strobe_o0 (wbm_strobe_o0), | |
481 | .wbm_strobe_o1 (wbm_strobe_o1), | |
482 | .wbm_strobe_o8 (wbm_strobe_o8), | |
483 | .wbm_we_o0 (wbm_we_o0), | |
484 | .wbm_we_o1 (wbm_we_o1), | |
485 | .wbm_we_o8 (wbm_we_o8)); | |
486 | ||
487 | mem_harness mem_harness0( | |
488 | .sys_clock_i (clk), | |
489 | .sys_reset_i (reset), | |
490 | .wbs_cycle_i (wbm_cycle_o0), | |
491 | .wbs_strobe_i (wbm_strobe_o0), | |
492 | .wbs_addr_i (mem_harness0_wbs_addr_i), | |
493 | .wbs_data_i (wbm_data_o0[(64 - 1):0]), | |
494 | .wbs_we_i (wbm_we_o0), | |
495 | .wbs_sel_i (wbm_sel_o0[((64 / 8) - 1):0]), | |
496 | .wbs_ack_o (wbm_ack_i0), | |
497 | .wbs_data_o (wbm_data_i0)); | |
498 | mem_harness mem_harness1( | |
499 | .sys_clock_i (clk), | |
500 | .sys_reset_i (reset), | |
501 | .wbs_cycle_i (wbm_cycle_o1), | |
502 | .wbs_strobe_i (wbm_strobe_o1), | |
503 | .wbs_addr_i (mem_harness1_wbs_addr_i), | |
504 | .wbs_data_i (wbm_data_o1[(64 - 1):0]), | |
505 | .wbs_we_i (wbm_we_o1), | |
506 | .wbs_sel_i (wbm_sel_o1[((64 / 8) - 1):0]), | |
507 | .wbs_ack_o (wbm_ack_i1), | |
508 | .wbs_data_o (wbm_data_i1)); | |
509 | mem_harness mem_harness2( | |
510 | .sys_clock_i (clk), | |
511 | .sys_reset_i (reset), | |
512 | .wbs_cycle_i (wbm_cycle_nc_not_uart), | |
513 | .wbs_strobe_i (wbm_strobe_nc_not_uart), | |
514 | .wbs_addr_i (wbm_addr_o8[(64 - 1):0]), | |
515 | .wbs_data_i (wbm_data_o8[(64 - 1):0]), | |
516 | .wbs_we_i (wbm_we_o8), | |
517 | .wbs_sel_i (wbm_sel_o8[((64 / 8) - 1):0]), | |
518 | .wbs_ack_o (wbm_ack_nc_not_uart), | |
519 | .wbs_data_o (wbm_data_nc_not_uart[(64 - | |
520 | 1):0])); | |
521 | ||
522 | uart_top uart_top( | |
523 | .wb_clk_i (clk), | |
524 | .wb_rst_i (reset), | |
525 | .wb_adr_i (wbm_adr_uart[(3 - 1):0]), | |
526 | .wb_dat_i (wbm_data_uart_i[7:0]), | |
527 | .wb_dat_o (wbm_data_uart[31:0]), | |
528 | .wb_we_i (wbm_we_o8), | |
529 | .wb_stb_i (wbm_strobe_uart), | |
530 | .wb_cyc_i (wbm_cycle_uart), | |
531 | .wb_sel_i (wbm_sel_uart[3:0]), | |
532 | .wb_ack_o (wbm_ack_uart), | |
533 | .int_o (int_o), | |
534 | .srx_pad_i (srx_pad_i), | |
535 | .stx_pad_o (stx_pad_o), | |
536 | .rts_pad_o (rts_pad_o), | |
537 | .cts_pad_i (cts_pad_i), | |
538 | .dtr_pad_o (dtr_pad_o), | |
539 | .dsr_pad_i (dsr_pad_i), | |
540 | .ri_pad_i (ri_pad_i)); | |
541 | ||
542 | always @(negedge clk) begin | |
543 | if ((wbm_cycle_uart & wbm_strobe_uart) & wbm_we_o8) begin | |
544 | uart_dat <= wbm_data_uart_i; | |
545 | adr_uart <= wbm_adr_uart; | |
546 | end | |
547 | if (wbm_ack_uart) begin | |
548 | $display("SSI CONSOLE WRITE 0 %x %x", adr_uart, uart_dat); | |
549 | end | |
550 | end | |
551 | always @(posedge clk) if (count < 8'hf0) begin | |
552 | rst <= 1'b1; | |
553 | count <= (count + 8'b1); | |
554 | end | |
555 | else begin | |
556 | rst <= 1'b0; | |
557 | end | |
558 | ||
559 | // synopsys translate_off | |
560 | `ifdef FPGA_SIM | |
561 | ||
562 | reg [47:0] pc0_w ; | |
563 | reg [47:0] last_pc ; | |
564 | reg timeout_count_en ; | |
565 | reg [31:0] timeout_count ; | |
566 | ||
567 | initial | |
568 | begin | |
569 | timeout_count_en = 1'b0 ; | |
570 | timeout_count = 32'h00000000 ; | |
571 | end | |
572 | ||
573 | always @ (negedge clk) begin | |
574 | ||
575 | //pc0_w[47:0] <= {t2_fpga.t2.spc.tlu_pc_0_d[47:2], 2'b00} ; | |
576 | pc0_w[47:0] <= {t2_fpga.t2.spc.tlu.pct0.pc_0_w[47:2], 2'b00} ; | |
577 | last_pc <= pc0_w ; | |
578 | ||
579 | if(last_pc == 48'h000000083400) begin | |
580 | $display ("%t : GOOD TRAP Reached ! " ,$time ,last_pc ); | |
581 | // regreport needs "GOOD End". Do not alter. | |
582 | $display ("%t: dummyClass[]: Diag Reached GOOD End! (pre regreport checking)",$time); | |
583 | $display(""); | |
584 | $display ("%t: dummyClass[]: regreport will determine if diag has really PASSED",$time); | |
585 | $display(""); | |
586 | $display ("%t: dummyClass[]: regreport clock period: 100000 units",$time); | |
587 | $display(""); | |
588 | ||
589 | $finish ; | |
590 | end | |
591 | ||
592 | if(last_pc == 48'h000000083420) begin | |
593 | $display ("%t : BAD TRAP Reached ! ",$time ,last_pc ); | |
594 | $display ("%t: ERROR : Diag Reached BAD End! (pre regreport checking)",$time); | |
595 | $display(""); | |
596 | $display ("%t: ERROR : regreport clock period: 100000 units",$time); | |
597 | $display(""); | |
598 | ||
599 | $finish ; | |
600 | end | |
601 | ||
602 | ||
603 | // Logic to catch timeout | |
604 | ||
605 | if(last_pc != pc0_w) begin | |
606 | timeout_count_en <= 1'b0 ; | |
607 | `ifdef FPGA_MONITOR | |
608 | $display ("%t : PC VALUE is %h ",$time ,pc0_w) ; | |
609 | `endif | |
610 | end | |
611 | ||
612 | if(last_pc == pc0_w) begin | |
613 | timeout_count_en <= 1'b1; | |
614 | end | |
615 | ||
616 | if(timeout_count_en == 1'b1) begin | |
617 | timeout_count <= timeout_count + 1 ; | |
618 | end | |
619 | else if (timeout_count_en == 1'b0) begin | |
620 | timeout_count <= 32'h00000000 ; | |
621 | end | |
622 | ||
623 | if(timeout_count == 32'd100000) begin | |
624 | $display ("%t : ERROR : Time out reached after 100K idle cycles ! " ,$time ) ; | |
625 | $display(""); | |
626 | $display ("%t: ERROR : regreport clock period: 100000 units",$time); | |
627 | $display(""); | |
628 | $finish ; | |
629 | end | |
630 | ||
631 | ||
632 | end // end always | |
633 | ||
634 | ||
635 | // dump enabler | |
636 | ||
637 | `include "dump.v" | |
638 | `endif | |
639 | // synopsys translate_on | |
640 | ||
641 | ||
642 | endmodule | |
643 |