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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu_aux.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module my_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
36 | // RFM 05-14-2004 | |
37 | // Level sensitive in SCAN_MODE | |
38 | // Edge triggered when not in SCAN_MODE | |
39 | ||
40 | parameter SIZE = 1; | |
41 | ||
42 | output q; | |
43 | output so; | |
44 | ||
45 | input d; | |
46 | input l1clk; | |
47 | input si; | |
48 | input siclk; | |
49 | input soclk; | |
50 | input reset; | |
51 | ||
52 | cl_a1_msff_arst_4x lib_inst ( | |
53 | .q( q ), | |
54 | .so( so ), | |
55 | .d( d ), | |
56 | .l1clk( l1clk ), | |
57 | .si( si ), | |
58 | .siclk( siclk ), | |
59 | .soclk( soclk ), | |
60 | .reset ( reset ) | |
61 | ); | |
62 | ||
63 | // reg q; | |
64 | // reg so; | |
65 | // wire l1clk, siclk, soclk; | |
66 | // | |
67 | // reg l1; | |
68 | // | |
69 | // // master latch (tpl) | |
70 | // always @(l1clk or siclk or d or reset or si) begin | |
71 | // if (reset) | |
72 | // l1 = 1'b0; | |
73 | // else if (!l1clk && !siclk) | |
74 | // l1 = d; | |
75 | // else if (l1clk && siclk) | |
76 | // l1 = si; | |
77 | // else if (!l1clk && siclk) | |
78 | // l1 = 1'bx; | |
79 | // end | |
80 | // | |
81 | // // slave latch (tph) | |
82 | // always @(l1clk or soclk or l1 or reset) begin | |
83 | // if (reset) | |
84 | // so = 1'b0; | |
85 | // else if (l1clk && !soclk) | |
86 | // so = l1; | |
87 | // end | |
88 | // | |
89 | // always @(posedge l1clk or posedge reset) begin | |
90 | // if (reset) | |
91 | // q <= 1'b0; | |
92 | // else if (siclk || soclk) | |
93 | // q <= 1'bx; | |
94 | // else | |
95 | // q <= d; | |
96 | // end | |
97 | // | |
98 | // // assign so = q; | |
99 | // | |
100 | endmodule // dff | |
101 | ||
102 | ||
103 | ||
104 | ||
105 | // ******************************************* | |
106 | // 64 flops (async reset) | |
107 | // ******************************************* | |
108 | ||
109 | module ccu_msff_arst_4x_64 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
110 | ||
111 | output [63:0] q; | |
112 | output so; | |
113 | ||
114 | input [63:0] d; | |
115 | input l1clk; | |
116 | input si; | |
117 | input siclk; | |
118 | input soclk; | |
119 | input reset_n; | |
120 | ||
121 | wire [7:0] so_tmp; | |
122 | ||
123 | assign so = so_tmp[7]; | |
124 | ||
125 | ccu_msff_arst_4x_8 U0 ( .q (q[7:0]), .so (so_tmp[0]), .d (d[7:0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
126 | ccu_msff_arst_4x_8 U1 ( .q (q[15:8]), .so (so_tmp[1]), .d (d[15:8]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
127 | ccu_msff_arst_4x_8 U2 ( .q (q[23:16]), .so (so_tmp[2]), .d (d[23:16]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
128 | ccu_msff_arst_4x_8 U3 ( .q (q[31:24]), .so (so_tmp[3]), .d (d[31:24]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
129 | ccu_msff_arst_4x_8 U4 ( .q (q[39:32]), .so (so_tmp[4]), .d (d[39:32]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
130 | ccu_msff_arst_4x_8 U5 ( .q (q[47:40]), .so (so_tmp[5]), .d (d[47:40]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
131 | ccu_msff_arst_4x_8 U6 ( .q (q[55:48]), .so (so_tmp[6]), .d (d[55:48]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
132 | ccu_msff_arst_4x_8 U7 ( .q (q[63:56]), .so (so_tmp[7]), .d (d[63:56]), .l1clk (l1clk), .si (so_tmp[6]), .siclk (siclk), .soclk (soclk), .reset_n (reset_n) ); | |
133 | ||
134 | endmodule | |
135 | ||
136 | // ******************************************* | |
137 | // 8 flops (async reset) | |
138 | // ******************************************* | |
139 | ||
140 | module ccu_msff_arst_4x_8 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
141 | ||
142 | output [7:0] q; | |
143 | output so; | |
144 | ||
145 | input [7:0] d; | |
146 | input l1clk; | |
147 | input si; | |
148 | input siclk; | |
149 | input soclk; | |
150 | input reset_n; | |
151 | ||
152 | wire [7:0] so_tmp; | |
153 | wire reset; | |
154 | ||
155 | assign reset = ~reset_n; | |
156 | assign so = so_tmp[7]; | |
157 | ||
158 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
159 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
160 | my_msff_arst_4x U2 ( .q (q[2]), .so (so_tmp[2]), .d (d[2]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
161 | my_msff_arst_4x U3 ( .q (q[3]), .so (so_tmp[3]), .d (d[3]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
162 | my_msff_arst_4x U4 ( .q (q[4]), .so (so_tmp[4]), .d (d[4]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
163 | my_msff_arst_4x U5 ( .q (q[5]), .so (so_tmp[5]), .d (d[5]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
164 | my_msff_arst_4x U6 ( .q (q[6]), .so (so_tmp[6]), .d (d[6]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
165 | my_msff_arst_4x U7 ( .q (q[7]), .so (so_tmp[7]), .d (d[7]), .l1clk (l1clk), .si (so_tmp[6]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
166 | ||
167 | endmodule | |
168 | ||
169 | // ******************************************* | |
170 | // 64 flops shift-reg | |
171 | // ******************************************* | |
172 | ||
173 | module ccu_msff_arst_4x_64sr ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
174 | ||
175 | output [63:0] q; | |
176 | output so; | |
177 | ||
178 | input d; | |
179 | input l1clk; | |
180 | input si; | |
181 | input siclk; | |
182 | input soclk; | |
183 | input reset_n; | |
184 | ||
185 | wire [63:0] d_tmp; | |
186 | wire [63:0] so_tmp; | |
187 | wire reset; | |
188 | ||
189 | assign reset = ~reset_n; | |
190 | assign so = so_tmp[63]; | |
191 | assign q = d_tmp; | |
192 | ||
193 | my_msff_arst_4x U0 ( .q (d_tmp[0]), .so (so_tmp[0]), .d (d), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
194 | my_msff_arst_4x U1 ( .q (d_tmp[1]), .so (so_tmp[1]), .d (d_tmp[0]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
195 | my_msff_arst_4x U2 ( .q (d_tmp[2]), .so (so_tmp[2]), .d (d_tmp[1]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
196 | my_msff_arst_4x U3 ( .q (d_tmp[3]), .so (so_tmp[3]), .d (d_tmp[2]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
197 | my_msff_arst_4x U4 ( .q (d_tmp[4]), .so (so_tmp[4]), .d (d_tmp[3]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
198 | my_msff_arst_4x U5 ( .q (d_tmp[5]), .so (so_tmp[5]), .d (d_tmp[4]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
199 | my_msff_arst_4x U6 ( .q (d_tmp[6]), .so (so_tmp[6]), .d (d_tmp[5]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
200 | my_msff_arst_4x U7 ( .q (d_tmp[7]), .so (so_tmp[7]), .d (d_tmp[6]), .l1clk (l1clk), .si (so_tmp[6]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
201 | my_msff_arst_4x U8 ( .q (d_tmp[8]), .so (so_tmp[8]), .d (d_tmp[7]), .l1clk (l1clk), .si (so_tmp[7]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
202 | my_msff_arst_4x U9 ( .q (d_tmp[9]), .so (so_tmp[9]), .d (d_tmp[8]), .l1clk (l1clk), .si (so_tmp[8]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
203 | ||
204 | my_msff_arst_4x U10 ( .q (d_tmp[10]), .so (so_tmp[10]), .d (d_tmp[9]), .l1clk (l1clk), .si (so_tmp[9]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
205 | my_msff_arst_4x U11 ( .q (d_tmp[11]), .so (so_tmp[11]), .d (d_tmp[10]), .l1clk (l1clk), .si (so_tmp[10]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
206 | my_msff_arst_4x U12 ( .q (d_tmp[12]), .so (so_tmp[12]), .d (d_tmp[11]), .l1clk (l1clk), .si (so_tmp[11]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
207 | my_msff_arst_4x U13 ( .q (d_tmp[13]), .so (so_tmp[13]), .d (d_tmp[12]), .l1clk (l1clk), .si (so_tmp[12]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
208 | my_msff_arst_4x U14 ( .q (d_tmp[14]), .so (so_tmp[14]), .d (d_tmp[13]), .l1clk (l1clk), .si (so_tmp[13]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
209 | my_msff_arst_4x U15 ( .q (d_tmp[15]), .so (so_tmp[15]), .d (d_tmp[14]), .l1clk (l1clk), .si (so_tmp[14]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
210 | my_msff_arst_4x U16 ( .q (d_tmp[16]), .so (so_tmp[16]), .d (d_tmp[15]), .l1clk (l1clk), .si (so_tmp[15]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
211 | my_msff_arst_4x U17 ( .q (d_tmp[17]), .so (so_tmp[17]), .d (d_tmp[16]), .l1clk (l1clk), .si (so_tmp[16]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
212 | my_msff_arst_4x U18 ( .q (d_tmp[18]), .so (so_tmp[18]), .d (d_tmp[17]), .l1clk (l1clk), .si (so_tmp[17]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
213 | my_msff_arst_4x U19 ( .q (d_tmp[19]), .so (so_tmp[19]), .d (d_tmp[18]), .l1clk (l1clk), .si (so_tmp[18]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
214 | ||
215 | my_msff_arst_4x U20 ( .q (d_tmp[20]), .so (so_tmp[20]), .d (d_tmp[19]), .l1clk (l1clk), .si (so_tmp[19]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
216 | my_msff_arst_4x U21 ( .q (d_tmp[21]), .so (so_tmp[21]), .d (d_tmp[20]), .l1clk (l1clk), .si (so_tmp[20]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
217 | my_msff_arst_4x U22 ( .q (d_tmp[22]), .so (so_tmp[22]), .d (d_tmp[21]), .l1clk (l1clk), .si (so_tmp[21]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
218 | my_msff_arst_4x U23 ( .q (d_tmp[23]), .so (so_tmp[23]), .d (d_tmp[22]), .l1clk (l1clk), .si (so_tmp[22]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
219 | my_msff_arst_4x U24 ( .q (d_tmp[24]), .so (so_tmp[24]), .d (d_tmp[23]), .l1clk (l1clk), .si (so_tmp[23]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
220 | my_msff_arst_4x U25 ( .q (d_tmp[25]), .so (so_tmp[25]), .d (d_tmp[24]), .l1clk (l1clk), .si (so_tmp[24]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
221 | my_msff_arst_4x U26 ( .q (d_tmp[26]), .so (so_tmp[26]), .d (d_tmp[25]), .l1clk (l1clk), .si (so_tmp[25]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
222 | my_msff_arst_4x U27 ( .q (d_tmp[27]), .so (so_tmp[27]), .d (d_tmp[26]), .l1clk (l1clk), .si (so_tmp[26]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
223 | my_msff_arst_4x U28 ( .q (d_tmp[28]), .so (so_tmp[28]), .d (d_tmp[27]), .l1clk (l1clk), .si (so_tmp[27]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
224 | my_msff_arst_4x U29 ( .q (d_tmp[29]), .so (so_tmp[29]), .d (d_tmp[28]), .l1clk (l1clk), .si (so_tmp[28]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
225 | ||
226 | my_msff_arst_4x U30 ( .q (d_tmp[30]), .so (so_tmp[30]), .d (d_tmp[29]), .l1clk (l1clk), .si (so_tmp[29]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
227 | my_msff_arst_4x U31 ( .q (d_tmp[31]), .so (so_tmp[31]), .d (d_tmp[30]), .l1clk (l1clk), .si (so_tmp[30]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
228 | my_msff_arst_4x U32 ( .q (d_tmp[32]), .so (so_tmp[32]), .d (d_tmp[31]), .l1clk (l1clk), .si (so_tmp[31]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
229 | my_msff_arst_4x U33 ( .q (d_tmp[33]), .so (so_tmp[33]), .d (d_tmp[32]), .l1clk (l1clk), .si (so_tmp[32]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
230 | my_msff_arst_4x U34 ( .q (d_tmp[34]), .so (so_tmp[34]), .d (d_tmp[33]), .l1clk (l1clk), .si (so_tmp[33]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
231 | my_msff_arst_4x U35 ( .q (d_tmp[35]), .so (so_tmp[35]), .d (d_tmp[34]), .l1clk (l1clk), .si (so_tmp[34]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
232 | my_msff_arst_4x U36 ( .q (d_tmp[36]), .so (so_tmp[36]), .d (d_tmp[35]), .l1clk (l1clk), .si (so_tmp[35]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
233 | my_msff_arst_4x U37 ( .q (d_tmp[37]), .so (so_tmp[37]), .d (d_tmp[36]), .l1clk (l1clk), .si (so_tmp[36]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
234 | my_msff_arst_4x U38 ( .q (d_tmp[38]), .so (so_tmp[38]), .d (d_tmp[37]), .l1clk (l1clk), .si (so_tmp[37]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
235 | my_msff_arst_4x U39 ( .q (d_tmp[39]), .so (so_tmp[39]), .d (d_tmp[38]), .l1clk (l1clk), .si (so_tmp[38]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
236 | ||
237 | my_msff_arst_4x U40 ( .q (d_tmp[40]), .so (so_tmp[40]), .d (d_tmp[39]), .l1clk (l1clk), .si (so_tmp[39]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
238 | my_msff_arst_4x U41 ( .q (d_tmp[41]), .so (so_tmp[41]), .d (d_tmp[40]), .l1clk (l1clk), .si (so_tmp[40]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
239 | my_msff_arst_4x U42 ( .q (d_tmp[42]), .so (so_tmp[42]), .d (d_tmp[41]), .l1clk (l1clk), .si (so_tmp[41]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
240 | my_msff_arst_4x U43 ( .q (d_tmp[43]), .so (so_tmp[43]), .d (d_tmp[42]), .l1clk (l1clk), .si (so_tmp[42]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
241 | my_msff_arst_4x U44 ( .q (d_tmp[44]), .so (so_tmp[44]), .d (d_tmp[43]), .l1clk (l1clk), .si (so_tmp[43]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
242 | my_msff_arst_4x U45 ( .q (d_tmp[45]), .so (so_tmp[45]), .d (d_tmp[44]), .l1clk (l1clk), .si (so_tmp[44]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
243 | my_msff_arst_4x U46 ( .q (d_tmp[46]), .so (so_tmp[46]), .d (d_tmp[45]), .l1clk (l1clk), .si (so_tmp[45]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
244 | my_msff_arst_4x U47 ( .q (d_tmp[47]), .so (so_tmp[47]), .d (d_tmp[46]), .l1clk (l1clk), .si (so_tmp[46]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
245 | my_msff_arst_4x U48 ( .q (d_tmp[48]), .so (so_tmp[48]), .d (d_tmp[47]), .l1clk (l1clk), .si (so_tmp[47]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
246 | my_msff_arst_4x U49 ( .q (d_tmp[49]), .so (so_tmp[49]), .d (d_tmp[48]), .l1clk (l1clk), .si (so_tmp[48]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
247 | ||
248 | my_msff_arst_4x U50 ( .q (d_tmp[50]), .so (so_tmp[50]), .d (d_tmp[49]), .l1clk (l1clk), .si (so_tmp[49]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
249 | my_msff_arst_4x U51 ( .q (d_tmp[51]), .so (so_tmp[51]), .d (d_tmp[50]), .l1clk (l1clk), .si (so_tmp[50]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
250 | my_msff_arst_4x U52 ( .q (d_tmp[52]), .so (so_tmp[52]), .d (d_tmp[51]), .l1clk (l1clk), .si (so_tmp[51]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
251 | my_msff_arst_4x U53 ( .q (d_tmp[53]), .so (so_tmp[53]), .d (d_tmp[52]), .l1clk (l1clk), .si (so_tmp[52]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
252 | my_msff_arst_4x U54 ( .q (d_tmp[54]), .so (so_tmp[54]), .d (d_tmp[53]), .l1clk (l1clk), .si (so_tmp[53]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
253 | my_msff_arst_4x U55 ( .q (d_tmp[55]), .so (so_tmp[55]), .d (d_tmp[54]), .l1clk (l1clk), .si (so_tmp[54]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
254 | my_msff_arst_4x U56 ( .q (d_tmp[56]), .so (so_tmp[56]), .d (d_tmp[55]), .l1clk (l1clk), .si (so_tmp[55]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
255 | my_msff_arst_4x U57 ( .q (d_tmp[57]), .so (so_tmp[57]), .d (d_tmp[56]), .l1clk (l1clk), .si (so_tmp[56]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
256 | my_msff_arst_4x U58 ( .q (d_tmp[58]), .so (so_tmp[58]), .d (d_tmp[57]), .l1clk (l1clk), .si (so_tmp[57]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
257 | my_msff_arst_4x U59 ( .q (d_tmp[59]), .so (so_tmp[59]), .d (d_tmp[58]), .l1clk (l1clk), .si (so_tmp[58]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
258 | ||
259 | my_msff_arst_4x U60 ( .q (d_tmp[60]), .so (so_tmp[60]), .d (d_tmp[59]), .l1clk (l1clk), .si (so_tmp[59]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
260 | my_msff_arst_4x U61 ( .q (d_tmp[61]), .so (so_tmp[61]), .d (d_tmp[60]), .l1clk (l1clk), .si (so_tmp[60]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
261 | my_msff_arst_4x U62 ( .q (d_tmp[62]), .so (so_tmp[62]), .d (d_tmp[61]), .l1clk (l1clk), .si (so_tmp[61]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
262 | my_msff_arst_4x U63 ( .q (d_tmp[63]), .so (so_tmp[63]), .d (d_tmp[62]), .l1clk (l1clk), .si (so_tmp[62]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
263 | endmodule | |
264 | ||
265 | ||
266 | // ******************************************* | |
267 | // 7 flops (async reset) | |
268 | // ******************************************* | |
269 | ||
270 | module ccu_msff_arst_4x_7 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
271 | ||
272 | output [6:0] q; | |
273 | output so; | |
274 | ||
275 | input [6:0] d; | |
276 | input l1clk; | |
277 | input si; | |
278 | input siclk; | |
279 | input soclk; | |
280 | input reset_n; | |
281 | ||
282 | wire [6:0] so_tmp; | |
283 | wire reset; | |
284 | ||
285 | assign reset = ~reset_n; | |
286 | assign so = so_tmp[6]; | |
287 | ||
288 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
289 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
290 | my_msff_arst_4x U2 ( .q (q[2]), .so (so_tmp[2]), .d (d[2]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
291 | my_msff_arst_4x U3 ( .q (q[3]), .so (so_tmp[3]), .d (d[3]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
292 | my_msff_arst_4x U4 ( .q (q[4]), .so (so_tmp[4]), .d (d[4]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
293 | my_msff_arst_4x U5 ( .q (q[5]), .so (so_tmp[5]), .d (d[5]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
294 | my_msff_arst_4x U6 ( .q (q[6]), .so (so_tmp[6]), .d (d[6]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
295 | ||
296 | endmodule | |
297 | ||
298 | // ******************************************* | |
299 | // 6 flops (async reset) | |
300 | // ******************************************* | |
301 | ||
302 | module ccu_msff_arst_4x_6 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
303 | ||
304 | output [5:0] q; | |
305 | output so; | |
306 | ||
307 | input [5:0] d; | |
308 | input l1clk; | |
309 | input si; | |
310 | input siclk; | |
311 | input soclk; | |
312 | input reset_n; | |
313 | ||
314 | wire [5:0] so_tmp; | |
315 | wire reset; | |
316 | ||
317 | assign reset = ~reset_n; | |
318 | assign so = so_tmp[5]; | |
319 | ||
320 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
321 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
322 | my_msff_arst_4x U2 ( .q (q[2]), .so (so_tmp[2]), .d (d[2]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
323 | my_msff_arst_4x U3 ( .q (q[3]), .so (so_tmp[3]), .d (d[3]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
324 | my_msff_arst_4x U4 ( .q (q[4]), .so (so_tmp[4]), .d (d[4]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
325 | my_msff_arst_4x U5 ( .q (q[5]), .so (so_tmp[5]), .d (d[5]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
326 | ||
327 | endmodule | |
328 | ||
329 | // ******************************************* | |
330 | // 5 flops (async reset) | |
331 | // ******************************************* | |
332 | ||
333 | module ccu_msff_arst_4x_5 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
334 | ||
335 | output [4:0] q; | |
336 | output so; | |
337 | ||
338 | input [4:0] d; | |
339 | input l1clk; | |
340 | input si; | |
341 | input siclk; | |
342 | input soclk; | |
343 | input reset_n; | |
344 | ||
345 | wire reset; | |
346 | ||
347 | assign reset = ~reset_n; | |
348 | ||
349 | my_msff_arst_4x U0 ( .q (q[0]), .so (U0_so), .d (d[0]), .l1clk (l1clk), .si (U0_si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
350 | my_msff_arst_4x U1 ( .q (q[1]), .so (U1_so), .d (d[1]), .l1clk (l1clk), .si (U1_si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
351 | my_msff_arst_4x U2 ( .q (q[2]), .so (U2_so), .d (d[2]), .l1clk (l1clk), .si (U2_si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
352 | my_msff_arst_4x U3 ( .q (q[3]), .so (U3_so), .d (d[3]), .l1clk (l1clk), .si (U3_si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
353 | my_msff_arst_4x U4 ( .q (q[4]), .so (U4_so), .d (d[4]), .l1clk (l1clk), .si (U4_si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
354 | ||
355 | assign U0_si = si; | |
356 | assign U1_si = U0_so; | |
357 | assign U2_si = U1_so; | |
358 | assign U3_si = U2_so; | |
359 | assign U4_si = U3_so; | |
360 | assign so = U4_so; | |
361 | ||
362 | endmodule | |
363 | ||
364 | ||
365 | // ******************************************* | |
366 | // 4 flops (async reset) | |
367 | // ******************************************* | |
368 | ||
369 | module ccu_msff_arst_4x_4 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
370 | output [3:0] q; | |
371 | output so; | |
372 | input [3:0] d; | |
373 | input l1clk; | |
374 | input si; | |
375 | input siclk; | |
376 | input soclk; | |
377 | input reset_n; | |
378 | ||
379 | wire [3:0] so_tmp; | |
380 | wire reset; | |
381 | ||
382 | assign reset = ~reset_n; | |
383 | assign so = so_tmp[3]; | |
384 | ||
385 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
386 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
387 | my_msff_arst_4x U2 ( .q (q[2]), .so (so_tmp[2]), .d (d[2]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
388 | my_msff_arst_4x U3 ( .q (q[3]), .so (so_tmp[3]), .d (d[3]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
389 | ||
390 | endmodule | |
391 | ||
392 | // ******************************************* | |
393 | // 3 flops (async reset) | |
394 | // ******************************************* | |
395 | ||
396 | module ccu_msff_arst_4x_3 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
397 | output [2:0] q; | |
398 | output so; | |
399 | input [2:0] d; | |
400 | input l1clk; | |
401 | input si; | |
402 | input siclk; | |
403 | input soclk; | |
404 | input reset_n; | |
405 | ||
406 | wire [2:0] so_tmp; | |
407 | wire reset; | |
408 | ||
409 | assign reset = ~reset_n; | |
410 | assign so = so_tmp[2]; | |
411 | ||
412 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
413 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
414 | my_msff_arst_4x U2 ( .q (q[2]), .so (so_tmp[2]), .d (d[2]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
415 | ||
416 | endmodule | |
417 | // ******************************************* | |
418 | // 2 flops (async reset) | |
419 | // ******************************************* | |
420 | ||
421 | module ccu_msff_arst_4x_2 ( q, so, d, l1clk, si, siclk, soclk, reset_n ); | |
422 | output [1:0] q; | |
423 | output so; | |
424 | input [1:0] d; | |
425 | input l1clk; | |
426 | input si; | |
427 | input siclk; | |
428 | input soclk; | |
429 | input reset_n; | |
430 | ||
431 | wire [1:0] so_tmp; | |
432 | wire reset; | |
433 | ||
434 | assign reset = ~reset_n; | |
435 | assign so = so_tmp[1]; | |
436 | ||
437 | my_msff_arst_4x U0 ( .q (q[0]), .so (so_tmp[0]), .d (d[0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
438 | my_msff_arst_4x U1 ( .q (q[1]), .so (so_tmp[1]), .d (d[1]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk), .reset (reset) ); | |
439 | ||
440 | endmodule | |
441 | ||
442 | ||
443 | ||
444 | //////////////////////////////////////////////// | |
445 | // | |
446 | // ALL SYNC-RESETTABLE FLOPS | |
447 | // | |
448 | //////////////////////////////////////////////// | |
449 | ||
450 | // ******************************************* | |
451 | // 64 flops | |
452 | // ******************************************* | |
453 | ||
454 | module ccu_msff_syrst_1x_64 ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
455 | ||
456 | output [63:0] q; | |
457 | output so; | |
458 | ||
459 | input [63:0] d; | |
460 | input l1clk; | |
461 | input si; | |
462 | input siclk; | |
463 | input soclk; | |
464 | input reset; | |
465 | ||
466 | wire [1:0] so_tmp; | |
467 | ||
468 | assign so = so_tmp[1]; | |
469 | ||
470 | ccu_msff_syrst_1x_32 U0 ( .reset(reset), .q (q[31:0]), .so (so_tmp[0]), .d (d[31:0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk) ); | |
471 | ccu_msff_syrst_1x_32 U1 ( .reset(reset), .q (q[63:32]), .so (so_tmp[1]), .d (d[63:32]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk) ); | |
472 | ||
473 | endmodule | |
474 | ||
475 | ||
476 | // ******************************************* | |
477 | // 2 flops | |
478 | // ******************************************* | |
479 | ||
480 | module ccu_msff_syrst_1x_2 ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
481 | ||
482 | input reset; | |
483 | output [1:0] q; | |
484 | output so; | |
485 | ||
486 | input [1:0] d; | |
487 | input l1clk; | |
488 | input si; | |
489 | input siclk; | |
490 | input soclk; | |
491 | ||
492 | cl_a1_msff_syrst_1x U0 ( .reset (reset), .q (q[0]), .so (U0_so), .d (d[0]), .l1clk (l1clk), .si (U0_si), .siclk (siclk), .soclk (soclk) ); | |
493 | cl_a1_msff_syrst_1x U1 ( .reset (reset), .q (q[1]), .so (U1_so), .d (d[1]), .l1clk (l1clk), .si (U1_si), .siclk (siclk), .soclk (soclk) ); | |
494 | ||
495 | assign U0_si = si; | |
496 | assign U1_si = U0_so; | |
497 | assign so = U1_so; | |
498 | ||
499 | endmodule | |
500 | ||
501 | ||
502 | // ******************************************* | |
503 | // 4 flops | |
504 | // ******************************************* | |
505 | ||
506 | module ccu_msff_syrst_1x_4 ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
507 | ||
508 | output [3:0] q; | |
509 | output so; | |
510 | ||
511 | input reset; | |
512 | input [3:0] d; | |
513 | input l1clk; | |
514 | input si; | |
515 | input siclk; | |
516 | input soclk; | |
517 | ||
518 | ccu_msff_syrst_1x_2 U0 ( .reset (reset), .q (q[1:0]), .so (U0_so), .d (d[1:0]), .l1clk (l1clk), .si (U0_si), .siclk (siclk), .soclk (soclk) ); | |
519 | ccu_msff_syrst_1x_2 U1 ( .reset (reset), .q (q[3:2]), .so (U1_so), .d (d[3:2]), .l1clk (l1clk), .si (U1_si), .siclk (siclk), .soclk (soclk) ); | |
520 | ||
521 | assign U0_si = si; | |
522 | assign U1_si = U0_so; | |
523 | assign so = U1_so; | |
524 | ||
525 | endmodule | |
526 | ||
527 | // ******************************************* | |
528 | // 128 flops | |
529 | // ******************************************* | |
530 | ||
531 | module ccu_msff_syrst_1x_128 ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
532 | ||
533 | output [127:0] q; | |
534 | output so; | |
535 | ||
536 | input reset; | |
537 | input [127:0] d; | |
538 | input l1clk; | |
539 | input si; | |
540 | input siclk; | |
541 | input soclk; | |
542 | ||
543 | ccu_msff_syrst_1x_64 U0 ( .reset (reset), .q (q[63:0]), .so (U0_so), .d (d[63:0]), .l1clk (l1clk), .si (U0_si), .siclk (siclk), .soclk (soclk) ); | |
544 | ccu_msff_syrst_1x_64 U1 ( .reset (reset), .q (q[127:64]), .so (U1_so), .d (d[127:64]), .l1clk (l1clk), .si (U1_si), .siclk (siclk), .soclk (soclk) ); | |
545 | ||
546 | assign U0_si = si; | |
547 | assign U1_si = U0_so; | |
548 | assign so = U1_so; | |
549 | ||
550 | endmodule | |
551 | ||
552 | // ******************************************* | |
553 | // 32 flops | |
554 | // ******************************************* | |
555 | ||
556 | module ccu_msff_syrst_1x_32 ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
557 | ||
558 | output [31:0] q; | |
559 | output so; | |
560 | ||
561 | input reset; | |
562 | input [31:0] d; | |
563 | input l1clk; | |
564 | input si; | |
565 | input siclk; | |
566 | input soclk; | |
567 | ||
568 | wire [6:0] so_tmp; | |
569 | ||
570 | ccu_msff_syrst_1x_4 U0 ( .reset(reset), .q (q[3:0]), .so (so_tmp[0]), .d (d[3:0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk) ); | |
571 | ccu_msff_syrst_1x_4 U1 ( .reset(reset), .q (q[7:4]), .so (so_tmp[1]), .d (d[7:4]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk) ); | |
572 | ccu_msff_syrst_1x_4 U2 ( .reset(reset), .q (q[11:8]), .so (so_tmp[2]), .d (d[11:8]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk) ); | |
573 | ccu_msff_syrst_1x_4 U3 ( .reset(reset), .q (q[15:12]), .so (so_tmp[3]), .d (d[15:12]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk) ); | |
574 | ccu_msff_syrst_1x_4 U4 ( .reset(reset), .q (q[19:16]), .so (so_tmp[4]), .d (d[19:16]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk) ); | |
575 | ccu_msff_syrst_1x_4 U5 ( .reset(reset), .q (q[23:20]), .so (so_tmp[5]), .d (d[23:20]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk) ); | |
576 | ccu_msff_syrst_1x_4 U6 ( .reset(reset), .q (q[27:24]), .so (so_tmp[6]), .d (d[27:24]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk) ); | |
577 | ccu_msff_syrst_1x_4 U7 ( .reset(reset), .q (q[31:28]), .so (so ), .d (d[31:28]), .l1clk (l1clk), .si (so_tmp[6]), .siclk (siclk), .soclk (soclk) ); | |
578 | ||
579 | endmodule | |
580 | ||
581 | // ******************************************* | |
582 | // 117 flops | |
583 | // ******************************************* | |
584 | ||
585 | module ccu_msff_syrst_1x_117 ( reset, q, so, d, l1clk, si, siclk, soclk ); | |
586 | ||
587 | output [116:0] q; | |
588 | output so; | |
589 | ||
590 | input reset; | |
591 | input [116:0] d; | |
592 | input l1clk; | |
593 | input si; | |
594 | input siclk; | |
595 | input soclk; | |
596 | ||
597 | wire [5:0] so_tmp; | |
598 | ||
599 | ccu_msff_syrst_1x_64 U0 ( .reset(reset), .q (q[63:0]), .so (so_tmp[0]), .d (d[63:0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk) ); | |
600 | ccu_msff_syrst_1x_32 U1 ( .reset(reset), .q (q[95:64]), .so (so_tmp[1]), .d (d[95:64]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk) ); | |
601 | ccu_msff_syrst_1x_6 U2 ( .reset(reset), .q (q[101:96]), .so (so_tmp[2]), .d (d[101:96]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk) ); | |
602 | ccu_msff_syrst_1x_6 U3 ( .reset(reset), .q (q[107:102]), .so (so_tmp[3]), .d (d[107:102]), .l1clk (l1clk), .si (so_tmp[2]), .siclk (siclk), .soclk (soclk) ); | |
603 | ccu_msff_syrst_1x_4 U4 ( .reset(reset), .q (q[111:108]), .so (so_tmp[4]), .d (d[111:108]), .l1clk (l1clk), .si (so_tmp[3]), .siclk (siclk), .soclk (soclk) ); | |
604 | ccu_msff_syrst_1x_4 U5 ( .reset(reset), .q (q[115:112]), .so (so_tmp[5]), .d (d[115:112]), .l1clk (l1clk), .si (so_tmp[4]), .siclk (siclk), .soclk (soclk) ); | |
605 | cl_a1_msff_syrst_1x U6 ( .reset(reset), .q (q[116:116]), .so (so ), .d (d[116:116]), .l1clk (l1clk), .si (so_tmp[5]), .siclk (siclk), .soclk (soclk) ); | |
606 | ||
607 | endmodule | |
608 | // ******************************************* | |
609 | // 6 flops | |
610 | // ******************************************* | |
611 | ||
612 | module ccu_msff_syrst_1x_6 ( reset, q, so, d, l1clk, si, siclk, soclk); | |
613 | ||
614 | output [5:0] q; | |
615 | output so; | |
616 | input reset; | |
617 | input [5:0] d; | |
618 | input l1clk; | |
619 | input si; | |
620 | input siclk; | |
621 | input soclk; | |
622 | ||
623 | cl_a1_msff_syrst_1x U0 ( .reset (reset), .q (q[0]), .so (U0_so), .d (d[0]), .l1clk (l1clk), .si (U0_si), .siclk (siclk), .soclk (soclk) ); | |
624 | cl_a1_msff_syrst_1x U1 ( .reset (reset), .q (q[1]), .so (U1_so), .d (d[1]), .l1clk (l1clk), .si (U1_si), .siclk (siclk), .soclk (soclk) ); | |
625 | cl_a1_msff_syrst_1x U2 ( .reset (reset), .q (q[2]), .so (U2_so), .d (d[2]), .l1clk (l1clk), .si (U2_si), .siclk (siclk), .soclk (soclk) ); | |
626 | cl_a1_msff_syrst_1x U3 ( .reset (reset), .q (q[3]), .so (U3_so), .d (d[3]), .l1clk (l1clk), .si (U3_si), .siclk (siclk), .soclk (soclk) ); | |
627 | cl_a1_msff_syrst_1x U4 ( .reset (reset), .q (q[4]), .so (U4_so), .d (d[4]), .l1clk (l1clk), .si (U4_si), .siclk (siclk), .soclk (soclk) ); | |
628 | cl_a1_msff_syrst_1x U5 ( .reset (reset), .q (q[5]), .so (U5_so), .d (d[5]), .l1clk (l1clk), .si (U5_si), .siclk (siclk), .soclk (soclk) ); | |
629 | ||
630 | assign U0_si = si; | |
631 | assign U1_si = U0_so; | |
632 | assign U2_si = U1_so; | |
633 | assign U3_si = U2_so; | |
634 | assign U4_si = U3_so; | |
635 | assign U5_si = U4_so; | |
636 | assign so = U5_so; | |
637 | ||
638 | endmodule | |
639 | ||
640 | // ******************************************* | |
641 | // 76 flops | |
642 | // ******************************************* | |
643 | ||
644 | module ccu_msff_syrst_1x_76 ( reset, q, so, d, l1clk, si, siclk, soclk ); | |
645 | ||
646 | output [75:0] q; | |
647 | output so; | |
648 | ||
649 | input reset; | |
650 | input [75:0] d; | |
651 | input l1clk; | |
652 | input si; | |
653 | input siclk; | |
654 | input soclk; | |
655 | ||
656 | wire [1:0] so_tmp; | |
657 | ||
658 | ccu_msff_syrst_1x_64 U0 ( .reset(reset), .q (q[63:0]), .so (so_tmp[0]), .d (d[63:0]), .l1clk (l1clk), .si (si), .siclk (siclk), .soclk (soclk) ); | |
659 | ccu_msff_syrst_1x_6 U1 ( .reset(reset), .q (q[69:64]), .so (so_tmp[1]), .d (d[69:64]), .l1clk (l1clk), .si (so_tmp[0]), .siclk (siclk), .soclk (soclk) ); | |
660 | ccu_msff_syrst_1x_6 U2 ( .reset(reset), .q (q[75:70]), .so (so), .d (d[75:70]), .l1clk (l1clk), .si (so_tmp[1]), .siclk (siclk), .soclk (soclk) ); | |
661 | ||
662 | endmodule | |
663 | ||
664 | ||
665 | ||
666 | ||
667 | //////////////////////////////////////////////// | |
668 | // | |
669 | // ONLY LATCHES FOLLOW | |
670 | // | |
671 | //////////////////////////////////////////////// | |
672 | ||
673 | ||
674 | // ******************************************* | |
675 | // 1 latch | |
676 | // ******************************************* | |
677 | module ccu_blatch_4x_1 (latout, so, d, l1clk, si, siclk, soclk); | |
678 | ||
679 | output latout; | |
680 | output so; | |
681 | input d; | |
682 | input l1clk; | |
683 | input si; | |
684 | input siclk; | |
685 | input soclk; | |
686 | ||
687 | ||
688 | cl_a1_blatch_4x U0 ( .latout(latout), .so(so), .d(d), .l1clk(l1clk), .si(si), .siclk(siclk), .soclk(soclk) ); | |
689 | ||
690 | ||
691 | endmodule // ccu_blatch_4x_1 | |
692 | ||
693 | ||
694 | // ******************************************* | |
695 | // 6 latches | |
696 | // ******************************************* | |
697 | module ccu_blatch_4x_6 (latout, so, d, l1clk, si, siclk, soclk); | |
698 | ||
699 | output [5:0] latout; | |
700 | output so; | |
701 | input [5:0] d; | |
702 | input l1clk; | |
703 | input si; | |
704 | input siclk; | |
705 | input soclk; | |
706 | ||
707 | wire [5:0] so_tmp; | |
708 | ||
709 | assign so = so_tmp[5]; | |
710 | ||
711 | ||
712 | cl_a1_blatch_4x U0 ( .latout(latout[0]), .l1clk (l1clk), .d (d[0]), | |
713 | .so(so_tmp[0]), .si (si), .siclk(siclk), .soclk(soclk) ); | |
714 | cl_a1_blatch_4x U1 ( .latout(latout[1]), .l1clk (l1clk), .d (d[1]), | |
715 | .so(so_tmp[1]), .si (so_tmp[0]), .siclk(siclk), .soclk(soclk) ); | |
716 | cl_a1_blatch_4x U2 ( .latout(latout[2]), .l1clk (l1clk), .d (d[2]), | |
717 | .so(so_tmp[2]), .si (so_tmp[1]), .siclk(siclk), .soclk(soclk) ); | |
718 | cl_a1_blatch_4x U3 ( .latout(latout[3]), .l1clk (l1clk), .d (d[3]), | |
719 | .so(so_tmp[3]), .si (so_tmp[2]), .siclk(siclk), .soclk(soclk) ); | |
720 | cl_a1_blatch_4x U4 ( .latout(latout[4]), .l1clk (l1clk), .d (d[4]), | |
721 | .so(so_tmp[4]), .si (so_tmp[3]), .siclk(siclk), .soclk(soclk) ); | |
722 | cl_a1_blatch_4x U5 ( .latout(latout[5]), .l1clk (l1clk), .d (d[5]), | |
723 | .so(so_tmp[5]), .si (so_tmp[4]), .siclk(siclk), .soclk(soclk) ); | |
724 | ||
725 | endmodule // ccu_blatch_4x_6 | |
726 | ||
727 | ||
728 | ||
729 |