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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu_divider.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
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29 | // | |
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31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ccu_divider ( | |
36 | rst_n, | |
37 | div, | |
38 | clkin, | |
39 | clkout, | |
40 | phase_180 | |
41 | ); | |
42 | ||
43 | input rst_n; | |
44 | input [4:0] div; | |
45 | input clkin; | |
46 | output clkout; | |
47 | output phase_180; | |
48 | ||
49 | wire rst_n; | |
50 | wire [4:0] div; | |
51 | wire clkin; | |
52 | wire clkout; // ECO | |
53 | wire pre_phase_180; | |
54 | wire phase_180; | |
55 | ||
56 | // wire clkout_tmp; // ECO | |
57 | wire odd; | |
58 | wire [4:0] cnt; | |
59 | wire [3:0] div_by2; | |
60 | wire flip; | |
61 | ||
62 | wire reset; | |
63 | ||
64 | reg clkout_d_; // ECO | |
65 | wire clkout_q_; // ECO | |
66 | ||
67 | assign div_by2 = div[4:1]; | |
68 | assign odd = div[0]; | |
69 | ||
70 | reg [4:0] cnt_in; | |
71 | reg flip_in,pre_phase_180_in; | |
72 | always @ (cnt or div_by2 or div ) begin | |
73 | if (cnt == div_by2) begin | |
74 | cnt_in = cnt + 5'b1; | |
75 | flip_in = 1'b1; | |
76 | pre_phase_180_in = 1'b1; | |
77 | end else if (cnt == div) begin | |
78 | cnt_in = 5'h00; | |
79 | flip_in = 1'b1; | |
80 | pre_phase_180_in = 1'b0; | |
81 | end else begin | |
82 | cnt_in = cnt + 5'b1; | |
83 | flip_in = 1'b0; | |
84 | pre_phase_180_in = 1'b0; | |
85 | end | |
86 | end | |
87 | ||
88 | assign reset = ~rst_n; | |
89 | ||
90 | ccu_msff_arst_4x_5 cnt_bank5 ( | |
91 | .q(cnt), | |
92 | .so(), | |
93 | .d(cnt_in), | |
94 | .l1clk(clkin), | |
95 | .si(1'b0), | |
96 | .siclk(1'b0), | |
97 | .soclk(1'b0), | |
98 | .reset_n(rst_n) | |
99 | ); | |
100 | ||
101 | ||
102 | my_msff_arst_4x flip_0 ( .q(flip), .so(), .d(flip_in), .l1clk(clkin), | |
103 | .si(1'b0), .siclk(1'b0), .soclk(1'b0), .reset(reset) ); | |
104 | ||
105 | my_msff_arst_4x pre_phase_180_0 ( .q(pre_phase_180), .so(), .d(pre_phase_180_in), .l1clk(clkin), | |
106 | .si(1'b0), .siclk(1'b0), .soclk(1'b0), .reset(reset) ); | |
107 | ||
108 | ||
109 | ||
110 | // flip => output is inverted else maintain state | |
111 | ||
112 | wire clkout_tmp_in; | |
113 | wire clkout_tmp_; | |
114 | ||
115 | // assign clkout_tmp_in = flip ? clkout_tmp : ~clkout_tmp; | |
116 | assign clkout_tmp_in = flip ^ clkout_tmp_; // ECO | |
117 | ||
118 | my_msff_arst_4x clkout_tmp_0 ( | |
119 | // .q(clkout_tmp_), .so(), .d(clkout_tmp_in), .l1clk(clkin), | |
120 | .q(clkout_q_), .so(), .d(clkout_d_), .l1clk(clkin), // ECO | |
121 | .si(1'b0), .siclk(1'b0), .soclk(1'b0), .reset(reset) ); | |
122 | ||
123 | // assign clkout_tmp = ~clkout_tmp_; // ECO | |
124 | ||
125 | // just pipe one stage | |
126 | wire phase_180_in; | |
127 | wire phase_180_; | |
128 | ||
129 | assign phase_180_in = ~pre_phase_180; | |
130 | ||
131 | my_msff_arst_4x phase_180_0 ( | |
132 | .q(phase_180_), .so(), .d(phase_180_in), .l1clk(clkin), | |
133 | .si(1'b0), .siclk(1'b0), .soclk(1'b0), .reset(reset) ); | |
134 | ||
135 | assign phase_180 = ~phase_180_; | |
136 | ||
137 | ||
138 | // ------------------------------------------------------------ | |
139 | // Quick & dirty fix to shift clocks generated by N-8 cycles | |
140 | // when N is (effective) 11 or 15 for DTM | |
141 | // ------------------------------------------------------------ | |
142 | ||
143 | wire [6:0] clk_shift_; | |
144 | wire [6:0] clk_shift; | |
145 | ||
146 | assign clk_shift = ~clk_shift_ ; | |
147 | ||
148 | ccu_msff_arst_4x_7 shift_bank_7 ( | |
149 | .q(clk_shift_[6:0]), | |
150 | .so (), | |
151 | .d({clk_shift_[5:0], clkout_tmp_in}) , // ECO .d({clk_shift_[5:0], clkout_tmp_}) , | |
152 | .l1clk (clkin), | |
153 | .si (1'b0), | |
154 | .siclk (1'b0), | |
155 | .soclk (1'b0), | |
156 | .reset_n (rst_n) | |
157 | ); | |
158 | ||
159 | ||
160 | // dtm shift not needed for div eff == 8; only for 11 & 15 | |
161 | wire dtm_mode = ((div == 5'h0A) || (div == 5'h0E)); | |
162 | ||
163 | assign clkout = ~clkout_q_; // ECO | |
164 | assign clkout_tmp_ = dtm_mode ? clk_shift_[0] : clkout_q_ ; // ECO | |
165 | ||
166 | always @(div or clkout_tmp_in or clk_shift_) begin // ECO @(div or clkout_tmp or clk_shift) | |
167 | case (div) | |
168 | 5'h0A: clkout_d_ = clk_shift_[2]; // 11 => shift 3 cycles // ECO | |
169 | 5'h0E: clkout_d_ = clk_shift_[6]; // 15 => shift 7 cycles // ECO | |
170 | default: clkout_d_ = clkout_tmp_in; // else no shift // ECO | |
171 | endcase | |
172 | end | |
173 | ||
174 | // end of quick fix | |
175 | // ------------------------------------------------------------ | |
176 | ||
177 | endmodule | |
178 | ||
179 | ||
180 |