Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / ccu / rtl / ccu_hm_align_det.v

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// OpenSPARC T2 Processor File: ccu_hm_align_det.v
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`timescale 1 ns / 1ps

module ccu_hm_align_det (
	ref_clk,
	fast_clk,
	rst_n,
 	aligned
);


input ref_clk;
input fast_clk;
input rst_n;
output aligned; 

wire ref_clk;
wire fast_clk;
wire rst_n;
wire aligned; 


// inferred flops 
/*
reg ref_q1_n;
reg ref_q2_n;
reg ref_q3;
reg ref_q4;
reg ref_q5;
*/

wire ref_q1_n;
wire ref_q2_n;
wire ref_q3;
wire ref_q4;
wire ref_q5;

wire rst;
wire fast_clk_n;
wire ref_q5_in;


// inferred flops 
/*
always @ (negedge fast_clk or negedge rst_n) begin
	if (!rst_n) begin
		ref_q1_n <=  1'b0; 
		ref_q2_n <=  1'b0;
	end else begin
		ref_q1_n <= ref_clk;
		ref_q2_n <= ref_q1_n;
	end 
end
*/

// BEGIN_ECO
// POST TAPEOUT ECO - N2 BUG ....
wire ref_clk_n;
wire rst_n_synced;

assign ref_clk_n = ~ref_clk;
cl_a1_clksyncff_4x bf_arst_sync (
	.l1clk (ref_clk_n), .d (rst_n), .q (rst_n_synced),
	.siclk( 1'b0 ), .soclk( 1'b0 ), .si (1'b0), .so ()
);	
assign rst = ~(rst_n_synced & rst_n);	
// END_ECO

assign fast_clk_n = ~fast_clk; 

my_msff_arst_4x stg1_n (
	.l1clk (fast_clk_n),
	.reset (rst),
	.d (ref_clk),
	.q (ref_q1_n),
	.siclk (1'b0),
	.soclk (1'b0),
	.si (1'b0),
	.so ()
);

my_msff_arst_4x stg2_n (
	.l1clk (fast_clk_n),
	.reset (rst),
	.d (ref_q1_n),
	.q (ref_q2_n),
	.siclk (1'b0),
	.soclk (1'b0),
	.si (1'b0),
	.so ()
);



/*
always @ (posedge fast_clk or negedge rst_n) begin
	if (!rst_n) begin 
		ref_q3 <= 1'b0; 
		ref_q4 <= 1'b0; 
		ref_q5 <= 1'b0; 
	end else begin	// one half-cycle path
		ref_q3 <= ref_q2_n;
		ref_q4 <= ref_q3;
		ref_q5 <= ~ref_q4 & ref_q3; 
	end
end
*/

my_msff_arst_4x stg3 (
	.l1clk (fast_clk),
	.reset (rst),
	.d (ref_q2_n),
	.q (ref_q3),
	.siclk (1'b0),
	.soclk (1'b0),
	.si (1'b0),
	.so ()
);

my_msff_arst_4x stg4 (
	.l1clk (fast_clk),
	.reset (rst),
	.d (ref_q3),
	.q (ref_q4),
	.siclk (1'b0),
	.soclk (1'b0),
	.si (1'b0),
	.so ()
);


assign ref_q5_in = ~ref_q4 & ref_q3;

/* 
my_msff_arst_4x stg5 (
	.l1clk (fast_clk),
	.reset (rst),
	.d (ref_q5_in),
	.q (ref_q5),
	.siclk (1'b0),
	.soclk (1'b0),
	.si (1'b0),
	.so ()
);
*/

assign aligned = ref_q5_in;



endmodule