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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu_hm_dr_reset_gen.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ccu_hm_dr_reset_gen ( | |
36 | rst_out_n, | |
37 | clk, | |
38 | shift_amt, | |
39 | aligned, | |
40 | div_msb, | |
41 | rst_n | |
42 | ); | |
43 | ||
44 | output rst_out_n; | |
45 | input clk; | |
46 | input [4:0] shift_amt; | |
47 | input aligned; | |
48 | input div_msb; | |
49 | input rst_n; | |
50 | ||
51 | wire rst_out_n; | |
52 | wire clk; | |
53 | wire [4:0] shift_amt; | |
54 | wire aligned; | |
55 | wire div_msb; | |
56 | wire [1:0] align_shift; | |
57 | wire rst_n; | |
58 | ||
59 | wire pulse_rst_n; | |
60 | wire pulse_rst1_n; // eco 1.1 - mh157021 | |
61 | wire pulse_rst2_n; // eco 1.2 - mh157021 | |
62 | wire pulse_rst1_n_in; // eco 1.3 - mh157021 | |
63 | wire rst; | |
64 | reg dr_rst_n; | |
65 | wire dr_rst_n_q; | |
66 | ||
67 | ||
68 | ||
69 | assign rst = ~rst_n; | |
70 | ||
71 | assign rst_out_n = (div_msb) ? dr_rst_n : dr_rst_n_q ; | |
72 | ||
73 | always @(posedge clk) begin // later convert to async reset | |
74 | if (!rst_n) | |
75 | dr_rst_n <= 1'b0; | |
76 | else begin | |
77 | if (pulse_rst2_n) // eco 1.4 - mh157021 - wire change from pulse_rst_n | |
78 | dr_rst_n <= 1'b1; | |
79 | else | |
80 | dr_rst_n <= dr_rst_n; | |
81 | end | |
82 | end | |
83 | ||
84 | my_msff_arst_4x dr_rst_n_ff ( | |
85 | .q(dr_rst_n_q), | |
86 | .so(), | |
87 | .d(dr_rst_n), | |
88 | .l1clk(clk), | |
89 | .si(1'b0), | |
90 | .siclk(1'b0), | |
91 | .soclk(1'b0), | |
92 | .reset(rst) | |
93 | ); | |
94 | ||
95 | ||
96 | my_msff_arst_4x pulse_wait ( // eco 1.5 - mh157021 | |
97 | .q(pulse_rst1_n), | |
98 | .so(), | |
99 | .d(pulse_rst1_n_in), | |
100 | .l1clk(clk), | |
101 | .si(1'b0), | |
102 | .siclk(1'b0), | |
103 | .soclk(1'b0), | |
104 | .reset(rst) | |
105 | ); | |
106 | ||
107 | assign pulse_rst1_n_in = pulse_rst1_n | pulse_rst_n; // eco 1.6 - mh157021 - feedback | |
108 | assign pulse_rst2_n = pulse_rst1_n & pulse_rst_n; // eco 1.7 - mh157021 - 2nd pulse goes thru | |
109 | ||
110 | ||
111 | // *********************************************** | |
112 | // shift dr reset +4 cycle to reference edge | |
113 | // *********************************************** | |
114 | ||
115 | ccu_hm_pulse_shift dr_reset_shift ( | |
116 | .rst_n (rst_n), | |
117 | .clk (clk), | |
118 | .shift (shift_amt), | |
119 | .pulse_in (aligned), | |
120 | .pulse_out (pulse_rst_n) | |
121 | ); | |
122 | ||
123 | endmodule | |
124 |