Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / ccx_new_macro.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ccx_new_macro.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module ccx_new_macro_ccx_new_macro (
36 l2clk,
37 l1clk,
38 pce0,
39 pce1,
40 pce_ov,
41 se,
42 stop,
43 siclk_in,
44 soclk_in,
45 scan_in,
46 grant_a,
47 qsel0,
48 shift,
49 data_a,
50 data_x_l,
51 scan_out);
52wire so5;
53wire siclk_out;
54wire soclk_out;
55wire l1clk0;
56wire l1clk1;
57wire grant_x;
58wire qsel0_buf;
59wire shift_buf;
60
61input l2clk;
62input l1clk;
63input pce0;
64input pce1;
65input pce_ov;
66input se;
67input stop;
68input siclk_in;
69input soclk_in;
70input scan_in;
71input grant_a;
72input qsel0;
73input shift;
74input [9:0] data_a;
75output [9:0] data_x_l;
76output scan_out;
77cl_dp1_ccxhdr c0 (
78.si(scan_in),
79.so(so5),
80 .l2clk(l2clk),
81 .pce0(pce0),
82 .pce1(pce1),
83 .pce_ov(pce_ov),
84 .stop(stop),
85 .siclk_in(siclk_in),
86 .soclk_in(soclk_in),
87 .siclk_out(siclk_out),
88 .soclk_out(soclk_out),
89 .l1clk0(l1clk0),
90 .l1clk1(l1clk1),
91 .se(se),
92 .l1clk(l1clk),
93 .grant_a(grant_a),
94 .grant_x(grant_x),
95 .qsel0(qsel0),
96 .qsel0_buf(qsel0_buf),
97 .shift(shift),
98 .shift_buf(shift_buf)
99);
100
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105
106ccx_mac_a #(10) mac_a(
107.siclk(siclk_out),
108.soclk(soclk_out),
109.data_a(data_a[9:0]),
110.data_x_l(data_x_l[9:0]),
111.si(so5),
112.so(scan_out),
113 .l1clk0(l1clk0),
114 .l1clk1(l1clk1),
115 .grant_x(grant_x),
116 .qsel0_buf(qsel0_buf),
117 .shift_buf(shift_buf)
118);
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132
133endmodule
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