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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cpx_bfg_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifndef FPGA | |
36 | module cpx_bfg_dp ( | |
37 | cpx_sctag_grant_cx, | |
38 | cpx_sctag_grant_ca, | |
39 | tcu_scan_en, | |
40 | l2clk, | |
41 | scan_in, | |
42 | tcu_pce_ov, | |
43 | ccx_aclk, | |
44 | ccx_bclk, | |
45 | scan_out, | |
46 | ccx_aclk_out, | |
47 | ccx_bclk_out, | |
48 | tcu_pce_ov_out, | |
49 | tcu_scan_en_out); | |
50 | wire pce_ov; | |
51 | wire stop; | |
52 | wire siclk; | |
53 | wire soclk; | |
54 | wire se; | |
55 | wire i_dff_grant_x_scanin; | |
56 | wire i_dff_grant_x_scanout; | |
57 | wire [7:0] cpx_sctag_grant_x; | |
58 | wire scan_out_prebuf; | |
59 | ||
60 | ||
61 | output [7:0] cpx_sctag_grant_cx; | |
62 | ||
63 | input [7:0] cpx_sctag_grant_ca; | |
64 | ||
65 | //globals | |
66 | input tcu_scan_en ; | |
67 | input l2clk; | |
68 | input scan_in; | |
69 | input tcu_pce_ov; // scan signals | |
70 | input ccx_aclk; | |
71 | input ccx_bclk; | |
72 | output scan_out; | |
73 | ||
74 | // buffer the high fanout nets | |
75 | output ccx_aclk_out; | |
76 | output ccx_bclk_out; | |
77 | output tcu_pce_ov_out; | |
78 | output tcu_scan_en_out; | |
79 | ||
80 | // scan renames | |
81 | assign pce_ov = tcu_pce_ov_out; | |
82 | assign stop = 1'b0; | |
83 | assign siclk = ccx_aclk_out; | |
84 | assign soclk = ccx_bclk_out; | |
85 | assign se = tcu_scan_en_out ; | |
86 | // end scan | |
87 | ||
88 | cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn ( | |
89 | .din ({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}), | |
90 | .dout ({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out}) | |
91 | ); | |
92 | ||
93 | ||
94 | cpx_bfg_dp_msff_macro__stack_8r__width_8 i_dff_grant_x ( | |
95 | .scan_in(i_dff_grant_x_scanin), | |
96 | .scan_out(i_dff_grant_x_scanout), | |
97 | .clk (l2clk), | |
98 | .din (cpx_sctag_grant_ca[7:0]), | |
99 | .dout (cpx_sctag_grant_x[7:0]), | |
100 | .en (1'b1), | |
101 | .se(se), | |
102 | .siclk(siclk), | |
103 | .soclk(soclk), | |
104 | .pce_ov(pce_ov), | |
105 | .stop(stop) | |
106 | ); | |
107 | ||
108 | cpx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_grant_x ( | |
109 | .din (cpx_sctag_grant_x[7:0]), | |
110 | .dout (cpx_sctag_grant_cx[7:0]) | |
111 | ); | |
112 | ||
113 | cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout ( | |
114 | .din (scan_out_prebuf), | |
115 | .dout (scan_out) | |
116 | ); | |
117 | ||
118 | // fixscan start: | |
119 | assign i_dff_grant_x_scanin = scan_in ; | |
120 | assign scan_out_prebuf = i_dff_grant_x_scanout ; | |
121 | // fixscan end: | |
122 | endmodule // cpx_bfs_dp | |
123 | ||
124 | ||
125 | // | |
126 | // buff macro | |
127 | // | |
128 | // | |
129 | ||
130 | ||
131 | ||
132 | ||
133 | ||
134 | module cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 ( | |
135 | din, | |
136 | dout); | |
137 | input [3:0] din; | |
138 | output [3:0] dout; | |
139 | ||
140 | ||
141 | ||
142 | ||
143 | ||
144 | ||
145 | buff #(4) d0_0 ( | |
146 | .in(din[3:0]), | |
147 | .out(dout[3:0]) | |
148 | ); | |
149 | ||
150 | ||
151 | ||
152 | ||
153 | ||
154 | ||
155 | ||
156 | ||
157 | endmodule | |
158 | ||
159 | ||
160 | ||
161 | ||
162 | ||
163 | ||
164 | ||
165 | ||
166 | ||
167 | // any PARAMS parms go into naming of macro | |
168 | ||
169 | module cpx_bfg_dp_msff_macro__stack_8r__width_8 ( | |
170 | din, | |
171 | clk, | |
172 | en, | |
173 | se, | |
174 | scan_in, | |
175 | siclk, | |
176 | soclk, | |
177 | pce_ov, | |
178 | stop, | |
179 | dout, | |
180 | scan_out); | |
181 | wire l1clk; | |
182 | wire siclk_out; | |
183 | wire soclk_out; | |
184 | wire [6:0] so; | |
185 | ||
186 | input [7:0] din; | |
187 | ||
188 | ||
189 | input clk; | |
190 | input en; | |
191 | input se; | |
192 | input scan_in; | |
193 | input siclk; | |
194 | input soclk; | |
195 | input pce_ov; | |
196 | input stop; | |
197 | ||
198 | ||
199 | ||
200 | output [7:0] dout; | |
201 | ||
202 | ||
203 | output scan_out; | |
204 | ||
205 | ||
206 | ||
207 | ||
208 | cl_dp1_l1hdr_8x c0_0 ( | |
209 | .l2clk(clk), | |
210 | .pce(en), | |
211 | .aclk(siclk), | |
212 | .bclk(soclk), | |
213 | .l1clk(l1clk), | |
214 | .se(se), | |
215 | .pce_ov(pce_ov), | |
216 | .stop(stop), | |
217 | .siclk_out(siclk_out), | |
218 | .soclk_out(soclk_out) | |
219 | ); | |
220 | dff #(8) d0_0 ( | |
221 | .l1clk(l1clk), | |
222 | .siclk(siclk_out), | |
223 | .soclk(soclk_out), | |
224 | .d(din[7:0]), | |
225 | .si({scan_in,so[6:0]}), | |
226 | .so({so[6:0],scan_out}), | |
227 | .q(dout[7:0]) | |
228 | ); | |
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | ||
238 | ||
239 | ||
240 | ||
241 | ||
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | endmodule | |
250 | ||
251 | ||
252 | ||
253 | ||
254 | ||
255 | ||
256 | ||
257 | ||
258 | ||
259 | // | |
260 | // buff macro | |
261 | // | |
262 | // | |
263 | ||
264 | ||
265 | ||
266 | ||
267 | ||
268 | module cpx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 ( | |
269 | din, | |
270 | dout); | |
271 | input [7:0] din; | |
272 | output [7:0] dout; | |
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | buff #(8) d0_0 ( | |
280 | .in(din[7:0]), | |
281 | .out(dout[7:0]) | |
282 | ); | |
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | endmodule | |
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | // | |
298 | // buff macro | |
299 | // | |
300 | // | |
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | module cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 ( | |
307 | din, | |
308 | dout); | |
309 | input [0:0] din; | |
310 | output [0:0] dout; | |
311 | ||
312 | ||
313 | ||
314 | ||
315 | ||
316 | ||
317 | buff #(1) d0_0 ( | |
318 | .in(din[0:0]), | |
319 | .out(dout[0:0]) | |
320 | ); | |
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | endmodule | |
330 | ||
331 | ||
332 | ||
333 | `endif // `ifndef FPGA | |
334 | ||
335 | `ifdef FPGA | |
336 | ||
337 | `timescale 1 ns / 100 ps | |
338 | module cpx_bfg_dp(cpx_sctag_grant_cx, cpx_sctag_grant_ca, tcu_scan_en, l2clk, | |
339 | scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, | |
340 | ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out); | |
341 | ||
342 | output [7:0] cpx_sctag_grant_cx; | |
343 | input [7:0] cpx_sctag_grant_ca; | |
344 | input tcu_scan_en; | |
345 | input l2clk; | |
346 | input scan_in; | |
347 | input tcu_pce_ov; | |
348 | input ccx_aclk; | |
349 | input ccx_bclk; | |
350 | output scan_out; | |
351 | output ccx_aclk_out; | |
352 | output ccx_bclk_out; | |
353 | output tcu_pce_ov_out; | |
354 | output tcu_scan_en_out; | |
355 | ||
356 | wire pce_ov; | |
357 | wire stop; | |
358 | wire siclk; | |
359 | wire soclk; | |
360 | wire se; | |
361 | wire i_dff_grant_x_scanin; | |
362 | wire i_dff_grant_x_scanout; | |
363 | wire [7:0] cpx_sctag_grant_x; | |
364 | wire scan_out_prebuf; | |
365 | ||
366 | assign pce_ov = tcu_pce_ov_out; | |
367 | assign stop = 1'b0; | |
368 | assign siclk = ccx_aclk_out; | |
369 | assign soclk = ccx_bclk_out; | |
370 | assign se = tcu_scan_en_out; | |
371 | assign i_dff_grant_x_scanin = scan_in; | |
372 | assign scan_out_prebuf = i_dff_grant_x_scanout; | |
373 | ||
374 | buff_macro__dbuff_8x__stack_none__width_4 buf_hfn( | |
375 | .din ({ccx_aclk, ccx_bclk, | |
376 | tcu_pce_ov, tcu_scan_en}), | |
377 | .dout ({ccx_aclk_out, ccx_bclk_out, | |
378 | tcu_pce_ov_out, tcu_scan_en_out})); | |
379 | msff_macro__stack_8r__width_8 i_dff_grant_x( | |
380 | .scan_in (i_dff_grant_x_scanin), | |
381 | .scan_out (i_dff_grant_x_scanout), | |
382 | .clk (l2clk), | |
383 | .din (cpx_sctag_grant_ca[7:0]), | |
384 | .dout (cpx_sctag_grant_x[7:0]), | |
385 | .en (1'b1), | |
386 | .se (se), | |
387 | .siclk (siclk), | |
388 | .soclk (soclk), | |
389 | .pce_ov (pce_ov), | |
390 | .stop (stop)); | |
391 | buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_grant_x( | |
392 | .din (cpx_sctag_grant_x[7:0]), | |
393 | .dout (cpx_sctag_grant_cx[7:0])); | |
394 | buff_macro__dbuff_8x__stack_none__width_1 buf_scanout( | |
395 | .din (scan_out_prebuf), | |
396 | .dout (scan_out)); | |
397 | endmodule | |
398 | ||
399 | ||
400 | module msff_macro__stack_8r__width_8(din, clk, en, se, scan_in, siclk, soclk, | |
401 | pce_ov, stop, dout, scan_out); | |
402 | ||
403 | input [7:0] din; | |
404 | input clk; | |
405 | input en; | |
406 | input se; | |
407 | input scan_in; | |
408 | input siclk; | |
409 | input soclk; | |
410 | input pce_ov; | |
411 | input stop; | |
412 | output [7:0] dout; | |
413 | output scan_out; | |
414 | ||
415 | wire l1clk; | |
416 | wire siclk_out; | |
417 | wire soclk_out; | |
418 | wire [6:0] so; | |
419 | ||
420 | cl_dp1_l1hdr_8x c0_0( | |
421 | .l2clk (clk), | |
422 | .pce (en), | |
423 | .aclk (siclk), | |
424 | .bclk (soclk), | |
425 | .l1clk (l1clk), | |
426 | .se (se), | |
427 | .pce_ov (pce_ov), | |
428 | .stop (stop), | |
429 | .siclk_out (siclk_out), | |
430 | .soclk_out (soclk_out)); | |
431 | dff #(8) d0_0( | |
432 | .l1clk (l1clk), | |
433 | .siclk (siclk_out), | |
434 | .soclk (soclk_out), | |
435 | .d (din[7:0]), | |
436 | .si ({scan_in, so[6:0]}), | |
437 | .so ({so[6:0], scan_out}), | |
438 | .q (dout[7:0])); | |
439 | endmodule | |
440 | ||
441 | `ifdef FPGA | |
442 | `else | |
443 | `celldefine | |
444 | module buff_macro__dbuff_8x__stack_none__width_1(din, dout); | |
445 | ||
446 | input [0:0] din; | |
447 | output [0:0] dout; | |
448 | ||
449 | buff #(1) d0_0( | |
450 | .in (din[0]), | |
451 | .out (dout[0])); | |
452 | endmodule | |
453 | `endcelldefine | |
454 | ||
455 | `celldefine | |
456 | module buff_macro__dbuff_8x__stack_none__width_1(din, dout); | |
457 | ||
458 | input [0:0] din; | |
459 | output [0:0] dout; | |
460 | ||
461 | buff #(1) d0_0( | |
462 | .in (din[0]), | |
463 | .out (dout[0])); | |
464 | endmodule | |
465 | `endcelldefine | |
466 | ||
467 | `endif // `ifdef FPGA | |
468 | ||
469 | ||
470 | ||
471 | `endif // `ifdef FPGA | |
472 |