Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / cpx_dpsc.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cpx_dpsc.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
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10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifndef FPGA
36module cpx_dpsc (
37 cpx_spc_data_x_,
38 arb_grant_l_a,
39 arb_q0_holdbar_l_a,
40 arb_qsel0_l_a,
41 arb_qsel1_l_a,
42 arb_shift_l_a,
43 arb_grant_r_a,
44 arb_q0_holdbar_r_a,
45 arb_qsel0_r_a,
46 arb_qsel1_r_a,
47 arb_shift_r_a,
48 io_cpx_data_a,
49 scache0_cpx_data_a,
50 scache1_cpx_data_a,
51 scache2_cpx_data_a,
52 scache3_cpx_data_a,
53 scache4_cpx_data_a,
54 scache5_cpx_data_a,
55 scache6_cpx_data_a,
56 scache7_cpx_data_a,
57 tcu_scan_en,
58 l2clk,
59 scan_in,
60 tcu_pce_ov,
61 ccx_aclk,
62 ccx_bclk,
63 scan_out);
64wire [4:0] mac0_rep_in;
65wire [3:0] arb_grant_l_a_rep;
66wire [3:0] arb_qsel0_l_a_rep;
67wire [3:0] arb_qsel1_l_a_rep;
68wire [3:0] arb_shift_l_a_rep;
69wire [3:0] arb_q0_holdbar_l_a_rep;
70wire [4:0] mac0_rep_out;
71wire [4:0] mac1_rep_in;
72wire [4:0] mac1_rep_out;
73wire [4:0] mac2_rep_in;
74wire [4:0] mac2_rep_out;
75wire [4:0] mac3_rep_in;
76wire [4:0] mac3_rep_out;
77wire [4:0] mac4_rep_in;
78wire [7:5] arb_grant_r_a_rep;
79wire [7:5] arb_q0_holdbar_r_a_rep;
80wire [7:5] arb_qsel0_r_a_rep;
81wire [7:5] arb_qsel1_r_a_rep;
82wire [7:5] arb_shift_r_a_rep;
83wire [4:0] mac4_rep_out;
84wire [4:0] mac5_rep_in;
85wire [4:0] mac5_rep_out;
86wire [4:0] mac6_rep_in;
87wire [4:0] mac6_rep_out;
88wire scan_rep_in;
89wire [149:0] col8_data_x_;
90wire tcu_scan_en_out_8_unused;
91wire tcu_pce_ov_out_8_unused;
92wire ccx_aclk_out_8_unused;
93wire ccx_bclk_out_8_unused;
94wire cpx_mac8_scanin;
95wire cpx_mac8_scanout;
96wire [6:0] tcu_scan_en_out;
97wire [6:0] tcu_pce_ov_out;
98wire [6:0] ccx_aclk_out;
99wire [6:0] ccx_bclk_out;
100wire [149:0] col0_data_x_;
101wire cpx_mac0_scanin;
102wire cpx_mac0_scanout;
103wire [149:0] col1_data_x_;
104wire cpx_mac1_scanin;
105wire cpx_mac1_scanout;
106wire [149:0] col3_data_x_;
107wire cpx_mac2_scanin;
108wire cpx_mac2_scanout;
109wire [149:0] col4_data_x_;
110wire cpx_mac3_scanin;
111wire cpx_mac3_scanout;
112wire [149:0] col5_data_x_;
113wire cpx_mac4_scanin;
114wire cpx_mac4_scanout;
115wire [149:0] col6_data_x_;
116wire cpx_mac5_scanin;
117wire cpx_mac5_scanout;
118wire [149:0] col7_data_x_;
119wire cpx_mac6_scanin;
120wire cpx_mac6_scanout;
121wire tcu_scan_en_out_7_unused;
122wire tcu_pce_ov_out_7_unused;
123wire ccx_aclk_out_7_unused;
124wire ccx_bclk_out_7_unused;
125wire cpx_mac7_scanin;
126wire cpx_mac7_scanout;
127wire [7:4] arb_grant_l_a_unused;
128wire [7:4] arb_q0_holdbar_l_a_unused;
129wire [7:4] arb_qsel0_l_a_unused;
130wire [7:4] arb_qsel1_l_a_unused;
131wire [7:4] arb_shift_l_a_unused;
132wire [8:0] arb_grant_r_a_unused;
133wire [8:0] arb_q0_holdbar_r_a_unused;
134wire [8:0] arb_qsel0_r_a_unused;
135wire [8:0] arb_qsel1_r_a_unused;
136wire [8:0] arb_shift_r_a_unused;
137wire scan_rep_out;
138
139
140
141// Beginning of automatic outputs (from unused autoinst outputs)
142output [149:0] cpx_spc_data_x_; // From mac4 of cpx_mcr_dp.v
143// End of automatics
144
145// Beginning of automatic inputs (from unused autoinst inputs)
146input [8:0] arb_grant_l_a; // To mac0 of cpx_mar_dp.v, ...
147input [8:0] arb_q0_holdbar_l_a; // To mac0 of cpx_mar_dp.v, ...
148input [8:0] arb_qsel0_l_a; // To mac0 of cpx_mar_dp.v, ...
149input [8:0] arb_qsel1_l_a; // To mac0 of cpx_mar_dp.v, ...
150input [8:0] arb_shift_l_a; // To mac0 of cpx_mar_dp.v, ...
151input [8:0] arb_grant_r_a; // To mac0 of cpx_mar_dp.v, ...
152input [8:0] arb_q0_holdbar_r_a; // To mac0 of cpx_mar_dp.v, ...
153input [8:0] arb_qsel0_r_a; // To mac0 of cpx_mar_dp.v, ...
154input [8:0] arb_qsel1_r_a; // To mac0 of cpx_mar_dp.v, ...
155input [8:0] arb_shift_r_a; // To mac0 of cpx_mar_dp.v, ...
156input [149:0] io_cpx_data_a; // To mac8 of cpx_mal_dp.v
157input [149:0] scache0_cpx_data_a; // To mac0 of cpx_mar_dp.v
158input [149:0] scache1_cpx_data_a; // To mac1 of cpx_mbr_dp.v
159input [149:0] scache2_cpx_data_a; // To mac2 of cpx_mbr_dp.v
160input [149:0] scache3_cpx_data_a; // To mac3 of cpx_mbr_dp.v
161input [149:0] scache4_cpx_data_a; // To mac4 of cpx_mcr_dp.v
162input [149:0] scache5_cpx_data_a; // To mac5 of cpx_mbl_dp.v
163input [149:0] scache6_cpx_data_a; // To mac6 of cpx_mbl_dp.v
164input [149:0] scache7_cpx_data_a; // To cpx_mac7 of cpx_mbl_dp.v
165// End of automatics
166
167// globals
168input tcu_scan_en ;
169input l2clk;
170input scan_in;
171input tcu_pce_ov; // scan signals
172input ccx_aclk;
173input ccx_bclk;
174output scan_out;
175
176
177// io scache2 scache0 scache3 scache1 scache7 scache5 scache6 scache4
178// | | | | | | | | |
179// v v v v v v v v v
180// mac8-> mac0 -> mac1 <-mac2 <- mac3 <- mac4 <- mac5 <- mac6 <- mac7
181// al bl bl cl br br br br bl
182// |
183// ---buf-------------------
184// |
185// v
186// to spccore
187
188// mac0 arb inputs go through 1 buffer
189assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
190 arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};
191
192assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
193 arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
194
195// mac1 arb input go through 1 buffer
196assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
197 arb_qsel1_l_a[0],arb_shift_l_a[0]};
198
199assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
200 arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];
201
202// mac2 arb inputs go through 2 buffers
203assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
204 arb_qsel1_l_a[3],arb_shift_l_a[3]};
205
206assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
207 arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];
208
209// mac3 inputs go through 2 buffers
210assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
211 arb_qsel1_l_a[1],arb_shift_l_a[1]};
212
213assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
214 arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];
215
216// mac4 inputs go through 2 buffers
217assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
218 arb_qsel1_r_a[7],arb_shift_r_a[7]};
219
220assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
221 arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];
222
223// mac5 inputs go through 1 buffer
224assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
225 arb_qsel1_r_a[5],arb_shift_r_a[5]};
226
227assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
228 arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];
229
230// mac6 inputs go through 1 buffer
231assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
232 arb_qsel1_r_a[6],arb_shift_r_a[6]};
233
234assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
235 arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];
236
237assign scan_rep_in = scan_in;
238
239
240
241cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
242 .mac1_rep_out(mac1_rep_out[4:0]),
243 .mac2_rep_out(mac2_rep_out[4:0]),
244 .mac3_rep_out(mac3_rep_out[4:0]),
245 .mac4_rep_out(mac4_rep_out[4:0]),
246 .mac5_rep_out(mac5_rep_out[4:0]),
247 .mac6_rep_out(mac6_rep_out[4:0]),
248 .scan_rep_out(scan_rep_out),
249 .mac0_rep_in(mac0_rep_in[4:0]),
250 .mac1_rep_in(mac1_rep_in[4:0]),
251 .mac2_rep_in(mac2_rep_in[4:0]),
252 .mac3_rep_in(mac3_rep_in[4:0]),
253 .mac4_rep_in(mac4_rep_in[4:0]),
254 .mac5_rep_in(mac5_rep_in[4:0]),
255 .mac6_rep_in(mac6_rep_in[4:0]),
256 .scan_rep_in(scan_rep_in)
257 );
258
259/*
260 cpx_mal_dp AUTO_TEMPLATE
261 (
262 // Outputs
263 .data_out_x_ (col@_data_x_[149:0]),
264 // Inputs
265 .arb_grant_a(arb_grant_l_a[@]),
266 .arb_qsel0_a(arb_qsel0_l_a[@]),
267 .arb_qsel1_a(arb_qsel1_l_a[@]),
268 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
269 .arb_shift_a(arb_shift_l_a[@]),
270 .src_cpx_data_a(io_cpx_data_a[149:0]),
271 .l2clk (l2clk));
272*/
273
274// do not use autoinstancing.
275// connections have been modified to match the cpu floorplan
276// src_pcx_data_a has to be manually connected.
277
278// input from io
279cpx_mal_dp cpx_mac8 (
280 // Outputs
281 .data_out_x_ (col8_data_x_[149:0]), // Templated
282 .tcu_scan_en_out (tcu_scan_en_out_8_unused),
283 .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
284 .ccx_aclk_out (ccx_aclk_out_8_unused),
285 .ccx_bclk_out (ccx_bclk_out_8_unused),
286 // Inputs
287 .arb_grant_a (arb_grant_l_a[8]), // Templated
288 .arb_qsel0_a (arb_qsel0_l_a[8]), // Templated
289 .arb_qsel1_a (arb_qsel1_l_a[8]), // Templated
290 .arb_q0_holdbar_a (arb_q0_holdbar_l_a[8]), // Templated
291 .arb_shift_a (arb_shift_l_a[8]), // Templated
292 .src_cpx_data_a (io_cpx_data_a[149:0]), // Templated
293 .scan_in(cpx_mac8_scanin),
294 .scan_out(cpx_mac8_scanout),
295 .l2clk (l2clk), // Templated
296 .tcu_scan_en (tcu_scan_en_out[0]),
297 .tcu_pce_ov (tcu_pce_ov_out[0]),
298 .ccx_aclk (ccx_aclk_out[0]),
299 .ccx_bclk (ccx_bclk_out[0])
300 );
301
302
303/*
304 cpx_mbl_dp AUTO_TEMPLATE
305 (
306 // Outputs
307 .data_out_x_ (col@_data_x_[149:0]),
308 // Inputs
309 .arb_grant_a(arb_grant_l_a[@]),
310 .arb_qsel0_a(arb_qsel0_l_a[@]),
311 .arb_qsel1_a(arb_qsel1_l_a[@]),
312 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
313 .arb_shift_a(arb_shift_l_a[@]),
314 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
315 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
316 .l2clk (l2clk));
317*/
318
319
320// input from sctag2
321cpx_mbl_dp cpx_mac0 (
322 // Outputs
323 .data_out_x_ (col0_data_x_[149:0]),
324 .tcu_scan_en_out (tcu_scan_en_out[0]),
325 .tcu_pce_ov_out (tcu_pce_ov_out[0]),
326 .ccx_aclk_out (ccx_aclk_out[0]),
327 .ccx_bclk_out (ccx_bclk_out[0]),
328 // Inputs
329 .arb_grant_a (arb_grant_l_a_rep[2]),
330 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
331 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
332 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
333 .arb_shift_a (arb_shift_l_a_rep[2]),
334 .src_cpx_data_a (scache2_cpx_data_a[149:0]),
335 .data_prev_x_ (col8_data_x_[149:0]),
336 .scan_in(cpx_mac0_scanin),
337 .scan_out(cpx_mac0_scanout),
338 .l2clk (l2clk),
339 .tcu_scan_en (tcu_scan_en_out[1]),
340 .tcu_pce_ov (tcu_pce_ov_out[1]),
341 .ccx_aclk (ccx_aclk_out[1]),
342 .ccx_bclk (ccx_bclk_out[1])
343 );
344
345
346// input from sctag0
347cpx_mbl_dp cpx_mac1 (
348 // Outputs
349 .data_out_x_ (col1_data_x_[149:0]),
350 .tcu_scan_en_out (tcu_scan_en_out[1]),
351 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
352 .ccx_aclk_out (ccx_aclk_out[1]),
353 .ccx_bclk_out (ccx_bclk_out[1]),
354 // Inputs
355 .arb_grant_a (arb_grant_l_a_rep[0]),
356 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
357 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
358 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
359 .arb_shift_a (arb_shift_l_a_rep[0]),
360 .src_cpx_data_a (scache0_cpx_data_a[149:0]),
361 .data_prev_x_ (col0_data_x_[149:0]),
362 .scan_in(cpx_mac1_scanin),
363 .scan_out(cpx_mac1_scanout),
364 .l2clk (l2clk),
365 .tcu_scan_en (tcu_scan_en_out[2]),
366 .tcu_pce_ov (tcu_pce_ov_out[2]),
367 .ccx_aclk (ccx_aclk_out[2]),
368 .ccx_bclk (ccx_bclk_out[2])
369 );
370
371
372/*
373 cpx_mcl_dp AUTO_TEMPLATE
374 (
375 // Outputs
376 .data_out_x_ (cpx_spc_data_x_[149:0]),
377 // Inputs
378 .arb_grant_a(arb_grant_l_a[@]),
379 .arb_qsel0_a(arb_qsel0_l_a[@]),
380 .arb_qsel1_a(arb_qsel1_l_a[@]),
381 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
382 .arb_shift_a(arb_shift_l_a[@]),
383 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
384 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
385 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
386 .l2clk (l2clk));
387*/
388
389// input from sctag3
390cpx_mcl_dp cpx_mac2 (
391 // Outputs
392 .data_out_x_ (cpx_spc_data_x_[149:0]), // Templated
393 .tcu_scan_en_out (tcu_scan_en_out[2]),
394 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
395 .ccx_aclk_out (ccx_aclk_out[2]),
396 .ccx_bclk_out (ccx_bclk_out[2]),
397 // Inputs
398 .arb_grant_a (arb_grant_l_a_rep[3]), // Templated
399 .arb_qsel0_a (arb_qsel0_l_a_rep[3]), // Templated
400 .arb_qsel1_a (arb_qsel1_l_a_rep[3]), // Templated
401 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]), // Templated
402 .arb_shift_a (arb_shift_l_a_rep[3]), // Templated
403 .src_cpx_data_a (scache3_cpx_data_a[149:0]), // Templated
404 .data_crit_x_ (col3_data_x_[149:0]), // Templated
405 .data_ncrit_x_ (col1_data_x_[149:0]), // Templated
406 .scan_in(cpx_mac2_scanin),
407 .scan_out(cpx_mac2_scanout),
408 .l2clk (l2clk), // Templated
409 .tcu_scan_en (tcu_scan_en_out[3]),
410 .tcu_pce_ov (tcu_pce_ov_out[3]),
411 .ccx_aclk (ccx_aclk_out[3]),
412 .ccx_bclk (ccx_bclk_out[3])
413 );
414
415
416/*
417 cpx_mbr_dp AUTO_TEMPLATE
418 (
419 // Outputs
420 .data_out_x_ (col@_data_x_[149:0]),
421 // Inputs
422 .arb_grant_a(arb_grant_l_a[@]),
423 .arb_qsel0_a(arb_qsel0_l_a[@]),
424 .arb_qsel1_a(arb_qsel1_l_a[@]),
425 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
426 .arb_shift_a(arb_shift_l_a[@]),
427 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
428 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
429 .l2clk (l2clk));
430*/
431
432
433// input from sctag1
434cpx_mbr_dp cpx_mac3 (
435 // Outputs
436 .data_out_x_ (col3_data_x_[149:0]), // Templated
437 .tcu_scan_en_out (tcu_scan_en_out[3]),
438 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
439 .ccx_aclk_out (ccx_aclk_out[3]),
440 .ccx_bclk_out (ccx_bclk_out[3]),
441 // Inputs
442 .arb_grant_a (arb_grant_l_a_rep[1]), // Templated
443 .arb_qsel0_a (arb_qsel0_l_a_rep[1]), // Templated
444 .arb_qsel1_a (arb_qsel1_l_a_rep[1]), // Templated
445 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]), // Templated
446 .arb_shift_a (arb_shift_l_a_rep[1]), // Templated
447 .src_cpx_data_a (scache1_cpx_data_a[149:0]), // Templated
448 .data_prev_x_ (col4_data_x_[149:0]), // Templated
449 .scan_in(cpx_mac3_scanin),
450 .scan_out(cpx_mac3_scanout),
451 .l2clk (l2clk), // Templated
452 .tcu_scan_en (tcu_scan_en),
453 .tcu_pce_ov (tcu_pce_ov),
454 .ccx_aclk (ccx_aclk),
455 .ccx_bclk (ccx_bclk)
456 );
457
458
459// input from sctag7
460cpx_mbr_dp cpx_mac4 (
461 // Outputs
462 .data_out_x_ (col4_data_x_[149:0]), // Templated
463 .tcu_scan_en_out (tcu_scan_en_out[4]),
464 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
465 .ccx_aclk_out (ccx_aclk_out[4]),
466 .ccx_bclk_out (ccx_bclk_out[4]),
467 // Inputs
468 .arb_grant_a (arb_grant_r_a_rep[7]), // Templated
469 .arb_qsel0_a (arb_qsel0_r_a_rep[7]), // Templated
470 .arb_qsel1_a (arb_qsel1_r_a_rep[7]), // Templated
471 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]), // Templated
472 .arb_shift_a (arb_shift_r_a_rep[7]), // Templated
473 .src_cpx_data_a (scache7_cpx_data_a[149:0]), // Templated
474 .data_prev_x_ (col5_data_x_[149:0]), // Templated
475 .scan_in(cpx_mac4_scanin),
476 .scan_out(cpx_mac4_scanout),
477 .l2clk (l2clk), // Templated
478 .tcu_scan_en (tcu_scan_en_out[3]),
479 .tcu_pce_ov (tcu_pce_ov_out[3]),
480 .ccx_aclk (ccx_aclk_out[3]),
481 .ccx_bclk (ccx_bclk_out[3])
482 );
483
484
485// input from sctag5
486cpx_mbr_dp cpx_mac5 (
487 // Outputs
488 .data_out_x_ (col5_data_x_[149:0]), // Templated
489 .tcu_scan_en_out (tcu_scan_en_out[5]),
490 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
491 .ccx_aclk_out (ccx_aclk_out[5]),
492 .ccx_bclk_out (ccx_bclk_out[5]),
493 // Inputs
494 .arb_grant_a (arb_grant_r_a_rep[5]), // Templated
495 .arb_qsel0_a (arb_qsel0_r_a_rep[5]), // Templated
496 .arb_qsel1_a (arb_qsel1_r_a_rep[5]), // Templated
497 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]), // Templated
498 .arb_shift_a (arb_shift_r_a_rep[5]), // Templated
499 .src_cpx_data_a (scache5_cpx_data_a[149:0]), // Templated
500 .data_prev_x_ (col6_data_x_[149:0]), // Templated
501 .scan_in(cpx_mac5_scanin),
502 .scan_out(cpx_mac5_scanout),
503 .l2clk (l2clk), // Templated
504 .tcu_scan_en (tcu_scan_en_out[4]),
505 .tcu_pce_ov (tcu_pce_ov_out[4]),
506 .ccx_aclk (ccx_aclk_out[4]),
507 .ccx_bclk (ccx_bclk_out[4])
508 );
509
510// input from sctag6
511cpx_mbr_dp cpx_mac6 (
512 // Outputs
513 .data_out_x_ (col6_data_x_[149:0]), // Templated
514 .tcu_scan_en_out (tcu_scan_en_out[6]),
515 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
516 .ccx_aclk_out (ccx_aclk_out[6]),
517 .ccx_bclk_out (ccx_bclk_out[6]),
518 // Inputs
519 .arb_grant_a (arb_grant_r_a_rep[6]), // Templated
520 .arb_qsel0_a (arb_qsel0_r_a_rep[6]), // Templated
521 .arb_qsel1_a (arb_qsel1_r_a_rep[6]), // Templated
522 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[6]), // Templated
523 .arb_shift_a (arb_shift_r_a_rep[6]), // Templated
524 .src_cpx_data_a (scache6_cpx_data_a[149:0]), // Templated
525 .data_prev_x_ (col7_data_x_[149:0]), // Templated
526 .scan_in(cpx_mac6_scanin),
527 .scan_out(cpx_mac6_scanout),
528 .l2clk (l2clk), // Templated
529 .tcu_scan_en (tcu_scan_en_out[5]),
530 .tcu_pce_ov (tcu_pce_ov_out[5]),
531 .ccx_aclk (ccx_aclk_out[5]),
532 .ccx_bclk (ccx_bclk_out[5])
533 );
534
535/*
536 cpx_mar_dp AUTO_TEMPLATE
537 (
538 // Outputs
539 .data_out_x_ (col@_data_x_[149:0]),
540 // Inputs
541 .arb_grant_a(arb_grant_r_a[@]),
542 .arb_qsel0_a(arb_qsel0_r_a[@]),
543 .arb_qsel1_a(arb_qsel1_r_a[@]),
544 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
545 .arb_shift_a(arb_shift_r_a[@]),
546 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
547 .l2clk (l2clk));
548*/
549
550// input from sctag4
551cpx_mar_dp cpx_mac7 (
552 // Outputs
553 .data_out_x_ (col7_data_x_[149:0]), // Templated
554 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
555 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
556 .ccx_aclk_out (ccx_aclk_out_7_unused),
557 .ccx_bclk_out (ccx_bclk_out_7_unused),
558 // Inputs
559 .arb_grant_a (arb_grant_r_a[4]), // Templated
560 .arb_qsel0_a (arb_qsel0_r_a[4]), // Templated
561 .arb_qsel1_a (arb_qsel1_r_a[4]), // Templated
562 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[4]), // Templated
563 .arb_shift_a (arb_shift_r_a[4]), // Templated
564 .src_cpx_data_a (scache4_cpx_data_a[149:0]), // Templated
565 .scan_in(cpx_mac7_scanin),
566 .scan_out(cpx_mac7_scanout),
567 .l2clk (l2clk), // Templated
568 .tcu_scan_en (tcu_scan_en_out[6]),
569 .tcu_pce_ov (tcu_pce_ov_out[6]),
570 .ccx_aclk (ccx_aclk_out[6]),
571 .ccx_bclk (ccx_bclk_out[6])
572 );
573
574
575
576assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
577assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
578assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
579assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
580assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
581
582assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
583assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
584assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
585assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
586assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
587
588assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
589assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
590assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
591assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
592assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
593
594// fixscan start:
595assign cpx_mac8_scanin = scan_rep_out ;
596assign cpx_mac0_scanin = cpx_mac8_scanout ;
597assign cpx_mac1_scanin = cpx_mac0_scanout ;
598assign cpx_mac2_scanin = cpx_mac1_scanout ;
599assign cpx_mac3_scanin = cpx_mac2_scanout ;
600assign cpx_mac4_scanin = cpx_mac3_scanout ;
601assign cpx_mac5_scanin = cpx_mac4_scanout ;
602assign cpx_mac6_scanin = cpx_mac5_scanout ;
603assign cpx_mac7_scanin = cpx_mac6_scanout ;
604assign scan_out = cpx_mac7_scanout ;
605// fixscan end:
606endmodule
607
608// Local Variables:
609// verilog-library-directories:("." "v")
610// End:
611
612
613
614
615//
616// buff macro
617//
618//
619
620
621
622
623
624module cpx_dpsc_buff_macro__dbuff_32x__stack_6l__width_5 (
625 din,
626 dout);
627 input [4:0] din;
628 output [4:0] dout;
629
630
631
632
633
634
635buff #(5) d0_0 (
636.in(din[4:0]),
637.out(dout[4:0])
638);
639
640
641
642
643
644
645
646
647endmodule
648
649
650
651
652
653//
654// buff macro
655//
656//
657
658
659
660
661
662module cpx_dpsc_buff_macro__dbuff_32x__stack_none__width_1 (
663 din,
664 dout);
665 input [0:0] din;
666 output [0:0] dout;
667
668
669
670
671
672
673buff #(1) d0_0 (
674.in(din[0:0]),
675.out(dout[0:0])
676);
677
678
679
680
681
682
683
684
685endmodule
686
687
688
689
690//
691// buff macro
692//
693//
694
695
696
697
698
699module cpx_dpsc_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
700 din,
701 dout);
702 input [3:0] din;
703 output [3:0] dout;
704
705
706
707
708
709
710buff #(4) d0_0 (
711.in(din[3:0]),
712.out(dout[3:0])
713);
714
715
716
717
718
719
720
721
722endmodule
723
724
725
726
727
728
729
730
731
732// any PARAMS parms go into naming of macro
733
734module cpx_dpsc_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
735 l2clk,
736 l1en,
737 pce_ov,
738 stop,
739 se,
740 l1clk);
741
742
743 input l2clk;
744 input l1en;
745 input pce_ov;
746 input stop;
747 input se;
748 output l1clk;
749
750
751
752
753
754cl_sc1_l1hdr_24x c_0 (
755
756
757 .l2clk(l2clk),
758 .pce(l1en),
759 .l1clk(l1clk),
760 .se(se),
761 .pce_ov(pce_ov),
762 .stop(stop)
763);
764
765
766
767
768
769
770endmodule
771
772
773
774
775
776
777
778
779
780//
781// ccx macro
782//
783//
784
785
786
787
788
789module cpx_dpsc_ccx_new_macro__type_a (
790 l2clk,
791 l1clk,
792 pce0,
793 pce1,
794 pce_ov,
795 se,
796 stop,
797 siclk_in,
798 soclk_in,
799 scan_in,
800 grant_a,
801 qsel0,
802 shift,
803 data_a,
804 data_x_l,
805 scan_out);
806wire so5;
807wire siclk_out;
808wire soclk_out;
809wire l1clk0;
810wire l1clk1;
811wire grant_x;
812wire qsel0_buf;
813wire shift_buf;
814
815input l2clk;
816input l1clk;
817input pce0;
818input pce1;
819input pce_ov;
820input se;
821input stop;
822input siclk_in;
823input soclk_in;
824input scan_in;
825input grant_a;
826input qsel0;
827input shift;
828input [9:0] data_a;
829output [9:0] data_x_l;
830output scan_out;
831cl_dp1_ccxhdr c0 (
832.si(scan_in),
833.so(so5),
834 .l2clk(l2clk),
835 .pce0(pce0),
836 .pce1(pce1),
837 .pce_ov(pce_ov),
838 .stop(stop),
839 .siclk_in(siclk_in),
840 .soclk_in(soclk_in),
841 .siclk_out(siclk_out),
842 .soclk_out(soclk_out),
843 .l1clk0(l1clk0),
844 .l1clk1(l1clk1),
845 .se(se),
846 .l1clk(l1clk),
847 .grant_a(grant_a),
848 .grant_x(grant_x),
849 .qsel0(qsel0),
850 .qsel0_buf(qsel0_buf),
851 .shift(shift),
852 .shift_buf(shift_buf)
853);
854
855
856
857
858
859
860ccx_mac_a #(10) mac_a(
861.siclk(siclk_out),
862.soclk(soclk_out),
863.data_a(data_a[9:0]),
864.data_x_l(data_x_l[9:0]),
865.si(so5),
866.so(scan_out),
867 .l1clk0(l1clk0),
868 .l1clk1(l1clk1),
869 .grant_x(grant_x),
870 .qsel0_buf(qsel0_buf),
871 .shift_buf(shift_buf)
872);
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887endmodule
888
889
890
891//
892// ccx macro
893//
894//
895
896
897
898
899
900module cpx_dpsc_ccx_new_macro__type_b_l (
901 l2clk,
902 l1clk,
903 pce0,
904 pce1,
905 pce_ov,
906 se,
907 stop,
908 siclk_in,
909 soclk_in,
910 scan_in,
911 grant_a,
912 qsel0,
913 shift,
914 data_a,
915 data_prev_x_l,
916 data_x_l,
917 scan_out);
918wire so5;
919wire siclk_out;
920wire soclk_out;
921wire l1clk0;
922wire l1clk1;
923wire grant_x;
924wire qsel0_buf;
925wire shift_buf;
926
927input l2clk;
928input l1clk;
929input pce0;
930input pce1;
931input pce_ov;
932input se;
933input stop;
934input siclk_in;
935input soclk_in;
936input scan_in;
937input grant_a;
938input qsel0;
939input shift;
940input [9:0] data_a;
941input [9:0] data_prev_x_l;
942output [9:0] data_x_l;
943output scan_out;
944cl_dp1_ccxhdr c0 (
945.si(scan_in),
946.so(so5),
947 .l2clk(l2clk),
948 .pce0(pce0),
949 .pce1(pce1),
950 .pce_ov(pce_ov),
951 .stop(stop),
952 .siclk_in(siclk_in),
953 .soclk_in(soclk_in),
954 .siclk_out(siclk_out),
955 .soclk_out(soclk_out),
956 .l1clk0(l1clk0),
957 .l1clk1(l1clk1),
958 .se(se),
959 .l1clk(l1clk),
960 .grant_a(grant_a),
961 .grant_x(grant_x),
962 .qsel0(qsel0),
963 .qsel0_buf(qsel0_buf),
964 .shift(shift),
965 .shift_buf(shift_buf)
966);
967
968
969
970
971
972
973ccx_mac_b #(10) mac_b(
974.siclk(siclk_out),
975.soclk(soclk_out),
976.data_a(data_a[9:0]),
977.data_prev_x_l(data_prev_x_l[9:0]),
978.data_x_l(data_x_l[9:0]),
979.si(so5),
980.so(scan_out),
981 .l1clk0(l1clk0),
982 .l1clk1(l1clk1),
983 .grant_x(grant_x),
984 .qsel0_buf(qsel0_buf),
985 .shift_buf(shift_buf)
986);
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001endmodule
1002
1003
1004//
1005// ccx macro
1006//
1007//
1008
1009
1010
1011
1012
1013module cpx_dpsc_ccx_new_macro__type_c_l (
1014 l2clk,
1015 l1clk,
1016 pce0,
1017 pce1,
1018 pce_ov,
1019 se,
1020 stop,
1021 siclk_in,
1022 soclk_in,
1023 scan_in,
1024 grant_a,
1025 qsel0,
1026 shift,
1027 data_a,
1028 data_crit_x_l,
1029 data_ncrit_x_l,
1030 data_x_l,
1031 scan_out);
1032wire so5;
1033wire siclk_out;
1034wire soclk_out;
1035wire l1clk0;
1036wire l1clk1;
1037wire grant_x;
1038wire qsel0_buf;
1039wire shift_buf;
1040
1041input l2clk;
1042input l1clk;
1043input pce0;
1044input pce1;
1045input pce_ov;
1046input se;
1047input stop;
1048input siclk_in;
1049input soclk_in;
1050input scan_in;
1051input grant_a;
1052input qsel0;
1053input shift;
1054input [9:0] data_a;
1055input [9:0] data_crit_x_l;
1056input [9:0] data_ncrit_x_l;
1057output [9:0] data_x_l;
1058output scan_out;
1059cl_dp1_ccxhdr c0 (
1060.si(scan_in),
1061.so(so5),
1062 .l2clk(l2clk),
1063 .pce0(pce0),
1064 .pce1(pce1),
1065 .pce_ov(pce_ov),
1066 .stop(stop),
1067 .siclk_in(siclk_in),
1068 .soclk_in(soclk_in),
1069 .siclk_out(siclk_out),
1070 .soclk_out(soclk_out),
1071 .l1clk0(l1clk0),
1072 .l1clk1(l1clk1),
1073 .se(se),
1074 .l1clk(l1clk),
1075 .grant_a(grant_a),
1076 .grant_x(grant_x),
1077 .qsel0(qsel0),
1078 .qsel0_buf(qsel0_buf),
1079 .shift(shift),
1080 .shift_buf(shift_buf)
1081);
1082
1083
1084
1085
1086
1087
1088ccx_mac_c #(10) mac_c(
1089.siclk(siclk_out),
1090.soclk(soclk_out),
1091.data_a(data_a[9:0]),
1092.data_crit_x_l(data_crit_x_l[9:0]),
1093.data_ncrit_x_l(data_ncrit_x_l[9:0]),
1094.data_x_l(data_x_l[9:0]),
1095.si(so5),
1096.so(scan_out),
1097 .l1clk0(l1clk0),
1098 .l1clk1(l1clk1),
1099 .grant_x(grant_x),
1100 .qsel0_buf(qsel0_buf),
1101 .shift_buf(shift_buf)
1102);
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117endmodule
1118
1119
1120
1121//
1122// ccx macro
1123//
1124//
1125
1126
1127
1128
1129
1130module cpx_dpsc_ccx_new_macro__type_b_r (
1131 l2clk,
1132 l1clk,
1133 pce0,
1134 pce1,
1135 pce_ov,
1136 se,
1137 stop,
1138 siclk_in,
1139 soclk_in,
1140 scan_in,
1141 grant_a,
1142 qsel0,
1143 shift,
1144 data_a,
1145 data_prev_x_l,
1146 data_x_l,
1147 scan_out);
1148wire so5;
1149wire siclk_out;
1150wire soclk_out;
1151wire l1clk0;
1152wire l1clk1;
1153wire grant_x;
1154wire qsel0_buf;
1155wire shift_buf;
1156
1157input l2clk;
1158input l1clk;
1159input pce0;
1160input pce1;
1161input pce_ov;
1162input se;
1163input stop;
1164input siclk_in;
1165input soclk_in;
1166input scan_in;
1167input grant_a;
1168input qsel0;
1169input shift;
1170input [9:0] data_a;
1171input [9:0] data_prev_x_l;
1172output [9:0] data_x_l;
1173output scan_out;
1174cl_dp1_ccxhdr c0 (
1175.si(scan_in),
1176.so(so5),
1177 .l2clk(l2clk),
1178 .pce0(pce0),
1179 .pce1(pce1),
1180 .pce_ov(pce_ov),
1181 .stop(stop),
1182 .siclk_in(siclk_in),
1183 .soclk_in(soclk_in),
1184 .siclk_out(siclk_out),
1185 .soclk_out(soclk_out),
1186 .l1clk0(l1clk0),
1187 .l1clk1(l1clk1),
1188 .se(se),
1189 .l1clk(l1clk),
1190 .grant_a(grant_a),
1191 .grant_x(grant_x),
1192 .qsel0(qsel0),
1193 .qsel0_buf(qsel0_buf),
1194 .shift(shift),
1195 .shift_buf(shift_buf)
1196);
1197
1198
1199
1200
1201
1202
1203ccx_mac_b #(10) mac_b(
1204.siclk(siclk_out),
1205.soclk(soclk_out),
1206.data_a(data_a[9:0]),
1207.data_prev_x_l(data_prev_x_l[9:0]),
1208.data_x_l(data_x_l[9:0]),
1209.si(so5),
1210.so(scan_out),
1211 .l1clk0(l1clk0),
1212 .l1clk1(l1clk1),
1213 .grant_x(grant_x),
1214 .qsel0_buf(qsel0_buf),
1215 .shift_buf(shift_buf)
1216);
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231endmodule
1232
1233
1234//// scan renames
1235//assign pce_ov = tcu_pce_ov;
1236//assign stop = tcu_clk_stop;
1237//assign siclk = tcu_aclk;
1238//assign soclk = tcu_bclk;
1239//// end scan
1240//
1241//// buffer the grant signal
1242//
1243//buff_macro i_buf_grant (width=1, stack=50c)
1244//(
1245// .din (arb_grant_a),
1246// .dout (grant_a),
1247// );
1248//
1249//msff_macro i_dff_grant_x (width=12, stack=50c)
1250//(
1251// .scan_in(i_dff_grant_x_scanin),
1252// .scan_out(i_dff_grant_x_scanout),
1253// .clk (l2clk),
1254// .din ({12{grant_a}}),
1255// .dout (grant_x[11:0]),
1256// .en (1'b1),
1257// );
1258//
1259//
1260//// DATAPATH SECTION
1261//
1262//msff_macro i_dff_q1_2 (width=50, stack=50c)
1263//(
1264// .scan_in(i_dff_q1_2_scanin),
1265// .scan_out(i_dff_q1_2_scanout),
1266// .clk (l2clk),
1267// .din (src_cpx_data_a[149:100]),
1268// .dout (q1_dataout[149:100]),
1269// .en (arb_qsel1_a),
1270// );
1271//
1272//msff_macro i_dff_q1_1 (width=50, stack=50c)
1273//(
1274// .scan_in(i_dff_q1_1_scanin),
1275// .scan_out(i_dff_q1_1_scanout),
1276// .clk (l2clk),
1277// .din (src_cpx_data_a[99:50]),
1278// .dout (q1_dataout[99:50]),
1279// .en (arb_qsel1_a),
1280// );
1281//
1282//msff_macro i_dff_q1_0 (width=50, stack=50c)
1283//(
1284// .scan_in(i_dff_q1_0_scanin),
1285// .scan_out(i_dff_q1_0_scanout),
1286// .clk (l2clk),
1287// .din (src_cpx_data_a[49:0]),
1288// .dout (q1_dataout[49:0]),
1289// .en (arb_qsel1_a),
1290// );
1291//
1292////assign q0_datain_ca[149:0] =
1293//// (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
1294//// (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
1295//
1296//
1297//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c)
1298//(
1299// .din0 (src_cpx_data_a[149:100]),
1300// .din1 (q1_dataout[149:100]),
1301// .sel0 (arb_qsel0_a),
1302// .sel1 (arb_shift_a),
1303// .dout (q0_datain_a[149:100]),
1304// );
1305//
1306//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1307//(
1308// .din0 (src_cpx_data_a[99:50]),
1309// .din1 (q1_dataout[99:50]),
1310// .sel0 (arb_qsel0_a),
1311// .sel1 (arb_shift_a),
1312// .dout (q0_datain_a[99:50]),
1313// );
1314//
1315//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c)
1316//(
1317// .din0 (src_cpx_data_a[49:0]),
1318// .din1 (q1_dataout[49:0]),
1319// .sel0 (arb_qsel0_a),
1320// .sel1 (arb_shift_a),
1321// .dout (q0_datain_a[49:0]),
1322// );
1323//
1324//msff_macro i_dff_q0_2 (width=50, stack=50c)
1325//(
1326// .scan_in(i_dff_q0_2_scanin),
1327// .scan_out(i_dff_q0_2_scanout),
1328// .clk (l2clk),
1329// .din (q0_datain_a[149:100]),
1330// .dout (q0_dataout[149:100]),
1331// .en (arb_q0_holdbar_a),
1332// );
1333//
1334//msff_macro i_dff_q0_1 (width=50, stack=50c)
1335//(
1336// .scan_in(i_dff_q0_1_scanin),
1337// .scan_out(i_dff_q0_1_scanout),
1338// .clk (l2clk),
1339// .din (q0_datain_a[99:50]),
1340// .dout (q0_dataout[99:50]),
1341// .en (arb_q0_holdbar_a),
1342// );
1343//
1344//msff_macro i_dff_q0_0 (width=50, stack=50c)
1345//(
1346// .scan_in(i_dff_q0_0_scanin),
1347// .scan_out(i_dff_q0_0_scanout),
1348// .clk (l2clk),
1349// .din (q0_datain_a[49:0]),
1350// .dout (q0_dataout[49:0]),
1351// .en (arb_q0_holdbar_a),
1352// );
1353//
1354//// MUX
1355//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c)
1356//(
1357// .din0 (q0_dataout[149:100]),
1358// .din1 ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
1359// .dout (data_out_x_[149:100]),
1360// );
1361//
1362//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1363//(
1364// .din0 (q0_dataout[99:50]),
1365// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1366// .dout (data_out_x_[99:50]),
1367// );
1368//
1369//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c)
1370//(
1371// .din0 (q0_dataout[49:0]),
1372// .din1 ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
1373// .dout (data_out_x_[49:0]),
1374// );
1375//
1376//// fixscan start:
1377//assign i_dff_grant_x_scanin = scan_in ;
1378//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1379//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1380//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1381//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1382//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1383//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1384//assign scan_out = i_dff_q0_0_scanout ;
1385//// fixscan end:
1386
1387`endif // `ifndef FPGA
1388
1389`ifdef FPGA
1390`timescale 1 ns / 100 ps
1391module cpx_dpsc(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a,
1392 arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a,
1393 arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a,
1394 io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a,
1395 scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a,
1396 scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
1397 l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);
1398
1399 output [149:0] cpx_spc_data_x_;
1400 input [8:0] arb_grant_l_a;
1401 input [8:0] arb_q0_holdbar_l_a;
1402 input [8:0] arb_qsel0_l_a;
1403 input [8:0] arb_qsel1_l_a;
1404 input [8:0] arb_shift_l_a;
1405 input [8:0] arb_grant_r_a;
1406 input [8:0] arb_q0_holdbar_r_a;
1407 input [8:0] arb_qsel0_r_a;
1408 input [8:0] arb_qsel1_r_a;
1409 input [8:0] arb_shift_r_a;
1410 input [149:0] io_cpx_data_a;
1411 input [149:0] scache0_cpx_data_a;
1412 input [149:0] scache1_cpx_data_a;
1413 input [149:0] scache2_cpx_data_a;
1414 input [149:0] scache3_cpx_data_a;
1415 input [149:0] scache4_cpx_data_a;
1416 input [149:0] scache5_cpx_data_a;
1417 input [149:0] scache6_cpx_data_a;
1418 input [149:0] scache7_cpx_data_a;
1419 input tcu_scan_en;
1420 input l2clk;
1421 input scan_in;
1422 input tcu_pce_ov;
1423 input ccx_aclk;
1424 input ccx_bclk;
1425 output scan_out;
1426
1427 wire [4:0] mac0_rep_in;
1428 wire [3:0] arb_grant_l_a_rep;
1429 wire [3:0] arb_qsel0_l_a_rep;
1430 wire [3:0] arb_qsel1_l_a_rep;
1431 wire [3:0] arb_shift_l_a_rep;
1432 wire [3:0] arb_q0_holdbar_l_a_rep;
1433 wire [4:0] mac0_rep_out;
1434 wire [4:0] mac1_rep_in;
1435 wire [4:0] mac1_rep_out;
1436 wire [4:0] mac2_rep_in;
1437 wire [4:0] mac2_rep_out;
1438 wire [4:0] mac3_rep_in;
1439 wire [4:0] mac3_rep_out;
1440 wire [4:0] mac4_rep_in;
1441 wire [7:5] arb_grant_r_a_rep;
1442 wire [7:5] arb_q0_holdbar_r_a_rep;
1443 wire [7:5] arb_qsel0_r_a_rep;
1444 wire [7:5] arb_qsel1_r_a_rep;
1445 wire [7:5] arb_shift_r_a_rep;
1446 wire [4:0] mac4_rep_out;
1447 wire [4:0] mac5_rep_in;
1448 wire [4:0] mac5_rep_out;
1449 wire [4:0] mac6_rep_in;
1450 wire [4:0] mac6_rep_out;
1451 wire scan_rep_in;
1452 wire [149:0] col8_data_x_;
1453 wire tcu_scan_en_out_8_unused;
1454 wire tcu_pce_ov_out_8_unused;
1455 wire ccx_aclk_out_8_unused;
1456 wire ccx_bclk_out_8_unused;
1457 wire cpx_mac8_scanin;
1458 wire cpx_mac8_scanout;
1459 wire [6:0] tcu_scan_en_out;
1460 wire [6:0] tcu_pce_ov_out;
1461 wire [6:0] ccx_aclk_out;
1462 wire [6:0] ccx_bclk_out;
1463 wire [149:0] col0_data_x_;
1464 wire cpx_mac0_scanin;
1465 wire cpx_mac0_scanout;
1466 wire [149:0] col1_data_x_;
1467 wire cpx_mac1_scanin;
1468 wire cpx_mac1_scanout;
1469 wire [149:0] col3_data_x_;
1470 wire cpx_mac2_scanin;
1471 wire cpx_mac2_scanout;
1472 wire [149:0] col4_data_x_;
1473 wire cpx_mac3_scanin;
1474 wire cpx_mac3_scanout;
1475 wire [149:0] col5_data_x_;
1476 wire cpx_mac4_scanin;
1477 wire cpx_mac4_scanout;
1478 wire [149:0] col6_data_x_;
1479 wire cpx_mac5_scanin;
1480 wire cpx_mac5_scanout;
1481 wire [149:0] col7_data_x_;
1482 wire cpx_mac6_scanin;
1483 wire cpx_mac6_scanout;
1484 wire tcu_scan_en_out_7_unused;
1485 wire tcu_pce_ov_out_7_unused;
1486 wire ccx_aclk_out_7_unused;
1487 wire ccx_bclk_out_7_unused;
1488 wire cpx_mac7_scanin;
1489 wire cpx_mac7_scanout;
1490 wire [7:4] arb_grant_l_a_unused;
1491 wire [7:4] arb_q0_holdbar_l_a_unused;
1492 wire [7:4] arb_qsel0_l_a_unused;
1493 wire [7:4] arb_qsel1_l_a_unused;
1494 wire [7:4] arb_shift_l_a_unused;
1495 wire [8:0] arb_grant_r_a_unused;
1496 wire [8:0] arb_q0_holdbar_r_a_unused;
1497 wire [8:0] arb_qsel0_r_a_unused;
1498 wire [8:0] arb_qsel1_r_a_unused;
1499 wire [8:0] arb_shift_r_a_unused;
1500 wire scan_rep_out;
1501
1502 assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2],
1503 arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
1504 assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2],
1505 arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2],
1506 arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
1507 assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0],
1508 arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
1509 assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0],
1510 arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
1511 } = mac1_rep_out[4:0];
1512 assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3],
1513 arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
1514 assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3],
1515 arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
1516 } = mac2_rep_out[4:0];
1517 assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1],
1518 arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
1519 assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1],
1520 arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
1521 } = mac3_rep_out[4:0];
1522 assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7],
1523 arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
1524 assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7],
1525 arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
1526 } = mac4_rep_out[4:0];
1527 assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5],
1528 arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
1529 assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5],
1530 arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
1531 } = mac5_rep_out[4:0];
1532 assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6],
1533 arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
1534 assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6],
1535 arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
1536 } = mac6_rep_out[4:0];
1537 assign scan_rep_in = scan_in;
1538 assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
1539 assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
1540 assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
1541 assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
1542 assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
1543 assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
1544 assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
1545 assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
1546 assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
1547 assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
1548 assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
1549 assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
1550 assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
1551 assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
1552 assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
1553 assign cpx_mac8_scanin = scan_rep_out;
1554 assign cpx_mac0_scanin = cpx_mac8_scanout;
1555 assign cpx_mac1_scanin = cpx_mac0_scanout;
1556 assign cpx_mac2_scanin = cpx_mac1_scanout;
1557 assign cpx_mac3_scanin = cpx_mac2_scanout;
1558 assign cpx_mac4_scanin = cpx_mac3_scanout;
1559 assign cpx_mac5_scanin = cpx_mac4_scanout;
1560 assign cpx_mac6_scanin = cpx_mac5_scanout;
1561 assign cpx_mac7_scanin = cpx_mac6_scanout;
1562 assign scan_out = cpx_mac7_scanout;
1563
1564 cpx_rep_dp cpx_rep(
1565 .mac0_rep_out (mac0_rep_out[4:0]),
1566 .mac1_rep_out (mac1_rep_out[4:0]),
1567 .mac2_rep_out (mac2_rep_out[4:0]),
1568 .mac3_rep_out (mac3_rep_out[4:0]),
1569 .mac4_rep_out (mac4_rep_out[4:0]),
1570 .mac5_rep_out (mac5_rep_out[4:0]),
1571 .mac6_rep_out (mac6_rep_out[4:0]),
1572 .scan_rep_out (scan_rep_out),
1573 .mac0_rep_in (mac0_rep_in[4:0]),
1574 .mac1_rep_in (mac1_rep_in[4:0]),
1575 .mac2_rep_in (mac2_rep_in[4:0]),
1576 .mac3_rep_in (mac3_rep_in[4:0]),
1577 .mac4_rep_in (mac4_rep_in[4:0]),
1578 .mac5_rep_in (mac5_rep_in[4:0]),
1579 .mac6_rep_in (mac6_rep_in[4:0]),
1580 .scan_rep_in (scan_rep_in));
1581 cpx_mal_dp cpx_mac8(
1582 .data_out_x_ (col8_data_x_[149:0]),
1583 .tcu_scan_en_out (tcu_scan_en_out_8_unused),
1584 .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
1585 .ccx_aclk_out (ccx_aclk_out_8_unused),
1586 .ccx_bclk_out (ccx_bclk_out_8_unused),
1587 .arb_grant_a (arb_grant_l_a[8]),
1588 .arb_qsel0_a (arb_qsel0_l_a[8]),
1589 .arb_qsel1_a (arb_qsel1_l_a[8]),
1590 .arb_q0_holdbar_a (arb_q0_holdbar_l_a[8]),
1591 .arb_shift_a (arb_shift_l_a[8]),
1592 .src_cpx_data_a (io_cpx_data_a[149:0]),
1593 .scan_in (cpx_mac8_scanin),
1594 .scan_out (cpx_mac8_scanout),
1595 .l2clk (l2clk),
1596 .tcu_scan_en (tcu_scan_en_out[0]),
1597 .tcu_pce_ov (tcu_pce_ov_out[0]),
1598 .ccx_aclk (ccx_aclk_out[0]),
1599 .ccx_bclk (ccx_bclk_out[0]));
1600 cpx_mbl_dp cpx_mac0(
1601 .data_out_x_ (col0_data_x_[149:0]),
1602 .tcu_scan_en_out (tcu_scan_en_out[0]),
1603 .tcu_pce_ov_out (tcu_pce_ov_out[0]),
1604 .ccx_aclk_out (ccx_aclk_out[0]),
1605 .ccx_bclk_out (ccx_bclk_out[0]),
1606 .arb_grant_a (arb_grant_l_a_rep[2]),
1607 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
1608 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
1609 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
1610 .arb_shift_a (arb_shift_l_a_rep[2]),
1611 .src_cpx_data_a (scache2_cpx_data_a[149:0]),
1612 .data_prev_x_ (col8_data_x_[149:0]),
1613 .scan_in (cpx_mac0_scanin),
1614 .scan_out (cpx_mac0_scanout),
1615 .l2clk (l2clk),
1616 .tcu_scan_en (tcu_scan_en_out[1]),
1617 .tcu_pce_ov (tcu_pce_ov_out[1]),
1618 .ccx_aclk (ccx_aclk_out[1]),
1619 .ccx_bclk (ccx_bclk_out[1]));
1620 cpx_mbl_dp cpx_mac1(
1621 .data_out_x_ (col1_data_x_[149:0]),
1622 .tcu_scan_en_out (tcu_scan_en_out[1]),
1623 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
1624 .ccx_aclk_out (ccx_aclk_out[1]),
1625 .ccx_bclk_out (ccx_bclk_out[1]),
1626 .arb_grant_a (arb_grant_l_a_rep[0]),
1627 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
1628 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
1629 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
1630 .arb_shift_a (arb_shift_l_a_rep[0]),
1631 .src_cpx_data_a (scache0_cpx_data_a[149:0]),
1632 .data_prev_x_ (col0_data_x_[149:0]),
1633 .scan_in (cpx_mac1_scanin),
1634 .scan_out (cpx_mac1_scanout),
1635 .l2clk (l2clk),
1636 .tcu_scan_en (tcu_scan_en_out[2]),
1637 .tcu_pce_ov (tcu_pce_ov_out[2]),
1638 .ccx_aclk (ccx_aclk_out[2]),
1639 .ccx_bclk (ccx_bclk_out[2]));
1640 cpx_mcl_dp cpx_mac2(
1641 .data_out_x_ (cpx_spc_data_x_[149:0]),
1642 .tcu_scan_en_out (tcu_scan_en_out[2]),
1643 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
1644 .ccx_aclk_out (ccx_aclk_out[2]),
1645 .ccx_bclk_out (ccx_bclk_out[2]),
1646 .arb_grant_a (arb_grant_l_a_rep[3]),
1647 .arb_qsel0_a (arb_qsel0_l_a_rep[3]),
1648 .arb_qsel1_a (arb_qsel1_l_a_rep[3]),
1649 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]),
1650 .arb_shift_a (arb_shift_l_a_rep[3]),
1651 .src_cpx_data_a (scache3_cpx_data_a[149:0]),
1652 .data_crit_x_ (col3_data_x_[149:0]),
1653 .data_ncrit_x_ (col1_data_x_[149:0]),
1654 .scan_in (cpx_mac2_scanin),
1655 .scan_out (cpx_mac2_scanout),
1656 .l2clk (l2clk),
1657 .tcu_scan_en (tcu_scan_en_out[3]),
1658 .tcu_pce_ov (tcu_pce_ov_out[3]),
1659 .ccx_aclk (ccx_aclk_out[3]),
1660 .ccx_bclk (ccx_bclk_out[3]));
1661 cpx_mbr_dp cpx_mac3(
1662 .data_out_x_ (col3_data_x_[149:0]),
1663 .tcu_scan_en_out (tcu_scan_en_out[3]),
1664 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
1665 .ccx_aclk_out (ccx_aclk_out[3]),
1666 .ccx_bclk_out (ccx_bclk_out[3]),
1667 .arb_grant_a (arb_grant_l_a_rep[1]),
1668 .arb_qsel0_a (arb_qsel0_l_a_rep[1]),
1669 .arb_qsel1_a (arb_qsel1_l_a_rep[1]),
1670 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]),
1671 .arb_shift_a (arb_shift_l_a_rep[1]),
1672 .src_cpx_data_a (scache1_cpx_data_a[149:0]),
1673 .data_prev_x_ (col4_data_x_[149:0]),
1674 .scan_in (cpx_mac3_scanin),
1675 .scan_out (cpx_mac3_scanout),
1676 .l2clk (l2clk),
1677 .tcu_scan_en (tcu_scan_en),
1678 .tcu_pce_ov (tcu_pce_ov),
1679 .ccx_aclk (ccx_aclk),
1680 .ccx_bclk (ccx_bclk));
1681 cpx_mbr_dp cpx_mac4(
1682 .data_out_x_ (col4_data_x_[149:0]),
1683 .tcu_scan_en_out (tcu_scan_en_out[4]),
1684 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
1685 .ccx_aclk_out (ccx_aclk_out[4]),
1686 .ccx_bclk_out (ccx_bclk_out[4]),
1687 .arb_grant_a (arb_grant_r_a_rep[7]),
1688 .arb_qsel0_a (arb_qsel0_r_a_rep[7]),
1689 .arb_qsel1_a (arb_qsel1_r_a_rep[7]),
1690 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]),
1691 .arb_shift_a (arb_shift_r_a_rep[7]),
1692 .src_cpx_data_a (scache7_cpx_data_a[149:0]),
1693 .data_prev_x_ (col5_data_x_[149:0]),
1694 .scan_in (cpx_mac4_scanin),
1695 .scan_out (cpx_mac4_scanout),
1696 .l2clk (l2clk),
1697 .tcu_scan_en (tcu_scan_en_out[3]),
1698 .tcu_pce_ov (tcu_pce_ov_out[3]),
1699 .ccx_aclk (ccx_aclk_out[3]),
1700 .ccx_bclk (ccx_bclk_out[3]));
1701 cpx_mbr_dp cpx_mac5(
1702 .data_out_x_ (col5_data_x_[149:0]),
1703 .tcu_scan_en_out (tcu_scan_en_out[5]),
1704 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
1705 .ccx_aclk_out (ccx_aclk_out[5]),
1706 .ccx_bclk_out (ccx_bclk_out[5]),
1707 .arb_grant_a (arb_grant_r_a_rep[5]),
1708 .arb_qsel0_a (arb_qsel0_r_a_rep[5]),
1709 .arb_qsel1_a (arb_qsel1_r_a_rep[5]),
1710 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]),
1711 .arb_shift_a (arb_shift_r_a_rep[5]),
1712 .src_cpx_data_a (scache5_cpx_data_a[149:0]),
1713 .data_prev_x_ (col6_data_x_[149:0]),
1714 .scan_in (cpx_mac5_scanin),
1715 .scan_out (cpx_mac5_scanout),
1716 .l2clk (l2clk),
1717 .tcu_scan_en (tcu_scan_en_out[4]),
1718 .tcu_pce_ov (tcu_pce_ov_out[4]),
1719 .ccx_aclk (ccx_aclk_out[4]),
1720 .ccx_bclk (ccx_bclk_out[4]));
1721 cpx_mbr_dp cpx_mac6(
1722 .data_out_x_ (col6_data_x_[149:0]),
1723 .tcu_scan_en_out (tcu_scan_en_out[6]),
1724 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
1725 .ccx_aclk_out (ccx_aclk_out[6]),
1726 .ccx_bclk_out (ccx_bclk_out[6]),
1727 .arb_grant_a (arb_grant_r_a_rep[6]),
1728 .arb_qsel0_a (arb_qsel0_r_a_rep[6]),
1729 .arb_qsel1_a (arb_qsel1_r_a_rep[6]),
1730 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[6]),
1731 .arb_shift_a (arb_shift_r_a_rep[6]),
1732 .src_cpx_data_a (scache6_cpx_data_a[149:0]),
1733 .data_prev_x_ (col7_data_x_[149:0]),
1734 .scan_in (cpx_mac6_scanin),
1735 .scan_out (cpx_mac6_scanout),
1736 .l2clk (l2clk),
1737 .tcu_scan_en (tcu_scan_en_out[5]),
1738 .tcu_pce_ov (tcu_pce_ov_out[5]),
1739 .ccx_aclk (ccx_aclk_out[5]),
1740 .ccx_bclk (ccx_bclk_out[5]));
1741 cpx_mar_dp cpx_mac7(
1742 .data_out_x_ (col7_data_x_[149:0]),
1743 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
1744 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
1745 .ccx_aclk_out (ccx_aclk_out_7_unused),
1746 .ccx_bclk_out (ccx_bclk_out_7_unused),
1747 .arb_grant_a (arb_grant_r_a[4]),
1748 .arb_qsel0_a (arb_qsel0_r_a[4]),
1749 .arb_qsel1_a (arb_qsel1_r_a[4]),
1750 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[4]),
1751 .arb_shift_a (arb_shift_r_a[4]),
1752 .src_cpx_data_a (scache4_cpx_data_a[149:0]),
1753 .scan_in (cpx_mac7_scanin),
1754 .scan_out (cpx_mac7_scanout),
1755 .l2clk (l2clk),
1756 .tcu_scan_en (tcu_scan_en_out[6]),
1757 .tcu_pce_ov (tcu_pce_ov_out[6]),
1758 .ccx_aclk (ccx_aclk_out[6]),
1759 .ccx_bclk (ccx_bclk_out[6]));
1760endmodule
1761
1762`endif // `ifdef FPGA
1763