Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / cpx_dpsg.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cpx_dpsg.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifndef FPGA
36module cpx_dpsg (
37 cpx_spc_data_x_,
38 arb_grant_l_a,
39 arb_q0_holdbar_l_a,
40 arb_qsel0_l_a,
41 arb_qsel1_l_a,
42 arb_shift_l_a,
43 arb_grant_r_a,
44 arb_q0_holdbar_r_a,
45 arb_qsel0_r_a,
46 arb_qsel1_r_a,
47 arb_shift_r_a,
48 io_cpx_data_a,
49 scache0_cpx_data_a,
50 scache1_cpx_data_a,
51 scache2_cpx_data_a,
52 scache3_cpx_data_a,
53 scache4_cpx_data_a,
54 scache5_cpx_data_a,
55 scache6_cpx_data_a,
56 scache7_cpx_data_a,
57 tcu_scan_en,
58 l2clk,
59 scan_in,
60 tcu_pce_ov,
61 ccx_aclk,
62 ccx_bclk,
63 scan_out);
64wire [149:0] all_ones;
65wire [4:0] mac0_rep_in;
66wire [3:0] arb_grant_l_a_rep;
67wire [3:0] arb_qsel0_l_a_rep;
68wire [3:0] arb_qsel1_l_a_rep;
69wire [3:0] arb_shift_l_a_rep;
70wire [3:0] arb_q0_holdbar_l_a_rep;
71wire [4:0] mac0_rep_out;
72wire [4:0] mac1_rep_in;
73wire [4:0] mac1_rep_out;
74wire [4:0] mac2_rep_in;
75wire [4:0] mac2_rep_out;
76wire [4:0] mac3_rep_in;
77wire [4:0] mac3_rep_out;
78wire [4:0] mac4_rep_in;
79wire [7:5] arb_grant_r_a_rep;
80wire [7:5] arb_q0_holdbar_r_a_rep;
81wire [7:5] arb_qsel0_r_a_rep;
82wire [7:5] arb_qsel1_r_a_rep;
83wire [7:5] arb_shift_r_a_rep;
84wire [4:0] mac4_rep_out;
85wire [4:0] mac5_rep_in;
86wire [4:0] mac5_rep_out;
87wire [4:0] mac6_rep_in;
88wire [4:0] mac6_rep_out;
89wire scan_rep_in;
90wire [149:0] col8_data_x_;
91wire tcu_scan_en_out_8_unused;
92wire tcu_pce_ov_out_8_unused;
93wire ccx_aclk_out_8_unused;
94wire ccx_bclk_out_8_unused;
95wire cpx_mac8_scanin;
96wire cpx_mac8_scanout;
97wire [6:0] tcu_scan_en_out;
98wire [6:0] tcu_pce_ov_out;
99wire [6:0] ccx_aclk_out;
100wire [6:0] ccx_bclk_out;
101wire [149:0] col0_data_x_;
102wire cpx_mac0_scanin;
103wire cpx_mac0_scanout;
104wire [149:0] col1_data_x_;
105wire cpx_mac1_scanin;
106wire cpx_mac1_scanout;
107wire [149:0] col2_data_x_;
108wire cpx_mac2_scanin;
109wire cpx_mac2_scanout;
110wire [149:0] col3_data_x_;
111wire cpx_mac3_scanin;
112wire cpx_mac3_scanout;
113wire [149:0] col4_data_x_;
114wire cpx_mac4_scanin;
115wire cpx_mac4_scanout;
116wire [149:0] col5_data_x_;
117wire cpx_mac5_scanin;
118wire cpx_mac5_scanout;
119wire [149:0] col7_data_x_;
120wire cpx_mac6_scanin;
121wire cpx_mac6_scanout;
122wire tcu_scan_en_out_7_unused;
123wire tcu_pce_ov_out_7_unused;
124wire ccx_aclk_out_7_unused;
125wire ccx_bclk_out_7_unused;
126wire cpx_mac7_scanin;
127wire cpx_mac7_scanout;
128wire [7:4] arb_grant_l_a_unused;
129wire [7:4] arb_q0_holdbar_l_a_unused;
130wire [7:4] arb_qsel0_l_a_unused;
131wire [7:4] arb_qsel1_l_a_unused;
132wire [7:4] arb_shift_l_a_unused;
133wire [8:0] arb_grant_r_a_unused;
134wire [8:0] arb_q0_holdbar_r_a_unused;
135wire [8:0] arb_qsel0_r_a_unused;
136wire [8:0] arb_qsel1_r_a_unused;
137wire [8:0] arb_shift_r_a_unused;
138wire scan_rep_out;
139
140
141
142// Beginning of automatic outputs (from unused autoinst outputs)
143output [149:0] cpx_spc_data_x_; // From mac4 of cpx_mcr_dp.v
144// End of automatics
145
146// Beginning of automatic inputs (from unused autoinst inputs)
147input [8:0] arb_grant_l_a; // To mac0 of cpx_mar_dp.v, ...
148input [8:0] arb_q0_holdbar_l_a; // To mac0 of cpx_mar_dp.v, ...
149input [8:0] arb_qsel0_l_a; // To mac0 of cpx_mar_dp.v, ...
150input [8:0] arb_qsel1_l_a; // To mac0 of cpx_mar_dp.v, ...
151input [8:0] arb_shift_l_a; // To mac0 of cpx_mar_dp.v, ...
152input [8:0] arb_grant_r_a; // To mac0 of cpx_mar_dp.v, ...
153input [8:0] arb_q0_holdbar_r_a; // To mac0 of cpx_mar_dp.v, ...
154input [8:0] arb_qsel0_r_a; // To mac0 of cpx_mar_dp.v, ...
155input [8:0] arb_qsel1_r_a; // To mac0 of cpx_mar_dp.v, ...
156input [8:0] arb_shift_r_a; // To mac0 of cpx_mar_dp.v, ...
157input [149:0] io_cpx_data_a; // To mac8 of cpx_mal_dp.v
158input [149:0] scache0_cpx_data_a; // To mac0 of cpx_mar_dp.v
159input [149:0] scache1_cpx_data_a; // To mac1 of cpx_mbr_dp.v
160input [149:0] scache2_cpx_data_a; // To mac2 of cpx_mbr_dp.v
161input [149:0] scache3_cpx_data_a; // To mac3 of cpx_mbr_dp.v
162input [149:0] scache4_cpx_data_a; // To mac4 of cpx_mcr_dp.v
163input [149:0] scache5_cpx_data_a; // To mac5 of cpx_mbl_dp.v
164input [149:0] scache6_cpx_data_a; // To mac6 of cpx_mbl_dp.v
165input [149:0] scache7_cpx_data_a; // To cpx_mac7 of cpx_mbl_dp.v
166// End of automatics
167
168// globals
169input tcu_scan_en ;
170input l2clk;
171input scan_in;
172input tcu_pce_ov; // scan signals
173input ccx_aclk;
174input ccx_bclk;
175output scan_out;
176
177
178// io scache2 scache0 scache3 scache1 scache7 scache5 scache6 scache4
179// | | | | | | | | |
180// v v v v v v v v v
181// mac8-> mac0 -> mac1 <-mac2 <- mac3 <- mac4 <- mac5 <- mac6 <- mac7
182// al bl bl bl bl bl bl cl br
183// |
184// ---buf-------------------------------
185// |
186// v
187// to spccore
188
189assign all_ones[149:0] = 150'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
190
191// mac0 arb inputs go through 1 buffer
192assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
193 arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};
194
195assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
196 arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
197
198// mac1 arb input go through 1 buffer
199assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
200 arb_qsel1_l_a[0],arb_shift_l_a[0]};
201
202assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
203 arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];
204
205// mac2 arb inputs go through 2 buffers
206assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
207 arb_qsel1_l_a[3],arb_shift_l_a[3]};
208
209assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
210 arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];
211
212// mac3 inputs go through 2 buffers
213assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
214 arb_qsel1_l_a[1],arb_shift_l_a[1]};
215
216assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
217 arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];
218
219// mac4 inputs go through 2 buffers
220assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
221 arb_qsel1_r_a[7],arb_shift_r_a[7]};
222
223assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
224 arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];
225
226// mac5 inputs go through 1 buffer
227assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
228 arb_qsel1_r_a[5],arb_shift_r_a[5]};
229
230assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
231 arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];
232
233// mac6 inputs go through 1 buffer
234assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
235 arb_qsel1_r_a[6],arb_shift_r_a[6]};
236
237assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
238 arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];
239
240assign scan_rep_in = scan_in;
241
242
243
244cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
245 .mac1_rep_out(mac1_rep_out[4:0]),
246 .mac2_rep_out(mac2_rep_out[4:0]),
247 .mac3_rep_out(mac3_rep_out[4:0]),
248 .mac4_rep_out(mac4_rep_out[4:0]),
249 .mac5_rep_out(mac5_rep_out[4:0]),
250 .mac6_rep_out(mac6_rep_out[4:0]),
251 .scan_rep_out(scan_rep_out),
252 .mac0_rep_in(mac0_rep_in[4:0]),
253 .mac1_rep_in(mac1_rep_in[4:0]),
254 .mac2_rep_in(mac2_rep_in[4:0]),
255 .mac3_rep_in(mac3_rep_in[4:0]),
256 .mac4_rep_in(mac4_rep_in[4:0]),
257 .mac5_rep_in(mac5_rep_in[4:0]),
258 .mac6_rep_in(mac6_rep_in[4:0]),
259 .scan_rep_in(scan_rep_in)
260 );
261
262/*
263 cpx_mal_dp AUTO_TEMPLATE
264 (
265 // Outputs
266 .data_out_x_ (col@_data_x_[149:0]),
267 // Inputs
268 .arb_grant_a(arb_grant_l_a[@]),
269 .arb_qsel0_a(arb_qsel0_l_a[@]),
270 .arb_qsel1_a(arb_qsel1_l_a[@]),
271 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
272 .arb_shift_a(arb_shift_l_a[@]),
273 .src_cpx_data_a(io_cpx_data_a[149:0]),
274 .l2clk (l2clk));
275*/
276
277// do not use autoinstancing.
278// connections have been modified to match the cpu floorplan
279// src_pcx_data_a has to be manually connected.
280
281// input from io
282cpx_mal_dp cpx_mac8 (
283 // Outputs
284 .data_out_x_ (col8_data_x_[149:0]), // Templated
285 .tcu_scan_en_out (tcu_scan_en_out_8_unused),
286 .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
287 .ccx_aclk_out (ccx_aclk_out_8_unused),
288 .ccx_bclk_out (ccx_bclk_out_8_unused),
289 // Inputs
290 .arb_grant_a (arb_grant_l_a[8]), // Templated
291 .arb_qsel0_a (arb_qsel0_l_a[8]), // Templated
292 .arb_qsel1_a (arb_qsel1_l_a[8]), // Templated
293 .arb_q0_holdbar_a (arb_q0_holdbar_l_a[8]), // Templated
294 .arb_shift_a (arb_shift_l_a[8]), // Templated
295 .src_cpx_data_a (io_cpx_data_a[149:0]), // Templated
296 .scan_in(cpx_mac8_scanin),
297 .scan_out(cpx_mac8_scanout),
298 .l2clk (l2clk), // Templated
299 .tcu_scan_en (tcu_scan_en_out[0]),
300 .tcu_pce_ov (tcu_pce_ov_out[0]),
301 .ccx_aclk (ccx_aclk_out[0]),
302 .ccx_bclk (ccx_bclk_out[0])
303 );
304
305
306/*
307 cpx_mbl_dp AUTO_TEMPLATE
308 (
309 // Outputs
310 .data_out_x_ (col@_data_x_[149:0]),
311 // Inputs
312 .arb_grant_a(arb_grant_l_a[@]),
313 .arb_qsel0_a(arb_qsel0_l_a[@]),
314 .arb_qsel1_a(arb_qsel1_l_a[@]),
315 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
316 .arb_shift_a(arb_shift_l_a[@]),
317 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
318 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
319 .l2clk (l2clk));
320*/
321
322
323// input from sctag2
324cpx_mbl_dp cpx_mac0 (
325 // Outputs
326 .data_out_x_ (col0_data_x_[149:0]),
327 .tcu_scan_en_out (tcu_scan_en_out[0]),
328 .tcu_pce_ov_out (tcu_pce_ov_out[0]),
329 .ccx_aclk_out (ccx_aclk_out[0]),
330 .ccx_bclk_out (ccx_bclk_out[0]),
331 // Inputs
332 .arb_grant_a (arb_grant_l_a_rep[2]),
333 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
334 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
335 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
336 .arb_shift_a (arb_shift_l_a_rep[2]),
337 .src_cpx_data_a (scache2_cpx_data_a[149:0]),
338 .data_prev_x_ (col8_data_x_[149:0]),
339 .scan_in(cpx_mac0_scanin),
340 .scan_out(cpx_mac0_scanout),
341 .l2clk (l2clk),
342 .tcu_scan_en (tcu_scan_en_out[1]),
343 .tcu_pce_ov (tcu_pce_ov_out[1]),
344 .ccx_aclk (ccx_aclk_out[1]),
345 .ccx_bclk (ccx_bclk_out[1])
346 );
347
348
349// input from sctag0
350cpx_mbl_dp cpx_mac1 (
351 // Outputs
352 .data_out_x_ (col1_data_x_[149:0]),
353 .tcu_scan_en_out (tcu_scan_en_out[1]),
354 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
355 .ccx_aclk_out (ccx_aclk_out[1]),
356 .ccx_bclk_out (ccx_bclk_out[1]),
357 // Inputs
358 .arb_grant_a (arb_grant_l_a_rep[0]),
359 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
360 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
361 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
362 .arb_shift_a (arb_shift_l_a_rep[0]),
363 .src_cpx_data_a (scache0_cpx_data_a[149:0]),
364 .data_prev_x_ (col0_data_x_[149:0]),
365 .scan_in(cpx_mac1_scanin),
366 .scan_out(cpx_mac1_scanout),
367 .l2clk (l2clk),
368 .tcu_scan_en (tcu_scan_en_out[2]),
369 .tcu_pce_ov (tcu_pce_ov_out[2]),
370 .ccx_aclk (ccx_aclk_out[2]),
371 .ccx_bclk (ccx_bclk_out[2])
372 );
373
374
375// input from sctag3
376cpx_mbl_dp cpx_mac2 (
377 // Outputs
378 .data_out_x_ (col2_data_x_[149:0]),
379 .tcu_scan_en_out (tcu_scan_en_out[2]),
380 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
381 .ccx_aclk_out (ccx_aclk_out[2]),
382 .ccx_bclk_out (ccx_bclk_out[2]),
383 // Inputs
384 .arb_grant_a (arb_grant_l_a_rep[3]),
385 .arb_qsel0_a (arb_qsel0_l_a_rep[3]),
386 .arb_qsel1_a (arb_qsel1_l_a_rep[3]),
387 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]),
388 .arb_shift_a (arb_shift_l_a_rep[3]),
389 .src_cpx_data_a (scache3_cpx_data_a[149:0]),
390 .data_prev_x_ (col1_data_x_[149:0]),
391 .scan_in(cpx_mac2_scanin),
392 .scan_out(cpx_mac2_scanout),
393 .l2clk (l2clk),
394 .tcu_scan_en (tcu_scan_en_out[3]),
395 .tcu_pce_ov (tcu_pce_ov_out[3]),
396 .ccx_aclk (ccx_aclk_out[3]),
397 .ccx_bclk (ccx_bclk_out[3])
398 );
399
400// input from sctag1
401cpx_mbl_dp cpx_mac3 (
402 // Outputs
403 .data_out_x_ (col3_data_x_[149:0]),
404 .tcu_scan_en_out (tcu_scan_en_out[3]),
405 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
406 .ccx_aclk_out (ccx_aclk_out[3]),
407 .ccx_bclk_out (ccx_bclk_out[3]),
408 // Inputs
409 .arb_grant_a (arb_grant_l_a_rep[1]),
410 .arb_qsel0_a (arb_qsel0_l_a_rep[1]),
411 .arb_qsel1_a (arb_qsel1_l_a_rep[1]),
412 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]),
413 .arb_shift_a (arb_shift_l_a_rep[1]),
414 .src_cpx_data_a (scache1_cpx_data_a[149:0]),
415 .data_prev_x_ (col2_data_x_[149:0]),
416 .scan_in(cpx_mac3_scanin),
417 .scan_out(cpx_mac3_scanout),
418 .l2clk (l2clk),
419 .tcu_scan_en (tcu_scan_en),
420 .tcu_pce_ov (tcu_pce_ov),
421 .ccx_aclk (ccx_aclk),
422 .ccx_bclk (ccx_bclk)
423 );
424
425// input from sctag7
426cpx_mbl_dp cpx_mac4 (
427 // Outputs
428 .data_out_x_ (col4_data_x_[149:0]),
429 .tcu_scan_en_out (tcu_scan_en_out[4]),
430 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
431 .ccx_aclk_out (ccx_aclk_out[4]),
432 .ccx_bclk_out (ccx_bclk_out[4]),
433 // Inputs
434 .arb_grant_a (arb_grant_r_a_rep[7]),
435 .arb_qsel0_a (arb_qsel0_r_a_rep[7]),
436 .arb_qsel1_a (arb_qsel1_r_a_rep[7]),
437 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]),
438 .arb_shift_a (arb_shift_r_a_rep[7]),
439 .src_cpx_data_a (scache7_cpx_data_a[149:0]),
440 .data_prev_x_ (col3_data_x_[149:0]),
441 .scan_in(cpx_mac4_scanin),
442 .scan_out(cpx_mac4_scanout),
443 .l2clk (l2clk),
444 .tcu_scan_en (tcu_scan_en_out[3]),
445 .tcu_pce_ov (tcu_pce_ov_out[3]),
446 .ccx_aclk (ccx_aclk_out[3]),
447 .ccx_bclk (ccx_bclk_out[3])
448 );
449
450// input from sctag5
451cpx_mbl_dp cpx_mac5 (
452 // Outputs
453 .data_out_x_ (col5_data_x_[149:0]),
454 .tcu_scan_en_out (tcu_scan_en_out[5]),
455 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
456 .ccx_aclk_out (ccx_aclk_out[5]),
457 .ccx_bclk_out (ccx_bclk_out[5]),
458 // Inputs
459 .arb_grant_a (arb_grant_r_a_rep[5]),
460 .arb_qsel0_a (arb_qsel0_r_a_rep[5]),
461 .arb_qsel1_a (arb_qsel1_r_a_rep[5]),
462 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]),
463 .arb_shift_a (arb_shift_r_a_rep[5]),
464 .src_cpx_data_a (scache5_cpx_data_a[149:0]),
465 .data_prev_x_ (col4_data_x_[149:0]),
466 .scan_in(cpx_mac5_scanin),
467 .scan_out(cpx_mac5_scanout),
468 .l2clk (l2clk),
469 .tcu_scan_en (tcu_scan_en_out[4]),
470 .tcu_pce_ov (tcu_pce_ov_out[4]),
471 .ccx_aclk (ccx_aclk_out[4]),
472 .ccx_bclk (ccx_bclk_out[4])
473 );
474
475
476/*
477 cpx_mcr_dp AUTO_TEMPLATE
478 (
479 // Outputs
480 .data_out_x_ (cpx_spc_data_x_[149:0]),
481 // Inputs
482 .arb_grant_a(arb_grant_l_a[@]),
483 .arb_qsel0_a(arb_qsel0_l_a[@]),
484 .arb_qsel1_a(arb_qsel1_l_a[@]),
485 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
486 .arb_shift_a(arb_shift_l_a[@]),
487 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
488 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
489 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
490 .l2clk (l2clk));
491*/
492
493// input from sctag6
494cpx_mcr_dp cpx_mac6 (
495 // Outputs
496 .data_out_x_ (cpx_spc_data_x_[149:0]), // Templated
497 .tcu_scan_en_out (tcu_scan_en_out[6]),
498 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
499 .ccx_aclk_out (ccx_aclk_out[6]),
500 .ccx_bclk_out (ccx_bclk_out[6]),
501 // Inputs
502 .arb_grant_a (arb_grant_r_a_rep[6]), // Templated
503 .arb_qsel0_a (arb_qsel0_r_a_rep[6]), // Templated
504 .arb_qsel1_a (arb_qsel1_r_a_rep[6]), // Templated
505 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[6]), // Templated
506 .arb_shift_a (arb_shift_r_a_rep[6]), // Templated
507 .src_cpx_data_a (scache6_cpx_data_a[149:0]), // Templated
508 .data_crit_x_ (col5_data_x_[149:0]), // Templated
509 .data_ncrit_x_ (col7_data_x_[149:0]), // Templated
510 .scan_in(cpx_mac6_scanin),
511 .scan_out(cpx_mac6_scanout),
512 .l2clk (l2clk), // Templated
513 .tcu_scan_en (tcu_scan_en_out[5]),
514 .tcu_pce_ov (tcu_pce_ov_out[5]),
515 .ccx_aclk (ccx_aclk_out[5]),
516 .ccx_bclk (ccx_bclk_out[5])
517 );
518
519
520/*
521 cpx_mbr_dp AUTO_TEMPLATE
522 (
523 // Outputs
524 .data_out_x_ (col@_data_x_[149:0]),
525 // Inputs
526 .arb_grant_a(arb_grant_r_a[@]),
527 .arb_qsel0_a(arb_qsel0_r_a[@]),
528 .arb_qsel1_a(arb_qsel1_r_a[@]),
529 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
530 .arb_shift_a(arb_shift_r_a[@]),
531 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
532 .l2clk (l2clk));
533*/
534
535// input from sctag4
536cpx_mbr_dp cpx_mac7 (
537 // Outputs
538 .data_out_x_ (col7_data_x_[149:0]), // Templated
539 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
540 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
541 .ccx_aclk_out (ccx_aclk_out_7_unused),
542 .ccx_bclk_out (ccx_bclk_out_7_unused),
543 // Inputs
544 .arb_grant_a (arb_grant_r_a[4]), // Templated
545 .arb_qsel0_a (arb_qsel0_r_a[4]), // Templated
546 .arb_qsel1_a (arb_qsel1_r_a[4]), // Templated
547 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[4]), // Templated
548 .arb_shift_a (arb_shift_r_a[4]), // Templated
549 .src_cpx_data_a (scache4_cpx_data_a[149:0]), // Templated
550 .data_prev_x_ (all_ones[149:0]),
551 .scan_in(cpx_mac7_scanin),
552 .scan_out(cpx_mac7_scanout),
553 .l2clk (l2clk), // Templated
554 .tcu_scan_en (tcu_scan_en_out[6]),
555 .tcu_pce_ov (tcu_pce_ov_out[6]),
556 .ccx_aclk (ccx_aclk_out[6]),
557 .ccx_bclk (ccx_bclk_out[6])
558 );
559
560
561
562assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
563assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
564assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
565assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
566assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
567
568assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
569assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
570assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
571assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
572assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
573
574assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
575assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
576assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
577assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
578assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
579
580// fixscan start:
581assign cpx_mac8_scanin = scan_rep_out ;
582assign cpx_mac0_scanin = cpx_mac8_scanout ;
583assign cpx_mac1_scanin = cpx_mac0_scanout ;
584assign cpx_mac2_scanin = cpx_mac1_scanout ;
585assign cpx_mac3_scanin = cpx_mac2_scanout ;
586assign cpx_mac4_scanin = cpx_mac3_scanout ;
587assign cpx_mac5_scanin = cpx_mac4_scanout ;
588assign cpx_mac6_scanin = cpx_mac5_scanout ;
589assign cpx_mac7_scanin = cpx_mac6_scanout ;
590assign scan_out = cpx_mac7_scanout ;
591// fixscan end:
592endmodule
593
594// Local Variables:
595// verilog-library-directories:("." "v")
596// End:
597
598
599
600//
601// buff macro
602//
603//
604
605
606
607
608
609module cpx_dpsg_buff_macro__dbuff_32x__stack_6l__width_5 (
610 din,
611 dout);
612 input [4:0] din;
613 output [4:0] dout;
614
615
616
617
618
619
620buff #(5) d0_0 (
621.in(din[4:0]),
622.out(dout[4:0])
623);
624
625
626
627
628
629
630
631
632endmodule
633
634
635
636
637
638//
639// buff macro
640//
641//
642
643
644
645
646
647module cpx_dpsg_buff_macro__dbuff_32x__stack_none__width_1 (
648 din,
649 dout);
650 input [0:0] din;
651 output [0:0] dout;
652
653
654
655
656
657
658buff #(1) d0_0 (
659.in(din[0:0]),
660.out(dout[0:0])
661);
662
663
664
665
666
667
668
669
670endmodule
671
672
673
674
675//
676// buff macro
677//
678//
679
680
681
682
683
684module cpx_dpsg_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
685 din,
686 dout);
687 input [3:0] din;
688 output [3:0] dout;
689
690
691
692
693
694
695buff #(4) d0_0 (
696.in(din[3:0]),
697.out(dout[3:0])
698);
699
700
701
702
703
704
705
706
707endmodule
708
709
710
711
712
713
714
715
716
717// any PARAMS parms go into naming of macro
718
719module cpx_dpsg_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
720 l2clk,
721 l1en,
722 pce_ov,
723 stop,
724 se,
725 l1clk);
726
727
728 input l2clk;
729 input l1en;
730 input pce_ov;
731 input stop;
732 input se;
733 output l1clk;
734
735
736
737
738
739cl_sc1_l1hdr_24x c_0 (
740
741
742 .l2clk(l2clk),
743 .pce(l1en),
744 .l1clk(l1clk),
745 .se(se),
746 .pce_ov(pce_ov),
747 .stop(stop)
748);
749
750
751
752
753
754
755endmodule
756
757
758
759
760
761
762
763
764
765//
766// ccx macro
767//
768//
769
770
771
772
773
774module cpx_dpsg_ccx_new_macro__type_a (
775 l2clk,
776 l1clk,
777 pce0,
778 pce1,
779 pce_ov,
780 se,
781 stop,
782 siclk_in,
783 soclk_in,
784 scan_in,
785 grant_a,
786 qsel0,
787 shift,
788 data_a,
789 data_x_l,
790 scan_out);
791wire so5;
792wire siclk_out;
793wire soclk_out;
794wire l1clk0;
795wire l1clk1;
796wire grant_x;
797wire qsel0_buf;
798wire shift_buf;
799
800input l2clk;
801input l1clk;
802input pce0;
803input pce1;
804input pce_ov;
805input se;
806input stop;
807input siclk_in;
808input soclk_in;
809input scan_in;
810input grant_a;
811input qsel0;
812input shift;
813input [9:0] data_a;
814output [9:0] data_x_l;
815output scan_out;
816cl_dp1_ccxhdr c0 (
817.si(scan_in),
818.so(so5),
819 .l2clk(l2clk),
820 .pce0(pce0),
821 .pce1(pce1),
822 .pce_ov(pce_ov),
823 .stop(stop),
824 .siclk_in(siclk_in),
825 .soclk_in(soclk_in),
826 .siclk_out(siclk_out),
827 .soclk_out(soclk_out),
828 .l1clk0(l1clk0),
829 .l1clk1(l1clk1),
830 .se(se),
831 .l1clk(l1clk),
832 .grant_a(grant_a),
833 .grant_x(grant_x),
834 .qsel0(qsel0),
835 .qsel0_buf(qsel0_buf),
836 .shift(shift),
837 .shift_buf(shift_buf)
838);
839
840
841
842
843
844
845ccx_mac_a #(10) mac_a(
846.siclk(siclk_out),
847.soclk(soclk_out),
848.data_a(data_a[9:0]),
849.data_x_l(data_x_l[9:0]),
850.si(so5),
851.so(scan_out),
852 .l1clk0(l1clk0),
853 .l1clk1(l1clk1),
854 .grant_x(grant_x),
855 .qsel0_buf(qsel0_buf),
856 .shift_buf(shift_buf)
857);
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872endmodule
873
874
875//
876// ccx macro
877//
878//
879
880
881
882
883
884module cpx_dpsg_ccx_new_macro__type_b_l (
885 l2clk,
886 l1clk,
887 pce0,
888 pce1,
889 pce_ov,
890 se,
891 stop,
892 siclk_in,
893 soclk_in,
894 scan_in,
895 grant_a,
896 qsel0,
897 shift,
898 data_a,
899 data_prev_x_l,
900 data_x_l,
901 scan_out);
902wire so5;
903wire siclk_out;
904wire soclk_out;
905wire l1clk0;
906wire l1clk1;
907wire grant_x;
908wire qsel0_buf;
909wire shift_buf;
910
911input l2clk;
912input l1clk;
913input pce0;
914input pce1;
915input pce_ov;
916input se;
917input stop;
918input siclk_in;
919input soclk_in;
920input scan_in;
921input grant_a;
922input qsel0;
923input shift;
924input [9:0] data_a;
925input [9:0] data_prev_x_l;
926output [9:0] data_x_l;
927output scan_out;
928cl_dp1_ccxhdr c0 (
929.si(scan_in),
930.so(so5),
931 .l2clk(l2clk),
932 .pce0(pce0),
933 .pce1(pce1),
934 .pce_ov(pce_ov),
935 .stop(stop),
936 .siclk_in(siclk_in),
937 .soclk_in(soclk_in),
938 .siclk_out(siclk_out),
939 .soclk_out(soclk_out),
940 .l1clk0(l1clk0),
941 .l1clk1(l1clk1),
942 .se(se),
943 .l1clk(l1clk),
944 .grant_a(grant_a),
945 .grant_x(grant_x),
946 .qsel0(qsel0),
947 .qsel0_buf(qsel0_buf),
948 .shift(shift),
949 .shift_buf(shift_buf)
950);
951
952
953
954
955
956
957ccx_mac_b #(10) mac_b(
958.siclk(siclk_out),
959.soclk(soclk_out),
960.data_a(data_a[9:0]),
961.data_prev_x_l(data_prev_x_l[9:0]),
962.data_x_l(data_x_l[9:0]),
963.si(so5),
964.so(scan_out),
965 .l1clk0(l1clk0),
966 .l1clk1(l1clk1),
967 .grant_x(grant_x),
968 .qsel0_buf(qsel0_buf),
969 .shift_buf(shift_buf)
970);
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985endmodule
986
987
988//// scan renames
989//assign pce_ov = tcu_pce_ov;
990//assign stop = tcu_clk_stop;
991//assign siclk = tcu_aclk;
992//assign soclk = tcu_bclk;
993//// end scan
994//
995//// buffer the grant signal
996//
997//buff_macro i_buf_grant (width=1, stack=50c)
998//(
999// .din (arb_grant_a),
1000// .dout (grant_a),
1001// );
1002//
1003//msff_macro i_dff_grant_x (width=12, stack=50c)
1004//(
1005// .scan_in(i_dff_grant_x_scanin),
1006// .scan_out(i_dff_grant_x_scanout),
1007// .clk (l2clk),
1008// .din ({12{grant_a}}),
1009// .dout (grant_x[11:0]),
1010// .en (1'b1),
1011// );
1012//
1013//
1014//// DATAPATH SECTION
1015//
1016//msff_macro i_dff_q1_2 (width=50, stack=50c)
1017//(
1018// .scan_in(i_dff_q1_2_scanin),
1019// .scan_out(i_dff_q1_2_scanout),
1020// .clk (l2clk),
1021// .din (src_cpx_data_a[149:100]),
1022// .dout (q1_dataout[149:100]),
1023// .en (arb_qsel1_a),
1024// );
1025//
1026//msff_macro i_dff_q1_1 (width=50, stack=50c)
1027//(
1028// .scan_in(i_dff_q1_1_scanin),
1029// .scan_out(i_dff_q1_1_scanout),
1030// .clk (l2clk),
1031// .din (src_cpx_data_a[99:50]),
1032// .dout (q1_dataout[99:50]),
1033// .en (arb_qsel1_a),
1034// );
1035//
1036//msff_macro i_dff_q1_0 (width=50, stack=50c)
1037//(
1038// .scan_in(i_dff_q1_0_scanin),
1039// .scan_out(i_dff_q1_0_scanout),
1040// .clk (l2clk),
1041// .din (src_cpx_data_a[49:0]),
1042// .dout (q1_dataout[49:0]),
1043// .en (arb_qsel1_a),
1044// );
1045//
1046////assign q0_datain_ca[149:0] =
1047//// (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
1048//// (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
1049//
1050//
1051//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c)
1052//(
1053// .din0 (src_cpx_data_a[149:100]),
1054// .din1 (q1_dataout[149:100]),
1055// .sel0 (arb_qsel0_a),
1056// .sel1 (arb_shift_a),
1057// .dout (q0_datain_a[149:100]),
1058// );
1059//
1060//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1061//(
1062// .din0 (src_cpx_data_a[99:50]),
1063// .din1 (q1_dataout[99:50]),
1064// .sel0 (arb_qsel0_a),
1065// .sel1 (arb_shift_a),
1066// .dout (q0_datain_a[99:50]),
1067// );
1068//
1069//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c)
1070//(
1071// .din0 (src_cpx_data_a[49:0]),
1072// .din1 (q1_dataout[49:0]),
1073// .sel0 (arb_qsel0_a),
1074// .sel1 (arb_shift_a),
1075// .dout (q0_datain_a[49:0]),
1076// );
1077//
1078//msff_macro i_dff_q0_2 (width=50, stack=50c)
1079//(
1080// .scan_in(i_dff_q0_2_scanin),
1081// .scan_out(i_dff_q0_2_scanout),
1082// .clk (l2clk),
1083// .din (q0_datain_a[149:100]),
1084// .dout (q0_dataout[149:100]),
1085// .en (arb_q0_holdbar_a),
1086// );
1087//
1088//msff_macro i_dff_q0_1 (width=50, stack=50c)
1089//(
1090// .scan_in(i_dff_q0_1_scanin),
1091// .scan_out(i_dff_q0_1_scanout),
1092// .clk (l2clk),
1093// .din (q0_datain_a[99:50]),
1094// .dout (q0_dataout[99:50]),
1095// .en (arb_q0_holdbar_a),
1096// );
1097//
1098//msff_macro i_dff_q0_0 (width=50, stack=50c)
1099//(
1100// .scan_in(i_dff_q0_0_scanin),
1101// .scan_out(i_dff_q0_0_scanout),
1102// .clk (l2clk),
1103// .din (q0_datain_a[49:0]),
1104// .dout (q0_dataout[49:0]),
1105// .en (arb_q0_holdbar_a),
1106// );
1107//
1108////MUX
1109//
1110//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c)
1111//(
1112// .din0 (q0_dataout[149:100]),
1113// .din1 ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
1114// .dout (data_x_[149:100]),
1115// );
1116//
1117//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1118//(
1119// .din0 (q0_dataout[99:50]),
1120// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1121// .dout (data_x_[99:50]),
1122// );
1123//
1124//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c)
1125//(
1126// .din0 (q0_dataout[49:0]),
1127// .din1 ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
1128// .dout (data_x_[49:0]),
1129// );
1130//
1131//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c)
1132//(
1133// .din0 (data_x_[149:100]),
1134// .din1 (data_crit_x_[149:100]),
1135// .din2 (data_ncrit_x_[149:100]),
1136// .dout (data_out_x[149:100])
1137//);
1138//
1139//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c)
1140//(
1141// .din0 (data_x_[99:50]),
1142// .din1 (data_crit_x_[99:50]),
1143// .din2 (data_ncrit_x_[99:50]),
1144// .dout (data_out_x[99:50])
1145//);
1146//
1147//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c)
1148//(
1149// .din0 (data_x_[49:0]),
1150// .din1 (data_crit_x_[49:0]),
1151// .din2 (data_ncrit_x_[49:0]),
1152// .dout (data_out_x[49:0])
1153//);
1154//
1155//inv_macro i_inv_data_out_2 (width=50, stack=50c)
1156//(
1157// .din (data_out_x[149:100]),
1158// .dout (data_out_x_[149:100])
1159// );
1160//
1161//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1162//(
1163// .din (data_out_x[99:50]),
1164// .dout (data_out_x_[99:50])
1165// );
1166//
1167//inv_macro i_inv_data_out_0 (width=50, stack=50c)
1168//(
1169// .din (data_out_x[49:0]),
1170// .dout (data_out_x_[49:0])
1171// );
1172//
1173//// fixscan start:
1174//assign i_dff_grant_x_scanin = scan_in ;
1175//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1176//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1177//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1178//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1179//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1180//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1181//assign scan_out = i_dff_q0_0_scanout ;
1182//// fixscan end:
1183//endmodule
1184
1185
1186//
1187// ccx macro
1188//
1189//
1190
1191
1192
1193
1194
1195module cpx_dpsg_ccx_new_macro__type_c_r (
1196 l2clk,
1197 l1clk,
1198 pce0,
1199 pce1,
1200 pce_ov,
1201 se,
1202 stop,
1203 siclk_in,
1204 soclk_in,
1205 scan_in,
1206 grant_a,
1207 qsel0,
1208 shift,
1209 data_a,
1210 data_crit_x_l,
1211 data_ncrit_x_l,
1212 data_x_l,
1213 scan_out);
1214wire so5;
1215wire siclk_out;
1216wire soclk_out;
1217wire l1clk0;
1218wire l1clk1;
1219wire grant_x;
1220wire qsel0_buf;
1221wire shift_buf;
1222
1223input l2clk;
1224input l1clk;
1225input pce0;
1226input pce1;
1227input pce_ov;
1228input se;
1229input stop;
1230input siclk_in;
1231input soclk_in;
1232input scan_in;
1233input grant_a;
1234input qsel0;
1235input shift;
1236input [9:0] data_a;
1237input [9:0] data_crit_x_l;
1238input [9:0] data_ncrit_x_l;
1239output [9:0] data_x_l;
1240output scan_out;
1241cl_dp1_ccxhdr c0 (
1242.si(scan_in),
1243.so(so5),
1244 .l2clk(l2clk),
1245 .pce0(pce0),
1246 .pce1(pce1),
1247 .pce_ov(pce_ov),
1248 .stop(stop),
1249 .siclk_in(siclk_in),
1250 .soclk_in(soclk_in),
1251 .siclk_out(siclk_out),
1252 .soclk_out(soclk_out),
1253 .l1clk0(l1clk0),
1254 .l1clk1(l1clk1),
1255 .se(se),
1256 .l1clk(l1clk),
1257 .grant_a(grant_a),
1258 .grant_x(grant_x),
1259 .qsel0(qsel0),
1260 .qsel0_buf(qsel0_buf),
1261 .shift(shift),
1262 .shift_buf(shift_buf)
1263);
1264
1265
1266
1267
1268
1269
1270ccx_mac_c #(10) mac_c(
1271.siclk(siclk_out),
1272.soclk(soclk_out),
1273.data_a(data_a[9:0]),
1274.data_crit_x_l(data_crit_x_l[9:0]),
1275.data_ncrit_x_l(data_ncrit_x_l[9:0]),
1276.data_x_l(data_x_l[9:0]),
1277.si(so5),
1278.so(scan_out),
1279 .l1clk0(l1clk0),
1280 .l1clk1(l1clk1),
1281 .grant_x(grant_x),
1282 .qsel0_buf(qsel0_buf),
1283 .shift_buf(shift_buf)
1284);
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299endmodule
1300
1301
1302
1303//
1304// ccx macro
1305//
1306//
1307
1308
1309
1310
1311
1312module cpx_dpsg_ccx_new_macro__type_b_r (
1313 l2clk,
1314 l1clk,
1315 pce0,
1316 pce1,
1317 pce_ov,
1318 se,
1319 stop,
1320 siclk_in,
1321 soclk_in,
1322 scan_in,
1323 grant_a,
1324 qsel0,
1325 shift,
1326 data_a,
1327 data_prev_x_l,
1328 data_x_l,
1329 scan_out);
1330wire so5;
1331wire siclk_out;
1332wire soclk_out;
1333wire l1clk0;
1334wire l1clk1;
1335wire grant_x;
1336wire qsel0_buf;
1337wire shift_buf;
1338
1339input l2clk;
1340input l1clk;
1341input pce0;
1342input pce1;
1343input pce_ov;
1344input se;
1345input stop;
1346input siclk_in;
1347input soclk_in;
1348input scan_in;
1349input grant_a;
1350input qsel0;
1351input shift;
1352input [9:0] data_a;
1353input [9:0] data_prev_x_l;
1354output [9:0] data_x_l;
1355output scan_out;
1356cl_dp1_ccxhdr c0 (
1357.si(scan_in),
1358.so(so5),
1359 .l2clk(l2clk),
1360 .pce0(pce0),
1361 .pce1(pce1),
1362 .pce_ov(pce_ov),
1363 .stop(stop),
1364 .siclk_in(siclk_in),
1365 .soclk_in(soclk_in),
1366 .siclk_out(siclk_out),
1367 .soclk_out(soclk_out),
1368 .l1clk0(l1clk0),
1369 .l1clk1(l1clk1),
1370 .se(se),
1371 .l1clk(l1clk),
1372 .grant_a(grant_a),
1373 .grant_x(grant_x),
1374 .qsel0(qsel0),
1375 .qsel0_buf(qsel0_buf),
1376 .shift(shift),
1377 .shift_buf(shift_buf)
1378);
1379
1380
1381
1382
1383
1384
1385ccx_mac_b #(10) mac_b(
1386.siclk(siclk_out),
1387.soclk(soclk_out),
1388.data_a(data_a[9:0]),
1389.data_prev_x_l(data_prev_x_l[9:0]),
1390.data_x_l(data_x_l[9:0]),
1391.si(so5),
1392.so(scan_out),
1393 .l1clk0(l1clk0),
1394 .l1clk1(l1clk1),
1395 .grant_x(grant_x),
1396 .qsel0_buf(qsel0_buf),
1397 .shift_buf(shift_buf)
1398);
1399
1400
1401
1402
1403endmodule
1404
1405
1406
1407`endif // `ifndef FPGA
1408
1409`ifdef FPGA
1410
1411`timescale 1 ns / 100 ps
1412module cpx_dpsg(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a,
1413 arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a,
1414 arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a,
1415 io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a,
1416 scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a,
1417 scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
1418 l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);
1419
1420 output [149:0] cpx_spc_data_x_;
1421 input [8:0] arb_grant_l_a;
1422 input [8:0] arb_q0_holdbar_l_a;
1423 input [8:0] arb_qsel0_l_a;
1424 input [8:0] arb_qsel1_l_a;
1425 input [8:0] arb_shift_l_a;
1426 input [8:0] arb_grant_r_a;
1427 input [8:0] arb_q0_holdbar_r_a;
1428 input [8:0] arb_qsel0_r_a;
1429 input [8:0] arb_qsel1_r_a;
1430 input [8:0] arb_shift_r_a;
1431 input [149:0] io_cpx_data_a;
1432 input [149:0] scache0_cpx_data_a;
1433 input [149:0] scache1_cpx_data_a;
1434 input [149:0] scache2_cpx_data_a;
1435 input [149:0] scache3_cpx_data_a;
1436 input [149:0] scache4_cpx_data_a;
1437 input [149:0] scache5_cpx_data_a;
1438 input [149:0] scache6_cpx_data_a;
1439 input [149:0] scache7_cpx_data_a;
1440 input tcu_scan_en;
1441 input l2clk;
1442 input scan_in;
1443 input tcu_pce_ov;
1444 input ccx_aclk;
1445 input ccx_bclk;
1446 output scan_out;
1447
1448 wire [149:0] all_ones;
1449 wire [4:0] mac0_rep_in;
1450 wire [3:0] arb_grant_l_a_rep;
1451 wire [3:0] arb_qsel0_l_a_rep;
1452 wire [3:0] arb_qsel1_l_a_rep;
1453 wire [3:0] arb_shift_l_a_rep;
1454 wire [3:0] arb_q0_holdbar_l_a_rep;
1455 wire [4:0] mac0_rep_out;
1456 wire [4:0] mac1_rep_in;
1457 wire [4:0] mac1_rep_out;
1458 wire [4:0] mac2_rep_in;
1459 wire [4:0] mac2_rep_out;
1460 wire [4:0] mac3_rep_in;
1461 wire [4:0] mac3_rep_out;
1462 wire [4:0] mac4_rep_in;
1463 wire [7:5] arb_grant_r_a_rep;
1464 wire [7:5] arb_q0_holdbar_r_a_rep;
1465 wire [7:5] arb_qsel0_r_a_rep;
1466 wire [7:5] arb_qsel1_r_a_rep;
1467 wire [7:5] arb_shift_r_a_rep;
1468 wire [4:0] mac4_rep_out;
1469 wire [4:0] mac5_rep_in;
1470 wire [4:0] mac5_rep_out;
1471 wire [4:0] mac6_rep_in;
1472 wire [4:0] mac6_rep_out;
1473 wire scan_rep_in;
1474 wire [149:0] col8_data_x_;
1475 wire tcu_scan_en_out_8_unused;
1476 wire tcu_pce_ov_out_8_unused;
1477 wire ccx_aclk_out_8_unused;
1478 wire ccx_bclk_out_8_unused;
1479 wire cpx_mac8_scanin;
1480 wire cpx_mac8_scanout;
1481 wire [6:0] tcu_scan_en_out;
1482 wire [6:0] tcu_pce_ov_out;
1483 wire [6:0] ccx_aclk_out;
1484 wire [6:0] ccx_bclk_out;
1485 wire [149:0] col0_data_x_;
1486 wire cpx_mac0_scanin;
1487 wire cpx_mac0_scanout;
1488 wire [149:0] col1_data_x_;
1489 wire cpx_mac1_scanin;
1490 wire cpx_mac1_scanout;
1491 wire [149:0] col2_data_x_;
1492 wire cpx_mac2_scanin;
1493 wire cpx_mac2_scanout;
1494 wire [149:0] col3_data_x_;
1495 wire cpx_mac3_scanin;
1496 wire cpx_mac3_scanout;
1497 wire [149:0] col4_data_x_;
1498 wire cpx_mac4_scanin;
1499 wire cpx_mac4_scanout;
1500 wire [149:0] col5_data_x_;
1501 wire cpx_mac5_scanin;
1502 wire cpx_mac5_scanout;
1503 wire [149:0] col7_data_x_;
1504 wire cpx_mac6_scanin;
1505 wire cpx_mac6_scanout;
1506 wire tcu_scan_en_out_7_unused;
1507 wire tcu_pce_ov_out_7_unused;
1508 wire ccx_aclk_out_7_unused;
1509 wire ccx_bclk_out_7_unused;
1510 wire cpx_mac7_scanin;
1511 wire cpx_mac7_scanout;
1512 wire [7:4] arb_grant_l_a_unused;
1513 wire [7:4] arb_q0_holdbar_l_a_unused;
1514 wire [7:4] arb_qsel0_l_a_unused;
1515 wire [7:4] arb_qsel1_l_a_unused;
1516 wire [7:4] arb_shift_l_a_unused;
1517 wire [8:0] arb_grant_r_a_unused;
1518 wire [8:0] arb_q0_holdbar_r_a_unused;
1519 wire [8:0] arb_qsel0_r_a_unused;
1520 wire [8:0] arb_qsel1_r_a_unused;
1521 wire [8:0] arb_shift_r_a_unused;
1522 wire scan_rep_out;
1523
1524 assign all_ones[149:0] = 150'h3fffffffffffffffffffffffffffffffffffff;
1525 assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2],
1526 arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
1527 assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2],
1528 arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2],
1529 arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
1530 assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0],
1531 arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
1532 assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0],
1533 arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
1534 } = mac1_rep_out[4:0];
1535 assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3],
1536 arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
1537 assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3],
1538 arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
1539 } = mac2_rep_out[4:0];
1540 assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1],
1541 arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
1542 assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1],
1543 arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
1544 } = mac3_rep_out[4:0];
1545 assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7],
1546 arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
1547 assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7],
1548 arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
1549 } = mac4_rep_out[4:0];
1550 assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5],
1551 arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
1552 assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5],
1553 arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
1554 } = mac5_rep_out[4:0];
1555 assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6],
1556 arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
1557 assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6],
1558 arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
1559 } = mac6_rep_out[4:0];
1560 assign scan_rep_in = scan_in;
1561 assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
1562 assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
1563 assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
1564 assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
1565 assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
1566 assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
1567 assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
1568 assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
1569 assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
1570 assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
1571 assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
1572 assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
1573 assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
1574 assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
1575 assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
1576 assign cpx_mac8_scanin = scan_rep_out;
1577 assign cpx_mac0_scanin = cpx_mac8_scanout;
1578 assign cpx_mac1_scanin = cpx_mac0_scanout;
1579 assign cpx_mac2_scanin = cpx_mac1_scanout;
1580 assign cpx_mac3_scanin = cpx_mac2_scanout;
1581 assign cpx_mac4_scanin = cpx_mac3_scanout;
1582 assign cpx_mac5_scanin = cpx_mac4_scanout;
1583 assign cpx_mac6_scanin = cpx_mac5_scanout;
1584 assign cpx_mac7_scanin = cpx_mac6_scanout;
1585 assign scan_out = cpx_mac7_scanout;
1586
1587 cpx_rep_dp cpx_rep(
1588 .mac0_rep_out (mac0_rep_out[4:0]),
1589 .mac1_rep_out (mac1_rep_out[4:0]),
1590 .mac2_rep_out (mac2_rep_out[4:0]),
1591 .mac3_rep_out (mac3_rep_out[4:0]),
1592 .mac4_rep_out (mac4_rep_out[4:0]),
1593 .mac5_rep_out (mac5_rep_out[4:0]),
1594 .mac6_rep_out (mac6_rep_out[4:0]),
1595 .scan_rep_out (scan_rep_out),
1596 .mac0_rep_in (mac0_rep_in[4:0]),
1597 .mac1_rep_in (mac1_rep_in[4:0]),
1598 .mac2_rep_in (mac2_rep_in[4:0]),
1599 .mac3_rep_in (mac3_rep_in[4:0]),
1600 .mac4_rep_in (mac4_rep_in[4:0]),
1601 .mac5_rep_in (mac5_rep_in[4:0]),
1602 .mac6_rep_in (mac6_rep_in[4:0]),
1603 .scan_rep_in (scan_rep_in));
1604 cpx_mal_dp cpx_mac8(
1605 .data_out_x_ (col8_data_x_[149:0]),
1606 .tcu_scan_en_out (tcu_scan_en_out_8_unused),
1607 .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
1608 .ccx_aclk_out (ccx_aclk_out_8_unused),
1609 .ccx_bclk_out (ccx_bclk_out_8_unused),
1610 .arb_grant_a (arb_grant_l_a[8]),
1611 .arb_qsel0_a (arb_qsel0_l_a[8]),
1612 .arb_qsel1_a (arb_qsel1_l_a[8]),
1613 .arb_q0_holdbar_a (arb_q0_holdbar_l_a[8]),
1614 .arb_shift_a (arb_shift_l_a[8]),
1615 .src_cpx_data_a (io_cpx_data_a[149:0]),
1616 .scan_in (cpx_mac8_scanin),
1617 .scan_out (cpx_mac8_scanout),
1618 .l2clk (l2clk),
1619 .tcu_scan_en (tcu_scan_en_out[0]),
1620 .tcu_pce_ov (tcu_pce_ov_out[0]),
1621 .ccx_aclk (ccx_aclk_out[0]),
1622 .ccx_bclk (ccx_bclk_out[0]));
1623 cpx_mbl_dp cpx_mac0(
1624 .data_out_x_ (col0_data_x_[149:0]),
1625 .tcu_scan_en_out (tcu_scan_en_out[0]),
1626 .tcu_pce_ov_out (tcu_pce_ov_out[0]),
1627 .ccx_aclk_out (ccx_aclk_out[0]),
1628 .ccx_bclk_out (ccx_bclk_out[0]),
1629 .arb_grant_a (arb_grant_l_a_rep[2]),
1630 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
1631 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
1632 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
1633 .arb_shift_a (arb_shift_l_a_rep[2]),
1634 .src_cpx_data_a (scache2_cpx_data_a[149:0]),
1635 .data_prev_x_ (col8_data_x_[149:0]),
1636 .scan_in (cpx_mac0_scanin),
1637 .scan_out (cpx_mac0_scanout),
1638 .l2clk (l2clk),
1639 .tcu_scan_en (tcu_scan_en_out[1]),
1640 .tcu_pce_ov (tcu_pce_ov_out[1]),
1641 .ccx_aclk (ccx_aclk_out[1]),
1642 .ccx_bclk (ccx_bclk_out[1]));
1643 cpx_mbl_dp cpx_mac1(
1644 .data_out_x_ (col1_data_x_[149:0]),
1645 .tcu_scan_en_out (tcu_scan_en_out[1]),
1646 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
1647 .ccx_aclk_out (ccx_aclk_out[1]),
1648 .ccx_bclk_out (ccx_bclk_out[1]),
1649 .arb_grant_a (arb_grant_l_a_rep[0]),
1650 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
1651 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
1652 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
1653 .arb_shift_a (arb_shift_l_a_rep[0]),
1654 .src_cpx_data_a (scache0_cpx_data_a[149:0]),
1655 .data_prev_x_ (col0_data_x_[149:0]),
1656 .scan_in (cpx_mac1_scanin),
1657 .scan_out (cpx_mac1_scanout),
1658 .l2clk (l2clk),
1659 .tcu_scan_en (tcu_scan_en_out[2]),
1660 .tcu_pce_ov (tcu_pce_ov_out[2]),
1661 .ccx_aclk (ccx_aclk_out[2]),
1662 .ccx_bclk (ccx_bclk_out[2]));
1663 cpx_mbl_dp cpx_mac2(
1664 .data_out_x_ (col2_data_x_[149:0]),
1665 .tcu_scan_en_out (tcu_scan_en_out[2]),
1666 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
1667 .ccx_aclk_out (ccx_aclk_out[2]),
1668 .ccx_bclk_out (ccx_bclk_out[2]),
1669 .arb_grant_a (arb_grant_l_a_rep[3]),
1670 .arb_qsel0_a (arb_qsel0_l_a_rep[3]),
1671 .arb_qsel1_a (arb_qsel1_l_a_rep[3]),
1672 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]),
1673 .arb_shift_a (arb_shift_l_a_rep[3]),
1674 .src_cpx_data_a (scache3_cpx_data_a[149:0]),
1675 .data_prev_x_ (col1_data_x_[149:0]),
1676 .scan_in (cpx_mac2_scanin),
1677 .scan_out (cpx_mac2_scanout),
1678 .l2clk (l2clk),
1679 .tcu_scan_en (tcu_scan_en_out[3]),
1680 .tcu_pce_ov (tcu_pce_ov_out[3]),
1681 .ccx_aclk (ccx_aclk_out[3]),
1682 .ccx_bclk (ccx_bclk_out[3]));
1683 cpx_mbl_dp cpx_mac3(
1684 .data_out_x_ (col3_data_x_[149:0]),
1685 .tcu_scan_en_out (tcu_scan_en_out[3]),
1686 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
1687 .ccx_aclk_out (ccx_aclk_out[3]),
1688 .ccx_bclk_out (ccx_bclk_out[3]),
1689 .arb_grant_a (arb_grant_l_a_rep[1]),
1690 .arb_qsel0_a (arb_qsel0_l_a_rep[1]),
1691 .arb_qsel1_a (arb_qsel1_l_a_rep[1]),
1692 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]),
1693 .arb_shift_a (arb_shift_l_a_rep[1]),
1694 .src_cpx_data_a (scache1_cpx_data_a[149:0]),
1695 .data_prev_x_ (col2_data_x_[149:0]),
1696 .scan_in (cpx_mac3_scanin),
1697 .scan_out (cpx_mac3_scanout),
1698 .l2clk (l2clk),
1699 .tcu_scan_en (tcu_scan_en),
1700 .tcu_pce_ov (tcu_pce_ov),
1701 .ccx_aclk (ccx_aclk),
1702 .ccx_bclk (ccx_bclk));
1703 cpx_mbl_dp cpx_mac4(
1704 .data_out_x_ (col4_data_x_[149:0]),
1705 .tcu_scan_en_out (tcu_scan_en_out[4]),
1706 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
1707 .ccx_aclk_out (ccx_aclk_out[4]),
1708 .ccx_bclk_out (ccx_bclk_out[4]),
1709 .arb_grant_a (arb_grant_r_a_rep[7]),
1710 .arb_qsel0_a (arb_qsel0_r_a_rep[7]),
1711 .arb_qsel1_a (arb_qsel1_r_a_rep[7]),
1712 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]),
1713 .arb_shift_a (arb_shift_r_a_rep[7]),
1714 .src_cpx_data_a (scache7_cpx_data_a[149:0]),
1715 .data_prev_x_ (col3_data_x_[149:0]),
1716 .scan_in (cpx_mac4_scanin),
1717 .scan_out (cpx_mac4_scanout),
1718 .l2clk (l2clk),
1719 .tcu_scan_en (tcu_scan_en_out[3]),
1720 .tcu_pce_ov (tcu_pce_ov_out[3]),
1721 .ccx_aclk (ccx_aclk_out[3]),
1722 .ccx_bclk (ccx_bclk_out[3]));
1723 cpx_mbl_dp cpx_mac5(
1724 .data_out_x_ (col5_data_x_[149:0]),
1725 .tcu_scan_en_out (tcu_scan_en_out[5]),
1726 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
1727 .ccx_aclk_out (ccx_aclk_out[5]),
1728 .ccx_bclk_out (ccx_bclk_out[5]),
1729 .arb_grant_a (arb_grant_r_a_rep[5]),
1730 .arb_qsel0_a (arb_qsel0_r_a_rep[5]),
1731 .arb_qsel1_a (arb_qsel1_r_a_rep[5]),
1732 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]),
1733 .arb_shift_a (arb_shift_r_a_rep[5]),
1734 .src_cpx_data_a (scache5_cpx_data_a[149:0]),
1735 .data_prev_x_ (col4_data_x_[149:0]),
1736 .scan_in (cpx_mac5_scanin),
1737 .scan_out (cpx_mac5_scanout),
1738 .l2clk (l2clk),
1739 .tcu_scan_en (tcu_scan_en_out[4]),
1740 .tcu_pce_ov (tcu_pce_ov_out[4]),
1741 .ccx_aclk (ccx_aclk_out[4]),
1742 .ccx_bclk (ccx_bclk_out[4]));
1743 cpx_mcr_dp cpx_mac6(
1744 .data_out_x_ (cpx_spc_data_x_[149:0]),
1745 .tcu_scan_en_out (tcu_scan_en_out[6]),
1746 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
1747 .ccx_aclk_out (ccx_aclk_out[6]),
1748 .ccx_bclk_out (ccx_bclk_out[6]),
1749 .arb_grant_a (arb_grant_r_a_rep[6]),
1750 .arb_qsel0_a (arb_qsel0_r_a_rep[6]),
1751 .arb_qsel1_a (arb_qsel1_r_a_rep[6]),
1752 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[6]),
1753 .arb_shift_a (arb_shift_r_a_rep[6]),
1754 .src_cpx_data_a (scache6_cpx_data_a[149:0]),
1755 .data_crit_x_ (col5_data_x_[149:0]),
1756 .data_ncrit_x_ (col7_data_x_[149:0]),
1757 .scan_in (cpx_mac6_scanin),
1758 .scan_out (cpx_mac6_scanout),
1759 .l2clk (l2clk),
1760 .tcu_scan_en (tcu_scan_en_out[5]),
1761 .tcu_pce_ov (tcu_pce_ov_out[5]),
1762 .ccx_aclk (ccx_aclk_out[5]),
1763 .ccx_bclk (ccx_bclk_out[5]));
1764 cpx_mbr_dp cpx_mac7(
1765 .data_out_x_ (col7_data_x_[149:0]),
1766 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
1767 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
1768 .ccx_aclk_out (ccx_aclk_out_7_unused),
1769 .ccx_bclk_out (ccx_bclk_out_7_unused),
1770 .arb_grant_a (arb_grant_r_a[4]),
1771 .arb_qsel0_a (arb_qsel0_r_a[4]),
1772 .arb_qsel1_a (arb_qsel1_r_a[4]),
1773 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[4]),
1774 .arb_shift_a (arb_shift_r_a[4]),
1775 .src_cpx_data_a (scache4_cpx_data_a[149:0]),
1776 .data_prev_x_ (all_ones[149:0]),
1777 .scan_in (cpx_mac7_scanin),
1778 .scan_out (cpx_mac7_scanout),
1779 .l2clk (l2clk),
1780 .tcu_scan_en (tcu_scan_en_out[6]),
1781 .tcu_pce_ov (tcu_pce_ov_out[6]),
1782 .ccx_aclk (ccx_aclk_out[6]),
1783 .ccx_bclk (ccx_bclk_out[6]));
1784endmodule
1785
1786
1787`endif // `ifdef FPGA
1788