Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / cpx_rep_dp.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_rep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// GNU General Public License for more details.
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// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_rep_dp (
  mac0_rep_out, 
  mac1_rep_out, 
  mac2_rep_out, 
  mac3_rep_out, 
  mac4_rep_out, 
  mac5_rep_out, 
  mac6_rep_out, 
  scan_rep_out, 
  mac0_rep_in, 
  mac1_rep_in, 
  mac2_rep_in, 
  mac3_rep_in, 
  mac4_rep_in, 
  mac5_rep_in, 
  mac6_rep_in, 
  scan_rep_in);
wire [4:0] mac2_rep_0;
wire [4:0] mac3_rep_0;
wire [4:0] mac4_rep_0;
wire scan_rep7_out;
wire scan_rep5_out;
wire scan_rep3_out;
wire scan_rep1_out;


output [4:0]              mac0_rep_out;
output [4:0]              mac1_rep_out;
output [4:0]              mac2_rep_out;
output [4:0]              mac3_rep_out;
output [4:0]              mac4_rep_out;
output [4:0]              mac5_rep_out;
output [4:0]              mac6_rep_out;
output                    scan_rep_out;


input [4:0]              mac0_rep_in;
input [4:0]              mac1_rep_in;
input [4:0]              mac2_rep_in;
input [4:0]              mac3_rep_in;
input [4:0]              mac4_rep_in;
input [4:0]              mac5_rep_in;
input [4:0]              mac6_rep_in;
input                    scan_rep_in;




//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-  mac0  - mac1   -mac2  - mac3  -  mac4   - mac5  - mac6   - mac7   



// mac0 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0    (
	.din	({mac0_rep_in[4:0]}),
   .dout	({mac0_rep_out[4:0]})
);

// mac1 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1    (
	.din	({mac1_rep_in[4:0]}),
   .dout	({mac1_rep_out[4:0]})
);


// mac2 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0    (
	.din	({mac2_rep_in[4:0]}),
   .dout	({mac2_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1    (
	.din	({mac2_rep_0[4:0]}),
   .dout	({mac2_rep_out[4:0]})
);

// mac3 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0    (
	.din	({mac3_rep_in[4:0]}),
   .dout	({mac3_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1    (
	.din	({mac3_rep_0[4:0]}),
   .dout	({mac3_rep_out[4:0]})
);

// mac4 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0    (
	.din	({mac4_rep_in[4:0]}),
   .dout	({mac4_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1    (
	.din	({mac4_rep_0[4:0]}),
   .dout	({mac4_rep_out[4:0]})
);

// mac5 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5    (
	.din	({mac5_rep_in[4:0]}),
   .dout	({mac5_rep_out[4:0]})
);

// mac6 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6    (
	.din	({mac6_rep_in[4:0]}),
   .dout	({mac6_rep_out[4:0]})
);


// repeat the scan chain

// buffer on top of mac7
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan7    (
	.din	(scan_rep_in),
   .dout	(scan_rep7_out)
);

// buffer on top of mac5
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan5    (
	.din	(scan_rep7_out),
   .dout	(scan_rep5_out)
);

// buffer on top of mac3
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan3    (
	.din	(scan_rep5_out),
   .dout	(scan_rep3_out)
);

// buffer on top of mac1
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan1    (
	.din	(scan_rep3_out),
   .dout	(scan_rep1_out)
);

// buffer on top of mac8
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan8    (
	.din	(scan_rep1_out),
   .dout	(scan_rep_out)
);

endmodule


//
//   buff macro
//
//





module cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;






buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);








endmodule





//
//   buff macro
//
//





module cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;






buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);








endmodule



`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_rep_dp(mac0_rep_out, mac1_rep_out, mac2_rep_out, mac3_rep_out, 
	mac4_rep_out, mac5_rep_out, mac6_rep_out, scan_rep_out, mac0_rep_in, 
	mac1_rep_in, mac2_rep_in, mac3_rep_in, mac4_rep_in, mac5_rep_in, 
	mac6_rep_in, scan_rep_in);

	output	[4:0]		mac0_rep_out;
	output	[4:0]		mac1_rep_out;
	output	[4:0]		mac2_rep_out;
	output	[4:0]		mac3_rep_out;
	output	[4:0]		mac4_rep_out;
	output	[4:0]		mac5_rep_out;
	output	[4:0]		mac6_rep_out;
	output			scan_rep_out;
	input	[4:0]		mac0_rep_in;
	input	[4:0]		mac1_rep_in;
	input	[4:0]		mac2_rep_in;
	input	[4:0]		mac3_rep_in;
	input	[4:0]		mac4_rep_in;
	input	[4:0]		mac5_rep_in;
	input	[4:0]		mac6_rep_in;
	input			scan_rep_in;

	wire	[4:0]		mac2_rep_0;
	wire	[4:0]		mac3_rep_0;
	wire	[4:0]		mac4_rep_0;
	wire			scan_rep7_out;
	wire			scan_rep5_out;
	wire			scan_rep3_out;
	wire			scan_rep1_out;

	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0(
		.din				({mac0_rep_in[4:0]}), 
		.dout				({mac0_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1(
		.din				({mac1_rep_in[4:0]}), 
		.dout				({mac1_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0(
		.din				({mac2_rep_in[4:0]}), 
		.dout				({mac2_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1(
		.din				({mac2_rep_0[4:0]}), 
		.dout				({mac2_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0(
		.din				({mac3_rep_in[4:0]}), 
		.dout				({mac3_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1(
		.din				({mac3_rep_0[4:0]}), 
		.dout				({mac3_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0(
		.din				({mac4_rep_in[4:0]}), 
		.dout				({mac4_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1(
		.din				({mac4_rep_0[4:0]}), 
		.dout				({mac4_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5(
		.din				({mac5_rep_in[4:0]}), 
		.dout				({mac5_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6(
		.din				({mac6_rep_in[4:0]}), 
		.dout				({mac6_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan7(
		.din				(scan_rep_in), 
		.dout				(scan_rep7_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan5(
		.din				(scan_rep7_out), 
		.dout				(scan_rep5_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan3(
		.din				(scan_rep5_out), 
		.dout				(scan_rep3_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan1(
		.din				(scan_rep3_out), 
		.dout				(scan_rep1_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan8(
		.din				(scan_rep1_out), 
		.dout				(scan_rep_out));
endmodule

module buff_macro__dbuff_32x__stack_6l__width_5(din, dout);

        input   [4:0]           din;
        output  [4:0]           dout;

        buff #(5) d0_0(
                .in                             (din[4:0]),
                .out                            (dout[4:0]));
endmodule



`endif // `ifdef FPGA