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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / pcx_dpsb.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: pcx_dpsb.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifndef FPGA
36module pcx_dpsb (
37 pcx_scache_data_x_,
38 arb_grant_l_a,
39 arb_q0_holdbar_l_a,
40 arb_qsel0_l_a,
41 arb_qsel1_l_a,
42 arb_shift_l_a,
43 arb_grant_r_a,
44 arb_q0_holdbar_r_a,
45 arb_qsel0_r_a,
46 arb_qsel1_r_a,
47 arb_shift_r_a,
48 spc0_pcx_data_a,
49 spc1_pcx_data_a,
50 spc2_pcx_data_a,
51 spc3_pcx_data_a,
52 spc4_pcx_data_a,
53 spc5_pcx_data_a,
54 spc6_pcx_data_a,
55 spc7_pcx_data_a,
56 tcu_scan_en,
57 l2clk,
58 tcu_pce_ov,
59 ccx_aclk,
60 ccx_bclk,
61 scan_in,
62 scan_out);
63wire [129:0] all_ones;
64wire [4:0] mac0_rep_in;
65wire [3:0] arb_grant_l_a_rep;
66wire [3:0] arb_qsel0_l_a_rep;
67wire [3:0] arb_qsel1_l_a_rep;
68wire [3:0] arb_shift_l_a_rep;
69wire [3:0] arb_q0_holdbar_l_a_rep;
70wire [4:0] mac0_rep_out;
71wire [4:0] mac1_rep_in;
72wire [4:0] mac1_rep_out;
73wire [4:0] mac2_rep_in;
74wire [4:0] mac2_rep_out;
75wire [4:0] mac3_rep_in;
76wire [4:0] mac3_rep_out;
77wire [4:0] mac4_rep_in;
78wire [7:4] arb_grant_r_a_rep;
79wire [7:4] arb_q0_holdbar_r_a_rep;
80wire [7:4] arb_qsel0_r_a_rep;
81wire [7:4] arb_qsel1_r_a_rep;
82wire [7:4] arb_shift_r_a_rep;
83wire [4:0] mac4_rep_out;
84wire [4:0] mac5_rep_in;
85wire [4:0] mac5_rep_out;
86wire [4:0] mac6_rep_in;
87wire [4:0] mac6_rep_out;
88wire scan_rep_in;
89wire [129:0] col0_data_x_;
90wire tcu_scan_en_out_0_unused;
91wire tcu_pce_ov_out_0_unused;
92wire ccx_aclk_out_0_unused;
93wire ccx_bclk_out_0_unused;
94wire pcx_mac0_scanin;
95wire pcx_mac0_scanout;
96wire [6:1] tcu_scan_en_out;
97wire [6:1] tcu_pce_ov_out;
98wire [6:1] ccx_aclk_out;
99wire [6:1] ccx_bclk_out;
100wire [129:0] col2_data_x_;
101wire pcx_mac1_scanin;
102wire pcx_mac1_scanout;
103wire [129:0] col3_data_x_;
104wire pcx_mac2_scanin;
105wire pcx_mac2_scanout;
106wire [129:0] col4_data_x_;
107wire pcx_mac3_scanin;
108wire pcx_mac3_scanout;
109wire [129:0] col5_data_x_;
110wire pcx_mac4_scanin;
111wire pcx_mac4_scanout;
112wire [129:0] col6_data_x_;
113wire pcx_mac5_scanin;
114wire pcx_mac5_scanout;
115wire [129:0] col7_data_x_;
116wire pcx_mac6_scanin;
117wire pcx_mac6_scanout;
118wire tcu_scan_en_out_7_unused;
119wire tcu_pce_ov_out_7_unused;
120wire ccx_aclk_out_7_unused;
121wire ccx_bclk_out_7_unused;
122wire pcx_mac7_scanin;
123wire pcx_mac7_scanout;
124wire [7:4] arb_grant_l_a_unused;
125wire [7:4] arb_q0_holdbar_l_a_unused;
126wire [7:4] arb_qsel0_l_a_unused;
127wire [7:4] arb_qsel1_l_a_unused;
128wire [7:4] arb_shift_l_a_unused;
129wire [3:0] arb_grant_r_a_unused;
130wire [3:0] arb_q0_holdbar_r_a_unused;
131wire [3:0] arb_qsel0_r_a_unused;
132wire [3:0] arb_qsel1_r_a_unused;
133wire [3:0] arb_shift_r_a_unused;
134wire scan_rep_out;
135
136
137// Beginning of automatic outputs (from unused autoinst outputs)
138output [129:0] pcx_scache_data_x_; // From mac3 of pcx_mcr_dp.v
139// End of automatics
140
141// Beginning of automatic inputs (from unused autoinst inputs)
142input [7:0] arb_grant_l_a; // To mac0 of pcx_mar_dp.v, ...
143input [7:0] arb_q0_holdbar_l_a; // To mac0 of pcx_mar_dp.v, ...
144input [7:0] arb_qsel0_l_a; // To mac0 of pcx_mar_dp.v, ...
145input [7:0] arb_qsel1_l_a; // To mac0 of pcx_mar_dp.v, ...
146input [7:0] arb_shift_l_a; // To mac0 of pcx_mar_dp.v, ...
147input [7:0] arb_grant_r_a; // To mac0 of pcx_mar_dp.v, ...
148input [7:0] arb_q0_holdbar_r_a; // To mac0 of pcx_mar_dp.v, ...
149input [7:0] arb_qsel0_r_a; // To mac0 of pcx_mar_dp.v, ...
150input [7:0] arb_qsel1_r_a; // To mac0 of pcx_mar_dp.v, ...
151input [7:0] arb_shift_r_a; // To mac0 of pcx_mar_dp.v, ...
152input [129:0] spc0_pcx_data_a; // To mac0 of pcx_mar_dp.v
153input [129:0] spc1_pcx_data_a; // To mac1 of pcx_mbr_dp.v
154input [129:0] spc2_pcx_data_a; // To mac2 of pcx_mbr_dp.v
155input [129:0] spc3_pcx_data_a; // To mac3 of pcx_mcr_dp.v
156input [129:0] spc4_pcx_data_a; // To mac4 of pcx_mbl_dp.v
157input [129:0] spc5_pcx_data_a; // To mac5 of pcx_mbl_dp.v
158input [129:0] spc6_pcx_data_a; // To mac6 of pcx_mbl_dp.v
159input [129:0] spc7_pcx_data_a; // To mac7 of pcx_mal_dp.v
160// End of automatics
161// globals
162input tcu_scan_en ;
163input l2clk;
164input tcu_pce_ov; // scan signals
165input ccx_aclk;
166input ccx_bclk;
167input scan_in;
168output scan_out;
169
170
171// sparc0 sparc2 sparc1 sparc3 sparc5 sparc7 sparc4 sparc6
172// | | | | | | | |
173// v v v v v v v v
174// mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7
175// bl cl br br br br br ar
176// |
177// buf
178// |
179// v
180// to sctag
181
182assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
183
184// mac0 arb inputs go through 1 buffer
185assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
186 arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};
187
188assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
189 arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
190
191// mac1 arb input go through 1 buffer
192assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
193 arb_qsel1_l_a[2],arb_shift_l_a[2]};
194
195assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
196 arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];
197
198// mac2 arb inputs go through 2 buffers
199assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
200 arb_qsel1_l_a[1],arb_shift_l_a[1]};
201
202assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
203 arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];
204
205// mac3 inputs go through 2 buffers
206assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
207 arb_qsel1_l_a[3],arb_shift_l_a[3]};
208
209assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
210 arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];
211
212// mac4 inputs go through 2 buffers
213assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
214 arb_qsel1_r_a[5],arb_shift_r_a[5]};
215
216assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
217 arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];
218
219// mac5 inputs go through 1 buffer
220assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
221 arb_qsel1_r_a[7],arb_shift_r_a[7]};
222
223assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
224 arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];
225
226// mac6 inputs go through 1 buffer
227assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
228 arb_qsel1_r_a[4],arb_shift_r_a[4]};
229
230assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
231 arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];
232
233assign scan_rep_in = scan_in;
234
235
236
237pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
238 .mac1_rep_out(mac1_rep_out[4:0]),
239 .mac2_rep_out(mac2_rep_out[4:0]),
240 .mac3_rep_out(mac3_rep_out[4:0]),
241 .mac4_rep_out(mac4_rep_out[4:0]),
242 .mac5_rep_out(mac5_rep_out[4:0]),
243 .mac6_rep_out(mac6_rep_out[4:0]),
244 .scan_rep_out(scan_rep_out),
245 .mac0_rep_in(mac0_rep_in[4:0]),
246 .mac1_rep_in(mac1_rep_in[4:0]),
247 .mac2_rep_in(mac2_rep_in[4:0]),
248 .mac3_rep_in(mac3_rep_in[4:0]),
249 .mac4_rep_in(mac4_rep_in[4:0]),
250 .mac5_rep_in(mac5_rep_in[4:0]),
251 .mac6_rep_in(mac6_rep_in[4:0]),
252 .scan_rep_in(scan_rep_in)
253 );
254
255
256/*
257 pcx_mbl_dp AUTO_TEMPLATE
258 (
259 // Outputs
260 .data_out_x_ (col@_data_x_[129:0]),
261 // Inputs
262 .arb_grant_a(arb_grant_l_a[@]),
263 .arb_qsel0_a(arb_qsel0_l_a[@]),
264 .arb_qsel1_a(arb_qsel1_l_a[@]),
265 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
266 .arb_shift_a(arb_shift_l_a[@]),
267 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
268 .l2clk (l2clk));
269*/
270
271// do not use autoinstancing.
272// connections have been modified to match the cpu floorplan
273// src_pcx_data_a has to be manually connected.
274
275// input from sp0
276pcx_mbl_dp pcx_mac0 (
277 // Outputs
278 .data_out_x_ (col0_data_x_[129:0]), // Templated
279 .tcu_scan_en_out (tcu_scan_en_out_0_unused),
280 .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
281 .ccx_aclk_out (ccx_aclk_out_0_unused),
282 .ccx_bclk_out (ccx_bclk_out_0_unused),
283 // Inputs
284 .arb_grant_a (arb_grant_l_a_rep[0]), // Templated
285 .arb_qsel0_a (arb_qsel0_l_a_rep[0]), // Templated
286 .arb_qsel1_a (arb_qsel1_l_a_rep[0]), // Templated
287 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]), // Templated
288 .arb_shift_a (arb_shift_l_a_rep[0]), // Templated
289 .src_pcx_data_a (spc0_pcx_data_a[129:0]), // Templated
290 .data_prev_x_ (all_ones[129:0]), // Templated
291 .scan_in(pcx_mac0_scanin),
292 .scan_out(pcx_mac0_scanout),
293 .l2clk (l2clk), // Templated
294 .tcu_scan_en (tcu_scan_en_out[1]),
295 .tcu_pce_ov (tcu_pce_ov_out[1]),
296 .ccx_aclk (ccx_aclk_out[1]),
297 .ccx_bclk (ccx_bclk_out[1])
298 );
299
300
301/*
302 pcx_mcl_dp AUTO_TEMPLATE
303 (
304 // Outputs
305 .data_out_x_ (pcx_scache_data_x_[129:0]),
306 // Inputs
307 .arb_grant_a(arb_grant_l_a[@]),
308 .arb_qsel0_a(arb_qsel0_l_a[@]),
309 .arb_qsel1_a(arb_qsel1_l_a[@]),
310 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
311 .arb_shift_a(arb_shift_l_a[@]),
312 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
313 .data_crit_x_(col@"(+ @ 1)"_data_x_[129:0]),
314 .data_ncrit_x_(col@"(- @ 1)"_data_x_[129:0]),
315 .l2clk (l2clk))
316*/
317
318// input from spc2
319pcx_mcl_dp pcx_mac1(
320 // Outputs
321 .data_out_x_ (pcx_scache_data_x_[129:0]), // Templated
322 .tcu_scan_en_out (tcu_scan_en_out[1]),
323 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
324 .ccx_aclk_out (ccx_aclk_out[1]),
325 .ccx_bclk_out (ccx_bclk_out[1]),
326 // Inputs
327 .arb_grant_a (arb_grant_l_a_rep[2]), // Templated
328 .arb_qsel0_a (arb_qsel0_l_a_rep[2]), // Templated
329 .arb_qsel1_a (arb_qsel1_l_a_rep[2]), // Templated
330 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]), // Templated
331 .arb_shift_a (arb_shift_l_a_rep[2]), // Templated
332 .src_pcx_data_a (spc2_pcx_data_a[129:0]), // Templated
333 .data_crit_x_ (col2_data_x_[129:0]), // Templated
334 .data_ncrit_x_ (col0_data_x_[129:0]), // Templated
335 .scan_in(pcx_mac1_scanin),
336 .scan_out(pcx_mac1_scanout),
337 .l2clk (l2clk),
338 .tcu_scan_en (tcu_scan_en_out[2]),
339 .tcu_pce_ov (tcu_pce_ov_out[2]),
340 .ccx_aclk (ccx_aclk_out[2]),
341 .ccx_bclk (ccx_bclk_out[2])
342 );
343
344
345/*
346 pcx_mbr_dp AUTO_TEMPLATE
347 (
348 // Outputs
349 .data_out_x_ (col@_data_x_[129:0]),
350 // Inputs
351 .arb_grant_a(arb_grant_r_a[@]),
352 .arb_qsel0_a(arb_qsel0_r_a[@]),
353 .arb_qsel1_a(arb_qsel1_r_a[@]),
354 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
355 .arb_shift_a(arb_shift_r_a[@]),
356 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
357 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
358 .l2clk (l2clk))
359*/
360
361// do not use autoinstancing.
362// connections have been modified to match the cpu floorplan
363// src_pcx_data_a has to be manually connected.
364
365// input from spc1
366pcx_mbr_dp pcx_mac2(
367 // Outputs
368 .data_out_x_ (col2_data_x_[129:0]), // Templated
369 .tcu_scan_en_out (tcu_scan_en_out[2]),
370 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
371 .ccx_aclk_out (ccx_aclk_out[2]),
372 .ccx_bclk_out (ccx_bclk_out[2]),
373 // Inputs
374 .arb_grant_a (arb_grant_l_a_rep[1] ), // Templated
375 .arb_qsel0_a (arb_qsel0_l_a_rep[1]), // Templated
376 .arb_qsel1_a (arb_qsel1_l_a_rep[1]), // Templated
377 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]), // Templated
378 .arb_shift_a (arb_shift_l_a_rep[1]), // Templated
379 .src_pcx_data_a (spc1_pcx_data_a[129:0]), // Templated
380 .data_prev_x_ (col3_data_x_[129:0]), // Templated
381 .scan_in(pcx_mac2_scanin),
382 .scan_out(pcx_mac2_scanout),
383 .l2clk (l2clk),
384 .tcu_scan_en (tcu_scan_en_out[3]),
385 .tcu_pce_ov (tcu_pce_ov_out[3]),
386 .ccx_aclk (ccx_aclk_out[3]),
387 .ccx_bclk (ccx_bclk_out[3])
388 );
389
390// input from spc3
391pcx_mbr_dp pcx_mac3(
392 // Outputs
393 .data_out_x_ (col3_data_x_[129:0]), // Templated
394 .tcu_scan_en_out (tcu_scan_en_out[3]),
395 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
396 .ccx_aclk_out (ccx_aclk_out[3]),
397 .ccx_bclk_out (ccx_bclk_out[3]),
398 // Inputs
399 .arb_grant_a (arb_grant_l_a_rep[3]), // Templated
400 .arb_qsel0_a (arb_qsel0_l_a_rep[3]), // Templated
401 .arb_qsel1_a (arb_qsel1_l_a_rep[3]), // Templated
402 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]), // Templated
403 .arb_shift_a (arb_shift_l_a_rep[3]), // Templated
404 .src_pcx_data_a (spc3_pcx_data_a[129:0]), // Templated
405 .data_prev_x_ (col4_data_x_[129:0]), // Templated
406 .scan_in(pcx_mac3_scanin),
407 .scan_out(pcx_mac3_scanout),
408 .l2clk (l2clk),
409 .tcu_scan_en (tcu_scan_en),
410 .tcu_pce_ov (tcu_pce_ov),
411 .ccx_aclk (ccx_aclk),
412 .ccx_bclk (ccx_bclk)
413 );
414
415
416// input from spc5
417pcx_mbr_dp pcx_mac4(
418 // Outputs
419 .data_out_x_ (col4_data_x_[129:0]), // Templated
420 .tcu_scan_en_out (tcu_scan_en_out[4]),
421 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
422 .ccx_aclk_out (ccx_aclk_out[4]),
423 .ccx_bclk_out (ccx_bclk_out[4]),
424 // Inputs
425 .arb_grant_a (arb_grant_r_a_rep[5]), // Templated
426 .arb_qsel0_a (arb_qsel0_r_a_rep[5]), // Templated
427 .arb_qsel1_a (arb_qsel1_r_a_rep[5]), // Templated
428 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]), // Templated
429 .arb_shift_a (arb_shift_r_a_rep[5]), // Templated
430 .src_pcx_data_a (spc5_pcx_data_a[129:0]), // Templated
431 .data_prev_x_ (col5_data_x_[129:0]), // Templated
432 .scan_in(pcx_mac4_scanin),
433 .scan_out(pcx_mac4_scanout),
434 .l2clk (l2clk),
435 .tcu_scan_en (tcu_scan_en_out[3]),
436 .tcu_pce_ov (tcu_pce_ov_out[3]),
437 .ccx_aclk (ccx_aclk_out[3]),
438 .ccx_bclk (ccx_bclk_out[3])
439 );
440
441// input from spc7
442pcx_mbr_dp pcx_mac5(
443 // Outputs
444 .data_out_x_ (col5_data_x_[129:0]), // Templated
445 .tcu_scan_en_out (tcu_scan_en_out[5]),
446 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
447 .ccx_aclk_out (ccx_aclk_out[5]),
448 .ccx_bclk_out (ccx_bclk_out[5]),
449 // Inputs
450 .arb_grant_a (arb_grant_r_a_rep[7]), // Templated
451 .arb_qsel0_a (arb_qsel0_r_a_rep[7]), // Templated
452 .arb_qsel1_a (arb_qsel1_r_a_rep[7]), // Templated
453 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]), // Templated
454 .arb_shift_a (arb_shift_r_a_rep[7]), // Templated
455 .src_pcx_data_a (spc7_pcx_data_a[129:0]), // Templated
456 .data_prev_x_ (col6_data_x_[129:0]), // Templated
457 .scan_in(pcx_mac5_scanin),
458 .scan_out(pcx_mac5_scanout),
459 .l2clk (l2clk),
460 .tcu_scan_en (tcu_scan_en_out[4]),
461 .tcu_pce_ov (tcu_pce_ov_out[4]),
462 .ccx_aclk (ccx_aclk_out[4]),
463 .ccx_bclk (ccx_bclk_out[4])
464 );
465
466
467// input from spc4
468pcx_mbr_dp pcx_mac6(
469 // Outputs
470 .data_out_x_ (col6_data_x_[129:0]), // Templated
471 .tcu_scan_en_out (tcu_scan_en_out[6]),
472 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
473 .ccx_aclk_out (ccx_aclk_out[6]),
474 .ccx_bclk_out (ccx_bclk_out[6]),
475 // Inputs
476 .arb_grant_a (arb_grant_r_a_rep[4]), // Templated
477 .arb_qsel0_a (arb_qsel0_r_a_rep[4]), // Templated
478 .arb_qsel1_a (arb_qsel1_r_a_rep[4]), // Templated
479 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[4]), // Templated
480 .arb_shift_a (arb_shift_r_a_rep[4]), // Templated
481 .src_pcx_data_a (spc4_pcx_data_a[129:0]), // Templated
482 .data_prev_x_ (col7_data_x_[129:0]), // Templated
483 .scan_in(pcx_mac6_scanin),
484 .scan_out(pcx_mac6_scanout),
485 .l2clk (l2clk),
486 .tcu_scan_en (tcu_scan_en_out[5]),
487 .tcu_pce_ov (tcu_pce_ov_out[5]),
488 .ccx_aclk (ccx_aclk_out[5]),
489 .ccx_bclk (ccx_bclk_out[5])
490 );
491
492
493/*
494 pcx_mar_dp AUTO_TEMPLATE
495 (
496 // Outputs
497 .data_out_x_ (col@_data_x_[129:0]),
498 // Inputs
499 .arb_grant_a(arb_grant_r_a[@]),
500 .arb_qsel0_a(arb_qsel0_r_a[@]),
501 .arb_qsel1_a(arb_qsel1_r_a[@]),
502 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
503 .arb_shift_a(arb_shift_r_a[@]),
504 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
505 .l2clk (l2clk));
506*/
507
508// do not use autoinstancing.
509// connections have been modified to match the cpu floorplan
510// src_pcx_data_a has to be manually connected.
511
512// input from spc6
513pcx_mar_dp pcx_mac7 (
514 // Outputs
515 .data_out_x_ (col7_data_x_[129:0]), // Templated
516 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
517 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
518 .ccx_aclk_out (ccx_aclk_out_7_unused),
519 .ccx_bclk_out (ccx_bclk_out_7_unused),
520 // Inputs
521 .arb_grant_a (arb_grant_r_a[6]), // Templated
522 .arb_qsel0_a (arb_qsel0_r_a[6]), // Templated
523 .arb_qsel1_a (arb_qsel1_r_a[6]), // Templated
524 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[6]), // Templated
525 .arb_shift_a (arb_shift_r_a[6]), // Templated
526 .src_pcx_data_a (spc6_pcx_data_a[129:0]), // Templated
527 .scan_in(pcx_mac7_scanin),
528 .scan_out(pcx_mac7_scanout),
529 .l2clk (l2clk), // Templated
530 .tcu_scan_en (tcu_scan_en_out[6]),
531 .tcu_pce_ov (tcu_pce_ov_out[6]),
532 .ccx_aclk (ccx_aclk_out[6]),
533 .ccx_bclk (ccx_bclk_out[6])
534 );
535
536
537
538
539assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
540assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
541assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
542assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
543assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
544
545assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
546assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
547assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
548assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
549assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
550
551// fixscan start:
552assign pcx_mac0_scanin = scan_rep_out ;
553assign pcx_mac1_scanin = pcx_mac0_scanout ;
554assign pcx_mac2_scanin = pcx_mac1_scanout ;
555assign pcx_mac3_scanin = pcx_mac2_scanout ;
556assign pcx_mac4_scanin = pcx_mac3_scanout ;
557assign pcx_mac5_scanin = pcx_mac4_scanout ;
558assign pcx_mac6_scanin = pcx_mac5_scanout ;
559assign pcx_mac7_scanin = pcx_mac6_scanout ;
560assign scan_out = pcx_mac7_scanout ;
561// fixscan end:
562endmodule
563
564// Local Variables:
565// verilog-library-directories:("." "v")
566// End:
567
568
569
570//
571// buff macro
572//
573//
574
575
576
577
578
579module pcx_dpsb_buff_macro__dbuff_32x__stack_6l__width_5 (
580 din,
581 dout);
582 input [4:0] din;
583 output [4:0] dout;
584
585
586
587
588
589
590buff #(5) d0_0 (
591.in(din[4:0]),
592.out(dout[4:0])
593);
594
595
596
597
598
599
600
601
602endmodule
603
604
605
606
607
608//
609// buff macro
610//
611//
612
613
614
615
616
617module pcx_dpsb_buff_macro__dbuff_32x__stack_none__width_1 (
618 din,
619 dout);
620 input [0:0] din;
621 output [0:0] dout;
622
623
624
625
626
627
628buff #(1) d0_0 (
629.in(din[0:0]),
630.out(dout[0:0])
631);
632
633
634
635
636
637
638
639
640endmodule
641
642
643
644//
645// buff macro
646//
647//
648
649
650
651
652
653module pcx_dpsb_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
654 din,
655 dout);
656 input [3:0] din;
657 output [3:0] dout;
658
659
660
661
662
663
664buff #(4) d0_0 (
665.in(din[3:0]),
666.out(dout[3:0])
667);
668
669
670
671
672
673
674
675
676endmodule
677
678
679
680
681
682
683
684
685
686// any PARAMS parms go into naming of macro
687
688module pcx_dpsb_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
689 l2clk,
690 l1en,
691 pce_ov,
692 stop,
693 se,
694 l1clk);
695
696
697 input l2clk;
698 input l1en;
699 input pce_ov;
700 input stop;
701 input se;
702 output l1clk;
703
704
705
706
707
708cl_sc1_l1hdr_24x c_0 (
709
710
711 .l2clk(l2clk),
712 .pce(l1en),
713 .l1clk(l1clk),
714 .se(se),
715 .pce_ov(pce_ov),
716 .stop(stop)
717);
718
719
720
721
722
723
724endmodule
725
726
727
728
729
730
731
732
733
734//
735// ccx macro
736//
737//
738
739
740
741
742
743module pcx_dpsb_ccx_new_macro__type_b_l (
744 l2clk,
745 l1clk,
746 pce0,
747 pce1,
748 pce_ov,
749 se,
750 stop,
751 siclk_in,
752 soclk_in,
753 scan_in,
754 grant_a,
755 qsel0,
756 shift,
757 data_a,
758 data_prev_x_l,
759 data_x_l,
760 scan_out);
761wire so5;
762wire siclk_out;
763wire soclk_out;
764wire l1clk0;
765wire l1clk1;
766wire grant_x;
767wire qsel0_buf;
768wire shift_buf;
769
770input l2clk;
771input l1clk;
772input pce0;
773input pce1;
774input pce_ov;
775input se;
776input stop;
777input siclk_in;
778input soclk_in;
779input scan_in;
780input grant_a;
781input qsel0;
782input shift;
783input [9:0] data_a;
784input [9:0] data_prev_x_l;
785output [9:0] data_x_l;
786output scan_out;
787cl_dp1_ccxhdr c0 (
788.si(scan_in),
789.so(so5),
790 .l2clk(l2clk),
791 .pce0(pce0),
792 .pce1(pce1),
793 .pce_ov(pce_ov),
794 .stop(stop),
795 .siclk_in(siclk_in),
796 .soclk_in(soclk_in),
797 .siclk_out(siclk_out),
798 .soclk_out(soclk_out),
799 .l1clk0(l1clk0),
800 .l1clk1(l1clk1),
801 .se(se),
802 .l1clk(l1clk),
803 .grant_a(grant_a),
804 .grant_x(grant_x),
805 .qsel0(qsel0),
806 .qsel0_buf(qsel0_buf),
807 .shift(shift),
808 .shift_buf(shift_buf)
809);
810
811
812
813
814
815
816ccx_mac_b #(10) mac_b(
817.siclk(siclk_out),
818.soclk(soclk_out),
819.data_a(data_a[9:0]),
820.data_prev_x_l(data_prev_x_l[9:0]),
821.data_x_l(data_x_l[9:0]),
822.si(so5),
823.so(scan_out),
824 .l1clk0(l1clk0),
825 .l1clk1(l1clk1),
826 .grant_x(grant_x),
827 .qsel0_buf(qsel0_buf),
828 .shift_buf(shift_buf)
829);
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844endmodule
845
846
847//
848//// scan renames
849//assign pce_ov = tcu_pce_ov;
850//assign stop = tcu_clk_stop;
851//assign siclk = tcu_aclk;
852//assign soclk = tcu_bclk;
853//// end scan
854//
855//buff_macro i_buf_grant (width=1, stack=30c)
856//(
857// .din (arb_grant_a),
858// .dout (grant_a),
859// );
860//
861//msff_macro i_dff_grant_x (width=12, stack=30c)
862//(
863// .scan_in(i_dff_grant_x_scanin),
864// .scan_out(i_dff_grant_x_scanout),
865// .clk (l2clk),
866// .din ({12{grant_a}}),
867// .dout (grant_x[11:0]),
868// .en (1'b1),
869// );
870//
871//// DATAPATH SECTION
872//
873//msff_macro i_dff_q1_2 (width=40, stack=50c)
874//(
875// .scan_in(i_dff_q1_2_scanin),
876// .scan_out(i_dff_q1_2_scanout),
877// .clk (l2clk),
878// .din (src_pcx_data_a[129:90]),
879// .dout (q1_dataout[129:90]),
880// .en (arb_qsel1_a),
881// );
882//
883//msff_macro i_dff_q1_1 (width=50, stack=50c)
884//(
885// .scan_in(i_dff_q1_1_scanin),
886// .scan_out(i_dff_q1_1_scanout),
887// .clk (l2clk),
888// .din (src_pcx_data_a[89:40]),
889// .dout (q1_dataout[89:40]),
890// .en (arb_qsel1_a),
891// );
892//
893//msff_macro i_dff_q1_0 (width=40, stack=50c)
894//(
895// .scan_in(i_dff_q1_0_scanin),
896// .scan_out(i_dff_q1_0_scanout),
897// .clk (l2clk),
898// .din (src_pcx_data_a[39:0]),
899// .dout (q1_dataout[39:0]),
900// .en (arb_qsel1_a),
901// );
902//
903////assign q0_datain_ca[149:0] =
904//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
905//// (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
906//
907//
908//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
909//(
910// .din0 (src_pcx_data_a[129:90]),
911// .din1 (q1_dataout[129:90]),
912// .sel0 (arb_qsel0_a),
913// .sel1 (arb_shift_a),
914// .dout (q0_datain_a[129:90]),
915// );
916//
917//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
918//(
919// .din0 (src_pcx_data_a[89:40]),
920// .din1 (q1_dataout[89:40]),
921// .sel0 (arb_qsel0_a),
922// .sel1 (arb_shift_a),
923// .dout (q0_datain_a[89:40]),
924// );
925//
926//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
927//(
928// .din0 (src_pcx_data_a[39:0]),
929// .din1 (q1_dataout[39:0]),
930// .sel0 (arb_qsel0_a),
931// .sel1 (arb_shift_a),
932// .dout (q0_datain_a[39:0]),
933// );
934//
935//msff_macro i_dff_q0_2 (width=40, stack=50c)
936//(
937// .scan_in(i_dff_q0_2_scanin),
938// .scan_out(i_dff_q0_2_scanout),
939// .clk (l2clk),
940// .din (q0_datain_a[129:90]),
941// .dout (q0_dataout[129:90]),
942// .en (arb_q0_holdbar_a),
943// );
944//
945//msff_macro i_dff_q0_1 (width=50, stack=50c)
946//(
947// .scan_in(i_dff_q0_1_scanin),
948// .scan_out(i_dff_q0_1_scanout),
949// .clk (l2clk),
950// .din (q0_datain_a[89:40]),
951// .dout (q0_dataout[89:40]),
952// .en (arb_q0_holdbar_a),
953// );
954//
955//msff_macro i_dff_q0_0 (width=40, stack=50c)
956//(
957// .scan_in(i_dff_q0_0_scanin),
958// .scan_out(i_dff_q0_0_scanout),
959// .clk (l2clk),
960// .din (q0_datain_a[39:0]),
961// .dout (q0_dataout[39:0]),
962// .en (arb_q0_holdbar_a),
963// );
964//
965////MUX
966//
967//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
968//(
969// .din0 (q0_dataout[129:90]),
970// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
971// .dout (data_x_[129:90]),
972// );
973//
974//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
975//(
976// .din0 (q0_dataout[89:40]),
977// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
978// .dout (data_x_[89:40]),
979// );
980//
981//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
982//(
983// .din0 (q0_dataout[39:0]),
984// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
985// .dout (data_x_[39:0]),
986// );
987//
988//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c)
989//(
990// .din0 (data_x_[129:90]),
991// .din1 (data_crit_x_[129:90]),
992// .din2 (data_ncrit_x_[129:90]),
993// .dout (data_out_x[129:90])
994//);
995//
996//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c)
997//(
998// .din0 (data_x_[89:40]),
999// .din1 (data_crit_x_[89:40]),
1000// .din2 (data_ncrit_x_[89:40]),
1001// .dout (data_out_x[89:40])
1002//);
1003//
1004//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c)
1005//(
1006// .din0 (data_x_[39:0]),
1007// .din1 (data_crit_x_[39:0]),
1008// .din2 (data_ncrit_x_[39:0]),
1009// .dout (data_out_x[39:0])
1010//);
1011//
1012//inv_macro i_inv_data_out_2 (width=40, stack=50c)
1013//(
1014// .din (data_out_x[129:90]),
1015// .dout (data_out_x_[129:90])
1016// );
1017//
1018//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1019//(
1020// .din (data_out_x[89:40]),
1021// .dout (data_out_x_[89:40])
1022// );
1023//
1024//inv_macro i_inv_data_out_0 (width=40, stack=50c)
1025//(
1026// .din (data_out_x[39:0]),
1027// .dout (data_out_x_[39:0])
1028// );
1029//
1030//// fixscan start:
1031//assign i_dff_grant_x_scanin = scan_in ;
1032//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1033//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1034//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1035//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1036//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1037//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1038//assign scan_out = i_dff_q0_0_scanout ;
1039//// fixscan end:
1040//endmodule
1041// Local Variables:
1042// verilog-library-directories:("." "v")
1043// verilog-library-files:("./v/ccx_new_macro.v")
1044// End:
1045//
1046
1047
1048//
1049// ccx macro
1050//
1051//
1052
1053
1054
1055
1056
1057module pcx_dpsb_ccx_new_macro__type_c_l (
1058 l2clk,
1059 l1clk,
1060 pce0,
1061 pce1,
1062 pce_ov,
1063 se,
1064 stop,
1065 siclk_in,
1066 soclk_in,
1067 scan_in,
1068 grant_a,
1069 qsel0,
1070 shift,
1071 data_a,
1072 data_crit_x_l,
1073 data_ncrit_x_l,
1074 data_x_l,
1075 scan_out);
1076wire so5;
1077wire siclk_out;
1078wire soclk_out;
1079wire l1clk0;
1080wire l1clk1;
1081wire grant_x;
1082wire qsel0_buf;
1083wire shift_buf;
1084
1085input l2clk;
1086input l1clk;
1087input pce0;
1088input pce1;
1089input pce_ov;
1090input se;
1091input stop;
1092input siclk_in;
1093input soclk_in;
1094input scan_in;
1095input grant_a;
1096input qsel0;
1097input shift;
1098input [9:0] data_a;
1099input [9:0] data_crit_x_l;
1100input [9:0] data_ncrit_x_l;
1101output [9:0] data_x_l;
1102output scan_out;
1103cl_dp1_ccxhdr c0 (
1104.si(scan_in),
1105.so(so5),
1106 .l2clk(l2clk),
1107 .pce0(pce0),
1108 .pce1(pce1),
1109 .pce_ov(pce_ov),
1110 .stop(stop),
1111 .siclk_in(siclk_in),
1112 .soclk_in(soclk_in),
1113 .siclk_out(siclk_out),
1114 .soclk_out(soclk_out),
1115 .l1clk0(l1clk0),
1116 .l1clk1(l1clk1),
1117 .se(se),
1118 .l1clk(l1clk),
1119 .grant_a(grant_a),
1120 .grant_x(grant_x),
1121 .qsel0(qsel0),
1122 .qsel0_buf(qsel0_buf),
1123 .shift(shift),
1124 .shift_buf(shift_buf)
1125);
1126
1127
1128
1129
1130
1131
1132ccx_mac_c #(10) mac_c(
1133.siclk(siclk_out),
1134.soclk(soclk_out),
1135.data_a(data_a[9:0]),
1136.data_crit_x_l(data_crit_x_l[9:0]),
1137.data_ncrit_x_l(data_ncrit_x_l[9:0]),
1138.data_x_l(data_x_l[9:0]),
1139.si(so5),
1140.so(scan_out),
1141 .l1clk0(l1clk0),
1142 .l1clk1(l1clk1),
1143 .grant_x(grant_x),
1144 .qsel0_buf(qsel0_buf),
1145 .shift_buf(shift_buf)
1146);
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161endmodule
1162
1163
1164//
1165//// scan renames
1166//assign pce_ov = tcu_pce_ov;
1167//assign stop = tcu_clk_stop;
1168//assign siclk = tcu_aclk;
1169//assign soclk = tcu_bclk;
1170//// end scan
1171//
1172//buff_macro i_buf_grant (width=1, stack=30c)
1173//(
1174// .din (arb_grant_a),
1175// .dout (grant_a),
1176// );
1177//
1178//msff_macro i_dff_grant_x (width=12, stack=30c)
1179//(
1180// .scan_in(i_dff_grant_x_scanin),
1181// .scan_out(i_dff_grant_x_scanout),
1182// .clk (l2clk),
1183// .din ({12{grant_a}}),
1184// .dout (grant_x[11:0]),
1185// .en (1'b1),
1186// );
1187//
1188//
1189//// DATAPATH SECTION
1190//
1191//msff_macro i_dff_q1_2 (width=40, stack=50c)
1192//(
1193// .scan_in(i_dff_q1_2_scanin),
1194// .scan_out(i_dff_q1_2_scanout),
1195// .clk (l2clk),
1196// .din (src_pcx_data_a[129:90]),
1197// .dout (q1_dataout[129:90]),
1198// .en (arb_qsel1_a),
1199// );
1200//
1201//msff_macro i_dff_q1_1 (width=50, stack=50c)
1202//(
1203// .scan_in(i_dff_q1_1_scanin),
1204// .scan_out(i_dff_q1_1_scanout),
1205// .clk (l2clk),
1206// .din (src_pcx_data_a[89:40]),
1207// .dout (q1_dataout[89:40]),
1208// .en (arb_qsel1_a),
1209// );
1210//
1211//msff_macro i_dff_q1_0 (width=40, stack=50c)
1212//(
1213// .scan_in(i_dff_q1_0_scanin),
1214// .scan_out(i_dff_q1_0_scanout),
1215// .clk (l2clk),
1216// .din (src_pcx_data_a[39:0]),
1217// .dout (q1_dataout[39:0]),
1218// .en (arb_qsel1_a),
1219// );
1220//
1221////assign q0_datain_ca[149:0] =
1222//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
1223//// (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
1224//
1225//
1226//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
1227//(
1228// .din0 (src_pcx_data_a[129:90]),
1229// .din1 (q1_dataout[129:90]),
1230// .sel0 (arb_qsel0_a),
1231// .sel1 (arb_shift_a),
1232// .dout (q0_datain_a[129:90]),
1233// );
1234//
1235//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1236//(
1237// .din0 (src_pcx_data_a[89:40]),
1238// .din1 (q1_dataout[89:40]),
1239// .sel0 (arb_qsel0_a),
1240// .sel1 (arb_shift_a),
1241// .dout (q0_datain_a[89:40]),
1242// );
1243//
1244//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
1245//(
1246// .din0 (src_pcx_data_a[39:0]),
1247// .din1 (q1_dataout[39:0]),
1248// .sel0 (arb_qsel0_a),
1249// .sel1 (arb_shift_a),
1250// .dout (q0_datain_a[39:0]),
1251// );
1252//
1253//msff_macro i_dff_q0_2 (width=40, stack=50c)
1254//(
1255// .scan_in(i_dff_q0_2_scanin),
1256// .scan_out(i_dff_q0_2_scanout),
1257// .clk (l2clk),
1258// .din (q0_datain_a[129:90]),
1259// .dout (q0_dataout[129:90]),
1260// .en (arb_q0_holdbar_a),
1261// );
1262//
1263//msff_macro i_dff_q0_1 (width=50, stack=50c)
1264//(
1265// .scan_in(i_dff_q0_1_scanin),
1266// .scan_out(i_dff_q0_1_scanout),
1267// .clk (l2clk),
1268// .din (q0_datain_a[89:40]),
1269// .dout (q0_dataout[89:40]),
1270// .en (arb_q0_holdbar_a),
1271// );
1272//
1273//msff_macro i_dff_q0_0 (width=40, stack=50c)
1274//(
1275// .scan_in(i_dff_q0_0_scanin),
1276// .scan_out(i_dff_q0_0_scanout),
1277// .clk (l2clk),
1278// .din (q0_datain_a[39:0]),
1279// .dout (q0_dataout[39:0]),
1280// .en (arb_q0_holdbar_a),
1281// );
1282//
1283////MUX
1284//
1285//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
1286//(
1287// .din0 (q0_dataout[129:90]),
1288// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
1289// .dout (data_x_[129:90]),
1290// );
1291//
1292//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1293//(
1294// .din0 (q0_dataout[89:40]),
1295// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1296// .dout (data_x_[89:40]),
1297// );
1298//
1299//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
1300//(
1301// .din0 (q0_dataout[39:0]),
1302// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
1303// .dout (data_x_[39:0]),
1304// );
1305//
1306//
1307//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c)
1308//(
1309// .din0 (data_x_[129:90]),
1310// .din1 (data_prev_x_[129:90]),
1311// .dout (data_out_x[129:90])
1312// );
1313//
1314//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c)
1315//(
1316// .din0 (data_x_[89:40]),
1317// .din1 (data_prev_x_[89:40]),
1318// .dout (data_out_x[89:40])
1319// );
1320//
1321//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c)
1322//(
1323// .din0 (data_x_[39:0]),
1324// .din1 (data_prev_x_[39:0]),
1325// .dout (data_out_x[39:0])
1326// );
1327//
1328//inv_macro i_inv_data_out_2 (width=40, stack=50c)
1329//(
1330// .din (data_out_x[129:90]),
1331// .dout (data_out_x_[129:90])
1332// );
1333//
1334//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1335//(
1336// .din (data_out_x[89:40]),
1337// .dout (data_out_x_[89:40])
1338// );
1339//
1340//inv_macro i_inv_data_out_0 (width=40, stack=50c)
1341//(
1342// .din (data_out_x[39:0]),
1343// .dout (data_out_x_[39:0])
1344// );
1345//
1346//// fixscan start:
1347//assign i_dff_grant_x_scanin = scan_in ;
1348//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1349//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1350//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1351//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1352//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1353//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1354//assign scan_out = i_dff_q0_0_scanout ;
1355//// fixscan end:
1356//endmodule
1357//
1358// Local Variables:
1359// verilog-library-directories:("." "v")
1360// verilog-library-files:("./v/ccx_new_macro.v")
1361// End:
1362//
1363
1364
1365//
1366// ccx macro
1367//
1368//
1369
1370
1371
1372
1373
1374module pcx_dpsb_ccx_new_macro__type_b_r (
1375 l2clk,
1376 l1clk,
1377 pce0,
1378 pce1,
1379 pce_ov,
1380 se,
1381 stop,
1382 siclk_in,
1383 soclk_in,
1384 scan_in,
1385 grant_a,
1386 qsel0,
1387 shift,
1388 data_a,
1389 data_prev_x_l,
1390 data_x_l,
1391 scan_out);
1392wire so5;
1393wire siclk_out;
1394wire soclk_out;
1395wire l1clk0;
1396wire l1clk1;
1397wire grant_x;
1398wire qsel0_buf;
1399wire shift_buf;
1400
1401input l2clk;
1402input l1clk;
1403input pce0;
1404input pce1;
1405input pce_ov;
1406input se;
1407input stop;
1408input siclk_in;
1409input soclk_in;
1410input scan_in;
1411input grant_a;
1412input qsel0;
1413input shift;
1414input [9:0] data_a;
1415input [9:0] data_prev_x_l;
1416output [9:0] data_x_l;
1417output scan_out;
1418cl_dp1_ccxhdr c0 (
1419.si(scan_in),
1420.so(so5),
1421 .l2clk(l2clk),
1422 .pce0(pce0),
1423 .pce1(pce1),
1424 .pce_ov(pce_ov),
1425 .stop(stop),
1426 .siclk_in(siclk_in),
1427 .soclk_in(soclk_in),
1428 .siclk_out(siclk_out),
1429 .soclk_out(soclk_out),
1430 .l1clk0(l1clk0),
1431 .l1clk1(l1clk1),
1432 .se(se),
1433 .l1clk(l1clk),
1434 .grant_a(grant_a),
1435 .grant_x(grant_x),
1436 .qsel0(qsel0),
1437 .qsel0_buf(qsel0_buf),
1438 .shift(shift),
1439 .shift_buf(shift_buf)
1440);
1441
1442
1443
1444
1445
1446
1447ccx_mac_b #(10) mac_b(
1448.siclk(siclk_out),
1449.soclk(soclk_out),
1450.data_a(data_a[9:0]),
1451.data_prev_x_l(data_prev_x_l[9:0]),
1452.data_x_l(data_x_l[9:0]),
1453.si(so5),
1454.so(scan_out),
1455 .l1clk0(l1clk0),
1456 .l1clk1(l1clk1),
1457 .grant_x(grant_x),
1458 .qsel0_buf(qsel0_buf),
1459 .shift_buf(shift_buf)
1460);
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475endmodule
1476
1477//
1478//// scan renames
1479//assign pce_ov = tcu_pce_ov;
1480//assign stop = tcu_clk_stop;
1481//assign siclk = ccx_aclk;
1482//assign soclk = ccx_bclk;
1483//// end scan
1484//
1485//// buffer the grant signal
1486//
1487//buff_macro i_buf_grant (width=1, stack=30c)
1488//(
1489// .din (arb_grant_a),
1490// .dout (grant_a),
1491// );
1492//
1493//msff_macro i_dff_grant_x (width=12, stack=30c)
1494//(
1495// .scan_in(i_dff_grant_x_scanin),
1496// .scan_out(i_dff_grant_x_scanout),
1497// .clk (l2clk),
1498// .din ({12{grant_a}}),
1499// .dout (grant_x[11:0]),
1500// .en (1'b1),
1501// );
1502//
1503//
1504//// DATAPATH SECTION
1505//
1506//msff_macro i_dff_q1_2 (width=40, stack=50c)
1507//(
1508// .scan_in(i_dff_q1_2_scanin),
1509// .scan_out(i_dff_q1_2_scanout),
1510// .clk (l2clk),
1511// .din (src_pcx_data_a[129:90]),
1512// .dout (q1_dataout[129:90]),
1513// .en (arb_qsel1_a),
1514// );
1515//
1516//msff_macro i_dff_q1_1 (width=50, stack=50c)
1517//(
1518// .scan_in(i_dff_q1_1_scanin),
1519// .scan_out(i_dff_q1_1_scanout),
1520// .clk (l2clk),
1521// .din (src_pcx_data_a[89:40]),
1522// .dout (q1_dataout[89:40]),
1523// .en (arb_qsel1_a),
1524// );
1525//
1526//msff_macro i_dff_q1_0 (width=40, stack=50c)
1527//(
1528// .scan_in(i_dff_q1_0_scanin),
1529// .scan_out(i_dff_q1_0_scanout),
1530// .clk (l2clk),
1531// .din (src_pcx_data_a[39:0]),
1532// .dout (q1_dataout[39:0]),
1533// .en (arb_qsel1_a),
1534// );
1535//
1536////assign q0_datain_ca[129:0] =
1537//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
1538//// (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
1539//
1540//
1541//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
1542//(
1543// .din0 (src_pcx_data_a[129:90]),
1544// .din1 (q1_dataout[129:90]),
1545// .sel0 (arb_qsel0_a),
1546// .sel1 (arb_shift_a),
1547// .dout (q0_datain_a[129:90]),
1548// );
1549//
1550//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1551//(
1552// .din0 (src_pcx_data_a[89:40]),
1553// .din1 (q1_dataout[89:40]),
1554// .sel0 (arb_qsel0_a),
1555// .sel1 (arb_shift_a),
1556// .dout (q0_datain_a[89:40]),
1557// );
1558//
1559//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
1560//(
1561// .din0 (src_pcx_data_a[39:0]),
1562// .din1 (q1_dataout[39:0]),
1563// .sel0 (arb_qsel0_a),
1564// .sel1 (arb_shift_a),
1565// .dout (q0_datain_a[39:0]),
1566// );
1567//
1568//msff_macro i_dff_q0_2 (width=40, stack=50c)
1569//(
1570// .scan_in(i_dff_q0_2_scanin),
1571// .scan_out(i_dff_q0_2_scanout),
1572// .clk (l2clk),
1573// .din (q0_datain_a[129:90]),
1574// .dout (q0_dataout[129:90]),
1575// .en (arb_q0_holdbar_a),
1576// );
1577//
1578//msff_macro i_dff_q0_1 (width=50, stack=50c)
1579//(
1580// .scan_in(i_dff_q0_1_scanin),
1581// .scan_out(i_dff_q0_1_scanout),
1582// .clk (l2clk),
1583// .din (q0_datain_a[89:40]),
1584// .dout (q0_dataout[89:40]),
1585// .en (arb_q0_holdbar_a),
1586// );
1587//
1588//msff_macro i_dff_q0_0 (width=40, stack=50c)
1589//(
1590// .scan_in(i_dff_q0_0_scanin),
1591// .scan_out(i_dff_q0_0_scanout),
1592// .clk (l2clk),
1593// .din (q0_datain_a[39:0]),
1594// .dout (q0_dataout[39:0]),
1595// .en (arb_q0_holdbar_a),
1596// );
1597//
1598//// MUX
1599//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
1600//(
1601// .din0 (q0_dataout[129:90]),
1602// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
1603// .dout (data_out_x_[129:90]),
1604// );
1605//
1606//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1607//(
1608// .din0 (q0_dataout[89:40]),
1609// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1610// .dout (data_out_x_[89:40]),
1611// );
1612//
1613//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
1614//(
1615// .din0 (q0_dataout[39:0]),
1616// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
1617// .dout (data_out_x_[39:0]),
1618// );
1619//
1620//// fixscan start:
1621//assign i_dff_grant_x_scanin = scan_in ;
1622//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1623//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1624//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1625//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1626//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1627//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1628//assign scan_out = i_dff_q0_0_scanout ;
1629//// fixscan end:
1630//endmodule
1631//
1632// Local Variables:
1633// verilog-library-directories:("." "v")
1634// verilog-library-files:("./v/ccx_new_macro.v")
1635// End:
1636//
1637
1638
1639
1640//
1641// ccx macro
1642//
1643//
1644
1645
1646
1647
1648
1649module pcx_dpsb_ccx_new_macro__type_a (
1650 l2clk,
1651 l1clk,
1652 pce0,
1653 pce1,
1654 pce_ov,
1655 se,
1656 stop,
1657 siclk_in,
1658 soclk_in,
1659 scan_in,
1660 grant_a,
1661 qsel0,
1662 shift,
1663 data_a,
1664 data_x_l,
1665 scan_out);
1666wire so5;
1667wire siclk_out;
1668wire soclk_out;
1669wire l1clk0;
1670wire l1clk1;
1671wire grant_x;
1672wire qsel0_buf;
1673wire shift_buf;
1674
1675input l2clk;
1676input l1clk;
1677input pce0;
1678input pce1;
1679input pce_ov;
1680input se;
1681input stop;
1682input siclk_in;
1683input soclk_in;
1684input scan_in;
1685input grant_a;
1686input qsel0;
1687input shift;
1688input [9:0] data_a;
1689output [9:0] data_x_l;
1690output scan_out;
1691cl_dp1_ccxhdr c0 (
1692.si(scan_in),
1693.so(so5),
1694 .l2clk(l2clk),
1695 .pce0(pce0),
1696 .pce1(pce1),
1697 .pce_ov(pce_ov),
1698 .stop(stop),
1699 .siclk_in(siclk_in),
1700 .soclk_in(soclk_in),
1701 .siclk_out(siclk_out),
1702 .soclk_out(soclk_out),
1703 .l1clk0(l1clk0),
1704 .l1clk1(l1clk1),
1705 .se(se),
1706 .l1clk(l1clk),
1707 .grant_a(grant_a),
1708 .grant_x(grant_x),
1709 .qsel0(qsel0),
1710 .qsel0_buf(qsel0_buf),
1711 .shift(shift),
1712 .shift_buf(shift_buf)
1713);
1714
1715
1716
1717
1718
1719
1720ccx_mac_a #(10) mac_a(
1721.siclk(siclk_out),
1722.soclk(soclk_out),
1723.data_a(data_a[9:0]),
1724.data_x_l(data_x_l[9:0]),
1725.si(so5),
1726.so(scan_out),
1727 .l1clk0(l1clk0),
1728 .l1clk1(l1clk1),
1729 .grant_x(grant_x),
1730 .qsel0_buf(qsel0_buf),
1731 .shift_buf(shift_buf)
1732);
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747endmodule
1748
1749
1750
1751`endif // `ifndef FPGA
1752
1753`ifdef FPGA
1754`timescale 1 ns / 100 ps
1755module pcx_dpsb(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a,
1756 arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a,
1757 arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a,
1758 spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a,
1759 spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a,
1760 tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);
1761
1762 output [129:0] pcx_scache_data_x_;
1763 input [7:0] arb_grant_l_a;
1764 input [7:0] arb_q0_holdbar_l_a;
1765 input [7:0] arb_qsel0_l_a;
1766 input [7:0] arb_qsel1_l_a;
1767 input [7:0] arb_shift_l_a;
1768 input [7:0] arb_grant_r_a;
1769 input [7:0] arb_q0_holdbar_r_a;
1770 input [7:0] arb_qsel0_r_a;
1771 input [7:0] arb_qsel1_r_a;
1772 input [7:0] arb_shift_r_a;
1773 input [129:0] spc0_pcx_data_a;
1774 input [129:0] spc1_pcx_data_a;
1775 input [129:0] spc2_pcx_data_a;
1776 input [129:0] spc3_pcx_data_a;
1777 input [129:0] spc4_pcx_data_a;
1778 input [129:0] spc5_pcx_data_a;
1779 input [129:0] spc6_pcx_data_a;
1780 input [129:0] spc7_pcx_data_a;
1781 input tcu_scan_en;
1782 input l2clk;
1783 input tcu_pce_ov;
1784 input ccx_aclk;
1785 input ccx_bclk;
1786 input scan_in;
1787 output scan_out;
1788
1789 wire [129:0] all_ones;
1790 wire [4:0] mac0_rep_in;
1791 wire [3:0] arb_grant_l_a_rep;
1792 wire [3:0] arb_qsel0_l_a_rep;
1793 wire [3:0] arb_qsel1_l_a_rep;
1794 wire [3:0] arb_shift_l_a_rep;
1795 wire [3:0] arb_q0_holdbar_l_a_rep;
1796 wire [4:0] mac0_rep_out;
1797 wire [4:0] mac1_rep_in;
1798 wire [4:0] mac1_rep_out;
1799 wire [4:0] mac2_rep_in;
1800 wire [4:0] mac2_rep_out;
1801 wire [4:0] mac3_rep_in;
1802 wire [4:0] mac3_rep_out;
1803 wire [4:0] mac4_rep_in;
1804 wire [7:4] arb_grant_r_a_rep;
1805 wire [7:4] arb_q0_holdbar_r_a_rep;
1806 wire [7:4] arb_qsel0_r_a_rep;
1807 wire [7:4] arb_qsel1_r_a_rep;
1808 wire [7:4] arb_shift_r_a_rep;
1809 wire [4:0] mac4_rep_out;
1810 wire [4:0] mac5_rep_in;
1811 wire [4:0] mac5_rep_out;
1812 wire [4:0] mac6_rep_in;
1813 wire [4:0] mac6_rep_out;
1814 wire scan_rep_in;
1815 wire [129:0] col0_data_x_;
1816 wire tcu_scan_en_out_0_unused;
1817 wire tcu_pce_ov_out_0_unused;
1818 wire ccx_aclk_out_0_unused;
1819 wire ccx_bclk_out_0_unused;
1820 wire pcx_mac0_scanin;
1821 wire pcx_mac0_scanout;
1822 wire [6:1] tcu_scan_en_out;
1823 wire [6:1] tcu_pce_ov_out;
1824 wire [6:1] ccx_aclk_out;
1825 wire [6:1] ccx_bclk_out;
1826 wire [129:0] col2_data_x_;
1827 wire pcx_mac1_scanin;
1828 wire pcx_mac1_scanout;
1829 wire [129:0] col3_data_x_;
1830 wire pcx_mac2_scanin;
1831 wire pcx_mac2_scanout;
1832 wire [129:0] col4_data_x_;
1833 wire pcx_mac3_scanin;
1834 wire pcx_mac3_scanout;
1835 wire [129:0] col5_data_x_;
1836 wire pcx_mac4_scanin;
1837 wire pcx_mac4_scanout;
1838 wire [129:0] col6_data_x_;
1839 wire pcx_mac5_scanin;
1840 wire pcx_mac5_scanout;
1841 wire [129:0] col7_data_x_;
1842 wire pcx_mac6_scanin;
1843 wire pcx_mac6_scanout;
1844 wire tcu_scan_en_out_7_unused;
1845 wire tcu_pce_ov_out_7_unused;
1846 wire ccx_aclk_out_7_unused;
1847 wire ccx_bclk_out_7_unused;
1848 wire pcx_mac7_scanin;
1849 wire pcx_mac7_scanout;
1850 wire [7:4] arb_grant_l_a_unused;
1851 wire [7:4] arb_q0_holdbar_l_a_unused;
1852 wire [7:4] arb_qsel0_l_a_unused;
1853 wire [7:4] arb_qsel1_l_a_unused;
1854 wire [7:4] arb_shift_l_a_unused;
1855 wire [3:0] arb_grant_r_a_unused;
1856 wire [3:0] arb_q0_holdbar_r_a_unused;
1857 wire [3:0] arb_qsel0_r_a_unused;
1858 wire [3:0] arb_qsel1_r_a_unused;
1859 wire [3:0] arb_shift_r_a_unused;
1860 wire scan_rep_out;
1861
1862 assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
1863 assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0],
1864 arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
1865 assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0],
1866 arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0],
1867 arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
1868 assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2],
1869 arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
1870 assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2],
1871 arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
1872 } = mac1_rep_out[4:0];
1873 assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1],
1874 arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
1875 assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1],
1876 arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
1877 } = mac2_rep_out[4:0];
1878 assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3],
1879 arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
1880 assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3],
1881 arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
1882 } = mac3_rep_out[4:0];
1883 assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5],
1884 arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
1885 assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5],
1886 arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
1887 } = mac4_rep_out[4:0];
1888 assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7],
1889 arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
1890 assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7],
1891 arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
1892 } = mac5_rep_out[4:0];
1893 assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4],
1894 arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
1895 assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4],
1896 arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
1897 } = mac6_rep_out[4:0];
1898 assign scan_rep_in = scan_in;
1899 assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
1900 assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
1901 assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
1902 assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
1903 assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
1904 assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
1905 assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
1906 assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
1907 assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
1908 assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
1909 assign pcx_mac0_scanin = scan_rep_out;
1910 assign pcx_mac1_scanin = pcx_mac0_scanout;
1911 assign pcx_mac2_scanin = pcx_mac1_scanout;
1912 assign pcx_mac3_scanin = pcx_mac2_scanout;
1913 assign pcx_mac4_scanin = pcx_mac3_scanout;
1914 assign pcx_mac5_scanin = pcx_mac4_scanout;
1915 assign pcx_mac6_scanin = pcx_mac5_scanout;
1916 assign pcx_mac7_scanin = pcx_mac6_scanout;
1917 assign scan_out = pcx_mac7_scanout;
1918
1919 pcx_rep_dp pcx_rep(
1920 .mac0_rep_out (mac0_rep_out[4:0]),
1921 .mac1_rep_out (mac1_rep_out[4:0]),
1922 .mac2_rep_out (mac2_rep_out[4:0]),
1923 .mac3_rep_out (mac3_rep_out[4:0]),
1924 .mac4_rep_out (mac4_rep_out[4:0]),
1925 .mac5_rep_out (mac5_rep_out[4:0]),
1926 .mac6_rep_out (mac6_rep_out[4:0]),
1927 .scan_rep_out (scan_rep_out),
1928 .mac0_rep_in (mac0_rep_in[4:0]),
1929 .mac1_rep_in (mac1_rep_in[4:0]),
1930 .mac2_rep_in (mac2_rep_in[4:0]),
1931 .mac3_rep_in (mac3_rep_in[4:0]),
1932 .mac4_rep_in (mac4_rep_in[4:0]),
1933 .mac5_rep_in (mac5_rep_in[4:0]),
1934 .mac6_rep_in (mac6_rep_in[4:0]),
1935 .scan_rep_in (scan_rep_in));
1936 pcx_mbl_dp pcx_mac0(
1937 .data_out_x_ (col0_data_x_[129:0]),
1938 .tcu_scan_en_out (tcu_scan_en_out_0_unused),
1939 .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
1940 .ccx_aclk_out (ccx_aclk_out_0_unused),
1941 .ccx_bclk_out (ccx_bclk_out_0_unused),
1942 .arb_grant_a (arb_grant_l_a_rep[0]),
1943 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
1944 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
1945 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
1946 .arb_shift_a (arb_shift_l_a_rep[0]),
1947 .src_pcx_data_a (spc0_pcx_data_a[129:0]),
1948 .data_prev_x_ (all_ones[129:0]),
1949 .scan_in (pcx_mac0_scanin),
1950 .scan_out (pcx_mac0_scanout),
1951 .l2clk (l2clk),
1952 .tcu_scan_en (tcu_scan_en_out[1]),
1953 .tcu_pce_ov (tcu_pce_ov_out[1]),
1954 .ccx_aclk (ccx_aclk_out[1]),
1955 .ccx_bclk (ccx_bclk_out[1]));
1956 pcx_mcl_dp pcx_mac1(
1957 .data_out_x_ (pcx_scache_data_x_[129:0]),
1958 .tcu_scan_en_out (tcu_scan_en_out[1]),
1959 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
1960 .ccx_aclk_out (ccx_aclk_out[1]),
1961 .ccx_bclk_out (ccx_bclk_out[1]),
1962 .arb_grant_a (arb_grant_l_a_rep[2]),
1963 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
1964 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
1965 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
1966 .arb_shift_a (arb_shift_l_a_rep[2]),
1967 .src_pcx_data_a (spc2_pcx_data_a[129:0]),
1968 .data_crit_x_ (col2_data_x_[129:0]),
1969 .data_ncrit_x_ (col0_data_x_[129:0]),
1970 .scan_in (pcx_mac1_scanin),
1971 .scan_out (pcx_mac1_scanout),
1972 .l2clk (l2clk),
1973 .tcu_scan_en (tcu_scan_en_out[2]),
1974 .tcu_pce_ov (tcu_pce_ov_out[2]),
1975 .ccx_aclk (ccx_aclk_out[2]),
1976 .ccx_bclk (ccx_bclk_out[2]));
1977 pcx_mbr_dp pcx_mac2(
1978 .data_out_x_ (col2_data_x_[129:0]),
1979 .tcu_scan_en_out (tcu_scan_en_out[2]),
1980 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
1981 .ccx_aclk_out (ccx_aclk_out[2]),
1982 .ccx_bclk_out (ccx_bclk_out[2]),
1983 .arb_grant_a (arb_grant_l_a_rep[1]),
1984 .arb_qsel0_a (arb_qsel0_l_a_rep[1]),
1985 .arb_qsel1_a (arb_qsel1_l_a_rep[1]),
1986 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]),
1987 .arb_shift_a (arb_shift_l_a_rep[1]),
1988 .src_pcx_data_a (spc1_pcx_data_a[129:0]),
1989 .data_prev_x_ (col3_data_x_[129:0]),
1990 .scan_in (pcx_mac2_scanin),
1991 .scan_out (pcx_mac2_scanout),
1992 .l2clk (l2clk),
1993 .tcu_scan_en (tcu_scan_en_out[3]),
1994 .tcu_pce_ov (tcu_pce_ov_out[3]),
1995 .ccx_aclk (ccx_aclk_out[3]),
1996 .ccx_bclk (ccx_bclk_out[3]));
1997 pcx_mbr_dp pcx_mac3(
1998 .data_out_x_ (col3_data_x_[129:0]),
1999 .tcu_scan_en_out (tcu_scan_en_out[3]),
2000 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
2001 .ccx_aclk_out (ccx_aclk_out[3]),
2002 .ccx_bclk_out (ccx_bclk_out[3]),
2003 .arb_grant_a (arb_grant_l_a_rep[3]),
2004 .arb_qsel0_a (arb_qsel0_l_a_rep[3]),
2005 .arb_qsel1_a (arb_qsel1_l_a_rep[3]),
2006 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]),
2007 .arb_shift_a (arb_shift_l_a_rep[3]),
2008 .src_pcx_data_a (spc3_pcx_data_a[129:0]),
2009 .data_prev_x_ (col4_data_x_[129:0]),
2010 .scan_in (pcx_mac3_scanin),
2011 .scan_out (pcx_mac3_scanout),
2012 .l2clk (l2clk),
2013 .tcu_scan_en (tcu_scan_en),
2014 .tcu_pce_ov (tcu_pce_ov),
2015 .ccx_aclk (ccx_aclk),
2016 .ccx_bclk (ccx_bclk));
2017 pcx_mbr_dp pcx_mac4(
2018 .data_out_x_ (col4_data_x_[129:0]),
2019 .tcu_scan_en_out (tcu_scan_en_out[4]),
2020 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
2021 .ccx_aclk_out (ccx_aclk_out[4]),
2022 .ccx_bclk_out (ccx_bclk_out[4]),
2023 .arb_grant_a (arb_grant_r_a_rep[5]),
2024 .arb_qsel0_a (arb_qsel0_r_a_rep[5]),
2025 .arb_qsel1_a (arb_qsel1_r_a_rep[5]),
2026 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]),
2027 .arb_shift_a (arb_shift_r_a_rep[5]),
2028 .src_pcx_data_a (spc5_pcx_data_a[129:0]),
2029 .data_prev_x_ (col5_data_x_[129:0]),
2030 .scan_in (pcx_mac4_scanin),
2031 .scan_out (pcx_mac4_scanout),
2032 .l2clk (l2clk),
2033 .tcu_scan_en (tcu_scan_en_out[3]),
2034 .tcu_pce_ov (tcu_pce_ov_out[3]),
2035 .ccx_aclk (ccx_aclk_out[3]),
2036 .ccx_bclk (ccx_bclk_out[3]));
2037 pcx_mbr_dp pcx_mac5(
2038 .data_out_x_ (col5_data_x_[129:0]),
2039 .tcu_scan_en_out (tcu_scan_en_out[5]),
2040 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
2041 .ccx_aclk_out (ccx_aclk_out[5]),
2042 .ccx_bclk_out (ccx_bclk_out[5]),
2043 .arb_grant_a (arb_grant_r_a_rep[7]),
2044 .arb_qsel0_a (arb_qsel0_r_a_rep[7]),
2045 .arb_qsel1_a (arb_qsel1_r_a_rep[7]),
2046 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]),
2047 .arb_shift_a (arb_shift_r_a_rep[7]),
2048 .src_pcx_data_a (spc7_pcx_data_a[129:0]),
2049 .data_prev_x_ (col6_data_x_[129:0]),
2050 .scan_in (pcx_mac5_scanin),
2051 .scan_out (pcx_mac5_scanout),
2052 .l2clk (l2clk),
2053 .tcu_scan_en (tcu_scan_en_out[4]),
2054 .tcu_pce_ov (tcu_pce_ov_out[4]),
2055 .ccx_aclk (ccx_aclk_out[4]),
2056 .ccx_bclk (ccx_bclk_out[4]));
2057 pcx_mbr_dp pcx_mac6(
2058 .data_out_x_ (col6_data_x_[129:0]),
2059 .tcu_scan_en_out (tcu_scan_en_out[6]),
2060 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
2061 .ccx_aclk_out (ccx_aclk_out[6]),
2062 .ccx_bclk_out (ccx_bclk_out[6]),
2063 .arb_grant_a (arb_grant_r_a_rep[4]),
2064 .arb_qsel0_a (arb_qsel0_r_a_rep[4]),
2065 .arb_qsel1_a (arb_qsel1_r_a_rep[4]),
2066 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[4]),
2067 .arb_shift_a (arb_shift_r_a_rep[4]),
2068 .src_pcx_data_a (spc4_pcx_data_a[129:0]),
2069 .data_prev_x_ (col7_data_x_[129:0]),
2070 .scan_in (pcx_mac6_scanin),
2071 .scan_out (pcx_mac6_scanout),
2072 .l2clk (l2clk),
2073 .tcu_scan_en (tcu_scan_en_out[5]),
2074 .tcu_pce_ov (tcu_pce_ov_out[5]),
2075 .ccx_aclk (ccx_aclk_out[5]),
2076 .ccx_bclk (ccx_bclk_out[5]));
2077 pcx_mar_dp pcx_mac7(
2078 .data_out_x_ (col7_data_x_[129:0]),
2079 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
2080 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
2081 .ccx_aclk_out (ccx_aclk_out_7_unused),
2082 .ccx_bclk_out (ccx_bclk_out_7_unused),
2083 .arb_grant_a (arb_grant_r_a[6]),
2084 .arb_qsel0_a (arb_qsel0_r_a[6]),
2085 .arb_qsel1_a (arb_qsel1_r_a[6]),
2086 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[6]),
2087 .arb_shift_a (arb_shift_r_a[6]),
2088 .src_pcx_data_a (spc6_pcx_data_a[129:0]),
2089 .scan_in (pcx_mac7_scanin),
2090 .scan_out (pcx_mac7_scanout),
2091 .l2clk (l2clk),
2092 .tcu_scan_en (tcu_scan_en_out[6]),
2093 .tcu_pce_ov (tcu_pce_ov_out[6]),
2094 .ccx_aclk (ccx_aclk_out[6]),
2095 .ccx_bclk (ccx_bclk_out[6]));
2096endmodule
2097
2098
2099`endif // `ifdef FPGA
2100
Full OpenSPARC design & verification tarball including full HDL.