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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / ccx / rtl / pcx_dpsg.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: pcx_dpsg.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifndef FPGA
36module pcx_dpsg (
37 pcx_scache_data_x_,
38 arb_grant_l_a,
39 arb_q0_holdbar_l_a,
40 arb_qsel0_l_a,
41 arb_qsel1_l_a,
42 arb_shift_l_a,
43 arb_grant_r_a,
44 arb_q0_holdbar_r_a,
45 arb_qsel0_r_a,
46 arb_qsel1_r_a,
47 arb_shift_r_a,
48 spc0_pcx_data_a,
49 spc1_pcx_data_a,
50 spc2_pcx_data_a,
51 spc3_pcx_data_a,
52 spc4_pcx_data_a,
53 spc5_pcx_data_a,
54 spc6_pcx_data_a,
55 spc7_pcx_data_a,
56 tcu_scan_en,
57 l2clk,
58 tcu_pce_ov,
59 ccx_aclk,
60 ccx_bclk,
61 scan_in,
62 scan_out);
63wire [129:0] all_ones;
64wire [4:0] mac0_rep_in;
65wire [3:0] arb_grant_l_a_rep;
66wire [3:0] arb_qsel0_l_a_rep;
67wire [3:0] arb_qsel1_l_a_rep;
68wire [3:0] arb_shift_l_a_rep;
69wire [3:0] arb_q0_holdbar_l_a_rep;
70wire [4:0] mac0_rep_out;
71wire [4:0] mac1_rep_in;
72wire [4:0] mac1_rep_out;
73wire [4:0] mac2_rep_in;
74wire [4:0] mac2_rep_out;
75wire [4:0] mac3_rep_in;
76wire [4:0] mac3_rep_out;
77wire [4:0] mac4_rep_in;
78wire [7:4] arb_grant_r_a_rep;
79wire [7:4] arb_q0_holdbar_r_a_rep;
80wire [7:4] arb_qsel0_r_a_rep;
81wire [7:4] arb_qsel1_r_a_rep;
82wire [7:4] arb_shift_r_a_rep;
83wire [4:0] mac4_rep_out;
84wire [4:0] mac5_rep_in;
85wire [4:0] mac5_rep_out;
86wire [4:0] mac6_rep_in;
87wire [4:0] mac6_rep_out;
88wire scan_rep_in;
89wire [129:0] col0_data_x_;
90wire tcu_scan_en_out_0_unused;
91wire tcu_pce_ov_out_0_unused;
92wire ccx_aclk_out_0_unused;
93wire ccx_bclk_out_0_unused;
94wire pcx_mac0_scanin;
95wire pcx_mac0_scanout;
96wire [6:1] tcu_scan_en_out;
97wire [6:1] tcu_pce_ov_out;
98wire [6:1] ccx_aclk_out;
99wire [6:1] ccx_bclk_out;
100wire [129:0] col1_data_x_;
101wire pcx_mac1_scanin;
102wire pcx_mac1_scanout;
103wire [129:0] col2_data_x_;
104wire pcx_mac2_scanin;
105wire pcx_mac2_scanout;
106wire [129:0] col3_data_x_;
107wire pcx_mac3_scanin;
108wire pcx_mac3_scanout;
109wire [129:0] col4_data_x_;
110wire pcx_mac4_scanin;
111wire pcx_mac4_scanout;
112wire [129:0] col5_data_x_;
113wire pcx_mac5_scanin;
114wire pcx_mac5_scanout;
115wire [129:0] col7_data_x_;
116wire pcx_mac6_scanin;
117wire pcx_mac6_scanout;
118wire tcu_scan_en_out_7_unused;
119wire tcu_pce_ov_out_7_unused;
120wire ccx_aclk_out_7_unused;
121wire ccx_bclk_out_7_unused;
122wire pcx_mac7_scanin;
123wire pcx_mac7_scanout;
124wire [7:4] arb_grant_l_a_unused;
125wire [7:4] arb_q0_holdbar_l_a_unused;
126wire [7:4] arb_qsel0_l_a_unused;
127wire [7:4] arb_qsel1_l_a_unused;
128wire [7:4] arb_shift_l_a_unused;
129wire [3:0] arb_grant_r_a_unused;
130wire [3:0] arb_q0_holdbar_r_a_unused;
131wire [3:0] arb_qsel0_r_a_unused;
132wire [3:0] arb_qsel1_r_a_unused;
133wire [3:0] arb_shift_r_a_unused;
134wire scan_rep_out;
135
136
137// Beginning of automatic outputs (from unused autoinst outputs)
138output [129:0] pcx_scache_data_x_; // From mac3 of pcx_mcr_dp.v
139// End of automatics
140
141// Beginning of automatic inputs (from unused autoinst inputs)
142input [7:0] arb_grant_l_a; // To mac0 of pcx_mar_dp.v, ...
143input [7:0] arb_q0_holdbar_l_a; // To mac0 of pcx_mar_dp.v, ...
144input [7:0] arb_qsel0_l_a; // To mac0 of pcx_mar_dp.v, ...
145input [7:0] arb_qsel1_l_a; // To mac0 of pcx_mar_dp.v, ...
146input [7:0] arb_shift_l_a; // To mac0 of pcx_mar_dp.v, ...
147input [7:0] arb_grant_r_a; // To mac0 of pcx_mar_dp.v, ...
148input [7:0] arb_q0_holdbar_r_a; // To mac0 of pcx_mar_dp.v, ...
149input [7:0] arb_qsel0_r_a; // To mac0 of pcx_mar_dp.v, ...
150input [7:0] arb_qsel1_r_a; // To mac0 of pcx_mar_dp.v, ...
151input [7:0] arb_shift_r_a; // To mac0 of pcx_mar_dp.v, ...
152input [129:0] spc0_pcx_data_a; // To mac0 of pcx_mar_dp.v
153input [129:0] spc1_pcx_data_a; // To mac1 of pcx_mbr_dp.v
154input [129:0] spc2_pcx_data_a; // To mac2 of pcx_mbr_dp.v
155input [129:0] spc3_pcx_data_a; // To mac3 of pcx_mcr_dp.v
156input [129:0] spc4_pcx_data_a; // To mac4 of pcx_mbl_dp.v
157input [129:0] spc5_pcx_data_a; // To mac5 of pcx_mbl_dp.v
158input [129:0] spc6_pcx_data_a; // To mac6 of pcx_mbl_dp.v
159input [129:0] spc7_pcx_data_a; // To mac7 of pcx_mal_dp.v
160// End of automatics
161// globals
162input tcu_scan_en ;
163input l2clk;
164input tcu_pce_ov; // scan signals
165input ccx_aclk;
166input ccx_bclk;
167input scan_in;
168output scan_out;
169
170
171// sparc0 sparc2 sparc1 sparc3 sparc5 sparc7 sparc4 sparc6
172// | | | | | | | |
173// v v v v v v v v
174// mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7
175// al bl bl bl bl bl cr br
176// |
177// ------buf------------------------------
178// |
179// v
180// to sctag
181
182assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
183
184// mac0 arb inputs go through 1 buffer
185assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
186 arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};
187
188assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
189 arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
190
191// mac1 arb input go through 1 buffer
192assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
193 arb_qsel1_l_a[2],arb_shift_l_a[2]};
194
195assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
196 arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];
197
198// mac2 arb inputs go through 2 buffers
199assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
200 arb_qsel1_l_a[1],arb_shift_l_a[1]};
201
202assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
203 arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];
204
205// mac3 inputs go through 2 buffers
206assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
207 arb_qsel1_l_a[3],arb_shift_l_a[3]};
208
209assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
210 arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];
211
212// mac4 inputs go through 2 buffers
213assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
214 arb_qsel1_r_a[5],arb_shift_r_a[5]};
215
216assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
217 arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];
218
219// mac5 inputs go through 1 buffer
220assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
221 arb_qsel1_r_a[7],arb_shift_r_a[7]};
222
223assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
224 arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];
225
226// mac6 inputs go through 1 buffer
227assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
228 arb_qsel1_r_a[4],arb_shift_r_a[4]};
229
230assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
231 arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];
232
233assign scan_rep_in = scan_in;
234
235
236
237pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
238 .mac1_rep_out(mac1_rep_out[4:0]),
239 .mac2_rep_out(mac2_rep_out[4:0]),
240 .mac3_rep_out(mac3_rep_out[4:0]),
241 .mac4_rep_out(mac4_rep_out[4:0]),
242 .mac5_rep_out(mac5_rep_out[4:0]),
243 .mac6_rep_out(mac6_rep_out[4:0]),
244 .scan_rep_out(scan_rep_out),
245 .mac0_rep_in(mac0_rep_in[4:0]),
246 .mac1_rep_in(mac1_rep_in[4:0]),
247 .mac2_rep_in(mac2_rep_in[4:0]),
248 .mac3_rep_in(mac3_rep_in[4:0]),
249 .mac4_rep_in(mac4_rep_in[4:0]),
250 .mac5_rep_in(mac5_rep_in[4:0]),
251 .mac6_rep_in(mac6_rep_in[4:0]),
252 .scan_rep_in(scan_rep_in)
253 );
254
255
256/*
257 pcx_mal_dp AUTO_TEMPLATE
258 (
259 // Outputs
260 .data_out_x_ (col@_data_x_[129:0]),
261 // Inputs
262 .arb_grant_a(arb_grant_l_a[@]),
263 .arb_qsel0_a(arb_qsel0_l_a[@]),
264 .arb_qsel1_a(arb_qsel1_l_a[@]),
265 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
266 .arb_shift_a(arb_shift_l_a[@]),
267 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
268 .l2clk (l2clk));
269*/
270
271// do not use autoinstancing.
272// connections have been modified to match the cpu floorplan
273// src_pcx_data_a has to be manually connected.
274
275// input from spc0
276pcx_mal_dp pcx_mac0 (
277 // Outputs
278 .data_out_x_ (col0_data_x_[129:0]), // Templated
279 .tcu_scan_en_out (tcu_scan_en_out_0_unused),
280 .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
281 .ccx_aclk_out (ccx_aclk_out_0_unused),
282 .ccx_bclk_out (ccx_bclk_out_0_unused),
283 // Inputs
284 .arb_grant_a (arb_grant_l_a_rep[0]), // Templated
285 .arb_qsel0_a (arb_qsel0_l_a_rep[0]), // Templated
286 .arb_qsel1_a (arb_qsel1_l_a_rep[0]), // Templated
287 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]), // Templated
288 .arb_shift_a (arb_shift_l_a_rep[0]), // Templated
289 .src_pcx_data_a (spc0_pcx_data_a[129:0]), // Templated
290 .scan_in(pcx_mac0_scanin),
291 .scan_out(pcx_mac0_scanout),
292 .l2clk (l2clk), // Templated
293 .tcu_scan_en (tcu_scan_en_out[1]),
294 .tcu_pce_ov (tcu_pce_ov_out[1]),
295 .ccx_aclk (ccx_aclk_out[1]),
296 .ccx_bclk (ccx_bclk_out[1])
297 );
298
299/*
300 pcx_mbl_dp AUTO_TEMPLATE
301 (
302 // Outputs
303 .data_out_x_ (col@_data_x_[129:0]),
304 // Inputs
305 .arb_grant_a(arb_grant_l_a[@]),
306 .arb_qsel0_a(arb_qsel0_l_a[@]),
307 .arb_qsel1_a(arb_qsel1_l_a[@]),
308 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
309 .arb_shift_a(arb_shift_l_a[@]),
310 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
311 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
312 .l2clk (l2clk));
313*/
314
315
316
317// input from spc2
318pcx_mbl_dp pcx_mac1(
319 // Outputs
320 .data_out_x_ (col1_data_x_[129:0]), // Templated
321 .tcu_scan_en_out (tcu_scan_en_out[1]),
322 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
323 .ccx_aclk_out (ccx_aclk_out[1]),
324 .ccx_bclk_out (ccx_bclk_out[1]),
325 // Inputs
326 .arb_grant_a (arb_grant_l_a_rep[2]), // Templated
327 .arb_qsel0_a (arb_qsel0_l_a_rep[2]), // Templated
328 .arb_qsel1_a (arb_qsel1_l_a_rep[2]), // Templated
329 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]), // Templated
330 .arb_shift_a (arb_shift_l_a_rep[2]), // Templated
331 .src_pcx_data_a (spc2_pcx_data_a[129:0]), // Templated
332 .data_prev_x_ (col0_data_x_[129:0]), // Templated
333 .scan_in(pcx_mac1_scanin),
334 .scan_out(pcx_mac1_scanout),
335 .l2clk (l2clk), // Templated
336 .tcu_scan_en (tcu_scan_en_out[2]),
337 .tcu_pce_ov (tcu_pce_ov_out[2]),
338 .ccx_aclk (ccx_aclk_out[2]),
339 .ccx_bclk (ccx_bclk_out[2])
340 );
341
342
343// input from spc1
344pcx_mbl_dp pcx_mac2(
345 // Outputs
346 .data_out_x_ (col2_data_x_[129:0]), // Templated
347 .tcu_scan_en_out (tcu_scan_en_out[2]),
348 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
349 .ccx_aclk_out (ccx_aclk_out[2]),
350 .ccx_bclk_out (ccx_bclk_out[2]),
351 // Inputs
352 .arb_grant_a (arb_grant_l_a_rep[1]), // Templated
353 .arb_qsel0_a (arb_qsel0_l_a_rep[1]), // Templated
354 .arb_qsel1_a (arb_qsel1_l_a_rep[1]), // Templated
355 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]), // Templated
356 .arb_shift_a (arb_shift_l_a_rep[1]), // Templated
357 .src_pcx_data_a (spc1_pcx_data_a[129:0]), // Templated
358 .data_prev_x_ (col1_data_x_[129:0]), // Templated
359 .scan_in(pcx_mac2_scanin),
360 .scan_out(pcx_mac2_scanout),
361 .l2clk (l2clk), // Templated
362 .tcu_scan_en (tcu_scan_en_out[3]),
363 .tcu_pce_ov (tcu_pce_ov_out[3]),
364 .ccx_aclk (ccx_aclk_out[3]),
365 .ccx_bclk (ccx_bclk_out[3])
366 );
367
368
369// input from spc3
370pcx_mbl_dp pcx_mac3(
371 // Outputs
372 .data_out_x_ (col3_data_x_[129:0]), // Templated
373 .tcu_scan_en_out (tcu_scan_en_out[3]),
374 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
375 .ccx_aclk_out (ccx_aclk_out[3]),
376 .ccx_bclk_out (ccx_bclk_out[3]),
377 // Inputs
378 .arb_grant_a (arb_grant_l_a_rep[3]), // Templated
379 .arb_qsel0_a (arb_qsel0_l_a_rep[3]), // Templated
380 .arb_qsel1_a (arb_qsel1_l_a_rep[3]), // Templated
381 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]), // Templated
382 .arb_shift_a (arb_shift_l_a_rep[3]), // Templated
383 .src_pcx_data_a (spc3_pcx_data_a[129:0]), // Templated
384 .data_prev_x_ (col2_data_x_[129:0]), // Templated
385 .scan_in(pcx_mac3_scanin),
386 .scan_out(pcx_mac3_scanout),
387 .l2clk (l2clk), // Templated
388 .tcu_scan_en (tcu_scan_en),
389 .tcu_pce_ov (tcu_pce_ov),
390 .ccx_aclk (ccx_aclk),
391 .ccx_bclk (ccx_bclk)
392 );
393
394// input from spc5
395pcx_mbl_dp pcx_mac4(
396 // Outputs
397 .data_out_x_ (col4_data_x_[129:0]), // Templated
398 .tcu_scan_en_out (tcu_scan_en_out[4]),
399 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
400 .ccx_aclk_out (ccx_aclk_out[4]),
401 .ccx_bclk_out (ccx_bclk_out[4]),
402 // Inputs
403 .arb_grant_a (arb_grant_r_a_rep[5]), // Templated
404 .arb_qsel0_a (arb_qsel0_r_a_rep[5]), // Templated
405 .arb_qsel1_a (arb_qsel1_r_a_rep[5]), // Templated
406 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]), // Templated
407 .arb_shift_a (arb_shift_r_a_rep[5]), // Templated
408 .src_pcx_data_a (spc5_pcx_data_a[129:0]), // Templated
409 .data_prev_x_ (col3_data_x_[129:0]), // Templated
410 .scan_in(pcx_mac4_scanin),
411 .scan_out(pcx_mac4_scanout),
412 .l2clk (l2clk), // Templated
413 .tcu_scan_en (tcu_scan_en_out[3]),
414 .tcu_pce_ov (tcu_pce_ov_out[3]),
415 .ccx_aclk (ccx_aclk_out[3]),
416 .ccx_bclk (ccx_bclk_out[3])
417 );
418
419
420// input from spc7
421pcx_mbl_dp pcx_mac5(
422 // Outputs
423 .data_out_x_ (col5_data_x_[129:0]), // Templated
424 .tcu_scan_en_out (tcu_scan_en_out[5]),
425 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
426 .ccx_aclk_out (ccx_aclk_out[5]),
427 .ccx_bclk_out (ccx_bclk_out[5]),
428 // Inputs
429 .arb_grant_a (arb_grant_r_a_rep[7]), // Templated
430 .arb_qsel0_a (arb_qsel0_r_a_rep[7]), // Templated
431 .arb_qsel1_a (arb_qsel1_r_a_rep[7]), // Templated
432 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]), // Templated
433 .arb_shift_a (arb_shift_r_a_rep[7]), // Templated
434 .src_pcx_data_a (spc7_pcx_data_a[129:0]), // Templated
435 .data_prev_x_ (col4_data_x_[129:0]), // Templated
436 .scan_in(pcx_mac5_scanin),
437 .scan_out(pcx_mac5_scanout),
438 .l2clk (l2clk), // Templated
439 .tcu_scan_en (tcu_scan_en_out[4]),
440 .tcu_pce_ov (tcu_pce_ov_out[4]),
441 .ccx_aclk (ccx_aclk_out[4]),
442 .ccx_bclk (ccx_bclk_out[4])
443 );
444
445
446/*
447 pcx_mcr_dp AUTO_TEMPLATE
448 (
449 // Outputs
450 .data_out_x_ (pcx_scache_data_x_[129:0]),
451 // Inputs
452 .arb_grant_a(arb_grant_r_a[@]),
453 .arb_qsel0_a(arb_qsel0_r_a[@]),
454 .arb_qsel1_a(arb_qsel1_r_a[@]),
455 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
456 .arb_shift_a(arb_shift_r_a[@]),
457 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
458 .data_crit_x_(col@"(- @ 1)"_data_x_[129:0]),
459 .data_ncrit_x_(col@"(+ @ 1)"_data_x_[129:0]),
460 .l2clk (l2clk))
461*/
462// input from spc4
463pcx_mcr_dp pcx_mac6(
464 // Outputs
465 .data_out_x_ (pcx_scache_data_x_[129:0]), // Templated
466 .tcu_scan_en_out (tcu_scan_en_out[6]),
467 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
468 .ccx_aclk_out (ccx_aclk_out[6]),
469 .ccx_bclk_out (ccx_bclk_out[6]),
470 // Inputs
471 .arb_grant_a (arb_grant_r_a_rep[4]), // Templated
472 .arb_qsel0_a (arb_qsel0_r_a_rep[4]), // Templated
473 .arb_qsel1_a (arb_qsel1_r_a_rep[4]), // Templated
474 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[4]), // Templated
475 .arb_shift_a (arb_shift_r_a_rep[4]), // Templated
476 .src_pcx_data_a (spc4_pcx_data_a[129:0]), // Templated
477 .data_crit_x_ (col5_data_x_[129:0]), // Templated
478 .data_ncrit_x_ (col7_data_x_[129:0]), // Templated
479 .scan_in(pcx_mac6_scanin),
480 .scan_out(pcx_mac6_scanout),
481 .l2clk (l2clk),
482 .tcu_scan_en (tcu_scan_en_out[5]),
483 .tcu_pce_ov (tcu_pce_ov_out[5]),
484 .ccx_aclk (ccx_aclk_out[5]),
485 .ccx_bclk (ccx_bclk_out[5])
486 );
487
488/*
489 pcx_mbr_dp AUTO_TEMPLATE
490 (
491 // Outputs
492 .data_out_x_ (col@_data_x_[129:0]),
493 // Inputs
494 .arb_grant_a(arb_grant_r_a[@]),
495 .arb_qsel0_a(arb_qsel0_r_a[@]),
496 .arb_qsel1_a(arb_qsel1_r_a[@]),
497 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
498 .arb_shift_a(arb_shift_r_a[@]),
499 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
500 .l2clk (l2clk));
501*/
502
503// input from spc6
504pcx_mbr_dp pcx_mac7 (
505 // Outputs
506 .data_out_x_ (col7_data_x_[129:0]), // Templated
507 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
508 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
509 .ccx_aclk_out (ccx_aclk_out_7_unused),
510 .ccx_bclk_out (ccx_bclk_out_7_unused),
511 // Inputs
512 .arb_grant_a (arb_grant_r_a[6]), // Templated
513 .arb_qsel0_a (arb_qsel0_r_a[6]), // Templated
514 .arb_qsel1_a (arb_qsel1_r_a[6]), // Templated
515 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[6]), // Templated
516 .arb_shift_a (arb_shift_r_a[6]), // Templated
517 .src_pcx_data_a (spc6_pcx_data_a[129:0]), // Templated
518 .data_prev_x_ (all_ones[129:0]), // Templated
519 .scan_in(pcx_mac7_scanin),
520 .scan_out(pcx_mac7_scanout),
521 .l2clk (l2clk), // Templated
522 .tcu_scan_en (tcu_scan_en_out[6]),
523 .tcu_pce_ov (tcu_pce_ov_out[6]),
524 .ccx_aclk (ccx_aclk_out[6]),
525 .ccx_bclk (ccx_bclk_out[6])
526 );
527
528
529assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
530assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
531assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
532assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
533assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
534
535assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
536assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
537assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
538assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
539assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
540
541
542
543// fixscan start:
544assign pcx_mac0_scanin = scan_rep_out ;
545assign pcx_mac1_scanin = pcx_mac0_scanout ;
546assign pcx_mac2_scanin = pcx_mac1_scanout ;
547assign pcx_mac3_scanin = pcx_mac2_scanout ;
548assign pcx_mac4_scanin = pcx_mac3_scanout ;
549assign pcx_mac5_scanin = pcx_mac4_scanout ;
550assign pcx_mac6_scanin = pcx_mac5_scanout ;
551assign pcx_mac7_scanin = pcx_mac6_scanout ;
552assign scan_out = pcx_mac7_scanout ;
553// fixscan end:
554endmodule
555
556// Local Variables:
557// verilog-library-directories:("." "v")
558// End:
559
560
561
562
563//
564// buff macro
565//
566//
567
568
569
570
571
572module pcx_dpsg_buff_macro__dbuff_32x__stack_6l__width_5 (
573 din,
574 dout);
575 input [4:0] din;
576 output [4:0] dout;
577
578
579
580
581
582
583buff #(5) d0_0 (
584.in(din[4:0]),
585.out(dout[4:0])
586);
587
588
589
590
591
592
593
594
595endmodule
596
597
598
599
600
601//
602// buff macro
603//
604//
605
606
607
608
609
610module pcx_dpsg_buff_macro__dbuff_32x__stack_none__width_1 (
611 din,
612 dout);
613 input [0:0] din;
614 output [0:0] dout;
615
616
617
618
619
620
621buff #(1) d0_0 (
622.in(din[0:0]),
623.out(dout[0:0])
624);
625
626
627
628
629
630
631
632
633endmodule
634
635
636
637
638//
639// buff macro
640//
641//
642
643
644
645
646
647module pcx_dpsg_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
648 din,
649 dout);
650 input [3:0] din;
651 output [3:0] dout;
652
653
654
655
656
657
658buff #(4) d0_0 (
659.in(din[3:0]),
660.out(dout[3:0])
661);
662
663
664
665
666
667
668
669
670endmodule
671
672
673
674
675
676
677
678
679
680// any PARAMS parms go into naming of macro
681
682module pcx_dpsg_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
683 l2clk,
684 l1en,
685 pce_ov,
686 stop,
687 se,
688 l1clk);
689
690
691 input l2clk;
692 input l1en;
693 input pce_ov;
694 input stop;
695 input se;
696 output l1clk;
697
698
699
700
701
702cl_sc1_l1hdr_24x c_0 (
703
704
705 .l2clk(l2clk),
706 .pce(l1en),
707 .l1clk(l1clk),
708 .se(se),
709 .pce_ov(pce_ov),
710 .stop(stop)
711);
712
713
714
715
716
717
718endmodule
719
720
721
722
723
724
725
726
727
728//
729// ccx macro
730//
731//
732
733
734
735
736
737module pcx_dpsg_ccx_new_macro__type_a (
738 l2clk,
739 l1clk,
740 pce0,
741 pce1,
742 pce_ov,
743 se,
744 stop,
745 siclk_in,
746 soclk_in,
747 scan_in,
748 grant_a,
749 qsel0,
750 shift,
751 data_a,
752 data_x_l,
753 scan_out);
754wire so5;
755wire siclk_out;
756wire soclk_out;
757wire l1clk0;
758wire l1clk1;
759wire grant_x;
760wire qsel0_buf;
761wire shift_buf;
762
763input l2clk;
764input l1clk;
765input pce0;
766input pce1;
767input pce_ov;
768input se;
769input stop;
770input siclk_in;
771input soclk_in;
772input scan_in;
773input grant_a;
774input qsel0;
775input shift;
776input [9:0] data_a;
777output [9:0] data_x_l;
778output scan_out;
779cl_dp1_ccxhdr c0 (
780.si(scan_in),
781.so(so5),
782 .l2clk(l2clk),
783 .pce0(pce0),
784 .pce1(pce1),
785 .pce_ov(pce_ov),
786 .stop(stop),
787 .siclk_in(siclk_in),
788 .soclk_in(soclk_in),
789 .siclk_out(siclk_out),
790 .soclk_out(soclk_out),
791 .l1clk0(l1clk0),
792 .l1clk1(l1clk1),
793 .se(se),
794 .l1clk(l1clk),
795 .grant_a(grant_a),
796 .grant_x(grant_x),
797 .qsel0(qsel0),
798 .qsel0_buf(qsel0_buf),
799 .shift(shift),
800 .shift_buf(shift_buf)
801);
802
803
804
805
806
807
808ccx_mac_a #(10) mac_a(
809.siclk(siclk_out),
810.soclk(soclk_out),
811.data_a(data_a[9:0]),
812.data_x_l(data_x_l[9:0]),
813.si(so5),
814.so(scan_out),
815 .l1clk0(l1clk0),
816 .l1clk1(l1clk1),
817 .grant_x(grant_x),
818 .qsel0_buf(qsel0_buf),
819 .shift_buf(shift_buf)
820);
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835endmodule
836
837//
838//// scan renames
839//assign pce_ov = tcu_pce_ov;
840//assign stop = tcu_clk_stop;
841//assign siclk = tcu_aclk;
842//assign soclk = tcu_bclk;
843//// end scan
844//
845//buff_macro i_buf_grant (width=1, stack=30c)
846//(
847// .din (arb_grant_a),
848// .dout (grant_a),
849// );
850//
851//msff_macro i_dff_grant_x (width=12, stack=30c)
852//(
853// .scan_in(i_dff_grant_x_scanin),
854// .scan_out(i_dff_grant_x_scanout),
855// .clk (l2clk),
856// .din ({12{grant_a}}),
857// .dout (grant_x[11:0]),
858// .en (1'b1),
859// );
860//
861//
862//// DATAPATH SECTION
863//
864//msff_macro i_dff_q1_2 (width=40, stack=50c)
865//(
866// .scan_in(i_dff_q1_2_scanin),
867// .scan_out(i_dff_q1_2_scanout),
868// .clk (l2clk),
869// .din (src_pcx_data_a[129:90]),
870// .dout (q1_dataout[129:90]),
871// .en (arb_qsel1_a),
872// );
873//
874//msff_macro i_dff_q1_1 (width=50, stack=50c)
875//(
876// .scan_in(i_dff_q1_1_scanin),
877// .scan_out(i_dff_q1_1_scanout),
878// .clk (l2clk),
879// .din (src_pcx_data_a[89:40]),
880// .dout (q1_dataout[89:40]),
881// .en (arb_qsel1_a),
882// );
883//
884//msff_macro i_dff_q1_0 (width=40, stack=50c)
885//(
886// .scan_in(i_dff_q1_0_scanin),
887// .scan_out(i_dff_q1_0_scanout),
888// .clk (l2clk),
889// .din (src_pcx_data_a[39:0]),
890// .dout (q1_dataout[39:0]),
891// .en (arb_qsel1_a),
892// );
893//
894////assign q0_datain_ca[149:0] =
895//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
896//// (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
897//
898//
899//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
900//(
901// .din0 (src_pcx_data_a[129:90]),
902// .din1 (q1_dataout[129:90]),
903// .sel0 (arb_qsel0_a),
904// .sel1 (arb_shift_a),
905// .dout (q0_datain_a[129:90]),
906// );
907//
908//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
909//(
910// .din0 (src_pcx_data_a[89:40]),
911// .din1 (q1_dataout[89:40]),
912// .sel0 (arb_qsel0_a),
913// .sel1 (arb_shift_a),
914// .dout (q0_datain_a[89:40]),
915// );
916//
917//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
918//(
919// .din0 (src_pcx_data_a[39:0]),
920// .din1 (q1_dataout[39:0]),
921// .sel0 (arb_qsel0_a),
922// .sel1 (arb_shift_a),
923// .dout (q0_datain_a[39:0]),
924// );
925//
926//msff_macro i_dff_q0_2 (width=40, stack=50c)
927//(
928// .scan_in(i_dff_q0_2_scanin),
929// .scan_out(i_dff_q0_2_scanout),
930// .clk (l2clk),
931// .din (q0_datain_a[129:90]),
932// .dout (q0_dataout[129:90]),
933// .en (arb_q0_holdbar_a),
934// );
935//
936//msff_macro i_dff_q0_1 (width=50, stack=50c)
937//(
938// .scan_in(i_dff_q0_1_scanin),
939// .scan_out(i_dff_q0_1_scanout),
940// .clk (l2clk),
941// .din (q0_datain_a[89:40]),
942// .dout (q0_dataout[89:40]),
943// .en (arb_q0_holdbar_a),
944// );
945//
946//msff_macro i_dff_q0_0 (width=40, stack=50c)
947//(
948// .scan_in(i_dff_q0_0_scanin),
949// .scan_out(i_dff_q0_0_scanout),
950// .clk (l2clk),
951// .din (q0_datain_a[39:0]),
952// .dout (q0_dataout[39:0]),
953// .en (arb_q0_holdbar_a),
954// );
955//
956////MUX
957//
958//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
959//(
960// .din0 (q0_dataout[129:90]),
961// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
962// .dout (data_x_[129:90]),
963// );
964//
965//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
966//(
967// .din0 (q0_dataout[89:40]),
968// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
969// .dout (data_x_[89:40]),
970// );
971//
972//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
973//(
974// .din0 (q0_dataout[39:0]),
975// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
976// .dout (data_x_[39:0]),
977// );
978//
979//
980//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c)
981//(
982// .din0 (data_x_[129:90]),
983// .din1 (data_prev_x_[129:90]),
984// .dout (data_out_x[129:90])
985// );
986//
987//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c)
988//(
989// .din0 (data_x_[89:40]),
990// .din1 (data_prev_x_[89:40]),
991// .dout (data_out_x[89:40])
992// );
993//
994//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c)
995//(
996// .din0 (data_x_[39:0]),
997// .din1 (data_prev_x_[39:0]),
998// .dout (data_out_x[39:0])
999// );
1000//
1001//inv_macro i_inv_data_out_2 (width=40, stack=50c)
1002//(
1003// .din (data_out_x[129:90]),
1004// .dout (data_out_x_[129:90])
1005// );
1006//
1007//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1008//(
1009// .din (data_out_x[89:40]),
1010// .dout (data_out_x_[89:40])
1011// );
1012//
1013//inv_macro i_inv_data_out_0 (width=40, stack=50c)
1014//(
1015// .din (data_out_x[39:0]),
1016// .dout (data_out_x_[39:0])
1017// );
1018//
1019//// fixscan start:
1020//assign i_dff_grant_x_scanin = scan_in ;
1021//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1022//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1023//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1024//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1025//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1026//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1027//assign scan_out = i_dff_q0_0_scanout ;
1028//// fixscan end:
1029//endmodule
1030//
1031// Local Variables:
1032// verilog-library-directories:("." "v")
1033// verilog-library-files:("./v/ccx_new_macro.v")
1034// End:
1035//
1036
1037
1038//
1039// ccx macro
1040//
1041//
1042
1043
1044
1045
1046
1047module pcx_dpsg_ccx_new_macro__type_b_l (
1048 l2clk,
1049 l1clk,
1050 pce0,
1051 pce1,
1052 pce_ov,
1053 se,
1054 stop,
1055 siclk_in,
1056 soclk_in,
1057 scan_in,
1058 grant_a,
1059 qsel0,
1060 shift,
1061 data_a,
1062 data_prev_x_l,
1063 data_x_l,
1064 scan_out);
1065wire so5;
1066wire siclk_out;
1067wire soclk_out;
1068wire l1clk0;
1069wire l1clk1;
1070wire grant_x;
1071wire qsel0_buf;
1072wire shift_buf;
1073
1074input l2clk;
1075input l1clk;
1076input pce0;
1077input pce1;
1078input pce_ov;
1079input se;
1080input stop;
1081input siclk_in;
1082input soclk_in;
1083input scan_in;
1084input grant_a;
1085input qsel0;
1086input shift;
1087input [9:0] data_a;
1088input [9:0] data_prev_x_l;
1089output [9:0] data_x_l;
1090output scan_out;
1091cl_dp1_ccxhdr c0 (
1092.si(scan_in),
1093.so(so5),
1094 .l2clk(l2clk),
1095 .pce0(pce0),
1096 .pce1(pce1),
1097 .pce_ov(pce_ov),
1098 .stop(stop),
1099 .siclk_in(siclk_in),
1100 .soclk_in(soclk_in),
1101 .siclk_out(siclk_out),
1102 .soclk_out(soclk_out),
1103 .l1clk0(l1clk0),
1104 .l1clk1(l1clk1),
1105 .se(se),
1106 .l1clk(l1clk),
1107 .grant_a(grant_a),
1108 .grant_x(grant_x),
1109 .qsel0(qsel0),
1110 .qsel0_buf(qsel0_buf),
1111 .shift(shift),
1112 .shift_buf(shift_buf)
1113);
1114
1115
1116
1117
1118
1119
1120ccx_mac_b #(10) mac_b(
1121.siclk(siclk_out),
1122.soclk(soclk_out),
1123.data_a(data_a[9:0]),
1124.data_prev_x_l(data_prev_x_l[9:0]),
1125.data_x_l(data_x_l[9:0]),
1126.si(so5),
1127.so(scan_out),
1128 .l1clk0(l1clk0),
1129 .l1clk1(l1clk1),
1130 .grant_x(grant_x),
1131 .qsel0_buf(qsel0_buf),
1132 .shift_buf(shift_buf)
1133);
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148endmodule
1149
1150//
1151//// scan renames
1152//assign pce_ov = tcu_pce_ov;
1153//assign stop = tcu_clk_stop;
1154//assign siclk = tcu_aclk;
1155//assign soclk = tcu_bclk;
1156//// end scan
1157//
1158//buff_macro i_buf_grant (width=1, stack=30c)
1159//(
1160// .din (arb_grant_a),
1161// .dout (grant_a),
1162// );
1163//
1164//msff_macro i_dff_grant_x (width=12, stack=30c)
1165//(
1166// .scan_in(i_dff_grant_x_scanin),
1167// .scan_out(i_dff_grant_x_scanout),
1168// .clk (l2clk),
1169// .din ({12{grant_a}}),
1170// .dout (grant_x[11:0]),
1171// .en (1'b1),
1172// );
1173//
1174//// DATAPATH SECTION
1175//
1176//msff_macro i_dff_q1_2 (width=40, stack=50c)
1177//(
1178// .scan_in(i_dff_q1_2_scanin),
1179// .scan_out(i_dff_q1_2_scanout),
1180// .clk (l2clk),
1181// .din (src_pcx_data_a[129:90]),
1182// .dout (q1_dataout[129:90]),
1183// .en (arb_qsel1_a),
1184// );
1185//
1186//msff_macro i_dff_q1_1 (width=50, stack=50c)
1187//(
1188// .scan_in(i_dff_q1_1_scanin),
1189// .scan_out(i_dff_q1_1_scanout),
1190// .clk (l2clk),
1191// .din (src_pcx_data_a[89:40]),
1192// .dout (q1_dataout[89:40]),
1193// .en (arb_qsel1_a),
1194// );
1195//
1196//msff_macro i_dff_q1_0 (width=40, stack=50c)
1197//(
1198// .scan_in(i_dff_q1_0_scanin),
1199// .scan_out(i_dff_q1_0_scanout),
1200// .clk (l2clk),
1201// .din (src_pcx_data_a[39:0]),
1202// .dout (q1_dataout[39:0]),
1203// .en (arb_qsel1_a),
1204// );
1205//
1206////assign q0_datain_ca[149:0] =
1207//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
1208//// (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
1209//
1210//
1211//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
1212//(
1213// .din0 (src_pcx_data_a[129:90]),
1214// .din1 (q1_dataout[129:90]),
1215// .sel0 (arb_qsel0_a),
1216// .sel1 (arb_shift_a),
1217// .dout (q0_datain_a[129:90]),
1218// );
1219//
1220//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1221//(
1222// .din0 (src_pcx_data_a[89:40]),
1223// .din1 (q1_dataout[89:40]),
1224// .sel0 (arb_qsel0_a),
1225// .sel1 (arb_shift_a),
1226// .dout (q0_datain_a[89:40]),
1227// );
1228//
1229//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
1230//(
1231// .din0 (src_pcx_data_a[39:0]),
1232// .din1 (q1_dataout[39:0]),
1233// .sel0 (arb_qsel0_a),
1234// .sel1 (arb_shift_a),
1235// .dout (q0_datain_a[39:0]),
1236// );
1237//
1238//msff_macro i_dff_q0_2 (width=40, stack=50c)
1239//(
1240// .scan_in(i_dff_q0_2_scanin),
1241// .scan_out(i_dff_q0_2_scanout),
1242// .clk (l2clk),
1243// .din (q0_datain_a[129:90]),
1244// .dout (q0_dataout[129:90]),
1245// .en (arb_q0_holdbar_a),
1246// );
1247//
1248//msff_macro i_dff_q0_1 (width=50, stack=50c)
1249//(
1250// .scan_in(i_dff_q0_1_scanin),
1251// .scan_out(i_dff_q0_1_scanout),
1252// .clk (l2clk),
1253// .din (q0_datain_a[89:40]),
1254// .dout (q0_dataout[89:40]),
1255// .en (arb_q0_holdbar_a),
1256// );
1257//
1258//msff_macro i_dff_q0_0 (width=40, stack=50c)
1259//(
1260// .scan_in(i_dff_q0_0_scanin),
1261// .scan_out(i_dff_q0_0_scanout),
1262// .clk (l2clk),
1263// .din (q0_datain_a[39:0]),
1264// .dout (q0_dataout[39:0]),
1265// .en (arb_q0_holdbar_a),
1266// );
1267//
1268////MUX
1269//
1270//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
1271//(
1272// .din0 (q0_dataout[129:90]),
1273// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
1274// .dout (data_x_[129:90]),
1275// );
1276//
1277//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1278//(
1279// .din0 (q0_dataout[89:40]),
1280// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1281// .dout (data_x_[89:40]),
1282// );
1283//
1284//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
1285//(
1286// .din0 (q0_dataout[39:0]),
1287// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
1288// .dout (data_x_[39:0]),
1289// );
1290//
1291//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c)
1292//(
1293// .din0 (data_x_[129:90]),
1294// .din1 (data_crit_x_[129:90]),
1295// .din2 (data_ncrit_x_[129:90]),
1296// .dout (data_out_x[129:90])
1297//);
1298//
1299//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c)
1300//(
1301// .din0 (data_x_[89:40]),
1302// .din1 (data_crit_x_[89:40]),
1303// .din2 (data_ncrit_x_[89:40]),
1304// .dout (data_out_x[89:40])
1305//);
1306//
1307//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c)
1308//(
1309// .din0 (data_x_[39:0]),
1310// .din1 (data_crit_x_[39:0]),
1311// .din2 (data_ncrit_x_[39:0]),
1312// .dout (data_out_x[39:0])
1313//);
1314//
1315//inv_macro i_inv_data_out_2 (width=40, stack=50c)
1316//(
1317// .din (data_out_x[129:90]),
1318// .dout (data_out_x_[129:90])
1319// );
1320//
1321//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1322//(
1323// .din (data_out_x[89:40]),
1324// .dout (data_out_x_[89:40])
1325// );
1326//
1327//inv_macro i_inv_data_out_0 (width=40, stack=50c)
1328//(
1329// .din (data_out_x[39:0]),
1330// .dout (data_out_x_[39:0])
1331// );
1332//
1333//// fixscan start:
1334//assign i_dff_grant_x_scanin = scan_in ;
1335//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1336//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1337//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1338//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1339//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1340//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1341//assign scan_out = i_dff_q0_0_scanout ;
1342//// fixscan end:
1343//endmodule
1344// Local Variables:
1345// verilog-library-directories:("." "v")
1346// verilog-library-files:("./v/ccx_new_macro.v")
1347// End:
1348//
1349
1350
1351//
1352// ccx macro
1353//
1354//
1355
1356
1357
1358
1359
1360module pcx_dpsg_ccx_new_macro__type_c_r (
1361 l2clk,
1362 l1clk,
1363 pce0,
1364 pce1,
1365 pce_ov,
1366 se,
1367 stop,
1368 siclk_in,
1369 soclk_in,
1370 scan_in,
1371 grant_a,
1372 qsel0,
1373 shift,
1374 data_a,
1375 data_crit_x_l,
1376 data_ncrit_x_l,
1377 data_x_l,
1378 scan_out);
1379wire so5;
1380wire siclk_out;
1381wire soclk_out;
1382wire l1clk0;
1383wire l1clk1;
1384wire grant_x;
1385wire qsel0_buf;
1386wire shift_buf;
1387
1388input l2clk;
1389input l1clk;
1390input pce0;
1391input pce1;
1392input pce_ov;
1393input se;
1394input stop;
1395input siclk_in;
1396input soclk_in;
1397input scan_in;
1398input grant_a;
1399input qsel0;
1400input shift;
1401input [9:0] data_a;
1402input [9:0] data_crit_x_l;
1403input [9:0] data_ncrit_x_l;
1404output [9:0] data_x_l;
1405output scan_out;
1406cl_dp1_ccxhdr c0 (
1407.si(scan_in),
1408.so(so5),
1409 .l2clk(l2clk),
1410 .pce0(pce0),
1411 .pce1(pce1),
1412 .pce_ov(pce_ov),
1413 .stop(stop),
1414 .siclk_in(siclk_in),
1415 .soclk_in(soclk_in),
1416 .siclk_out(siclk_out),
1417 .soclk_out(soclk_out),
1418 .l1clk0(l1clk0),
1419 .l1clk1(l1clk1),
1420 .se(se),
1421 .l1clk(l1clk),
1422 .grant_a(grant_a),
1423 .grant_x(grant_x),
1424 .qsel0(qsel0),
1425 .qsel0_buf(qsel0_buf),
1426 .shift(shift),
1427 .shift_buf(shift_buf)
1428);
1429
1430
1431
1432
1433
1434
1435ccx_mac_c #(10) mac_c(
1436.siclk(siclk_out),
1437.soclk(soclk_out),
1438.data_a(data_a[9:0]),
1439.data_crit_x_l(data_crit_x_l[9:0]),
1440.data_ncrit_x_l(data_ncrit_x_l[9:0]),
1441.data_x_l(data_x_l[9:0]),
1442.si(so5),
1443.so(scan_out),
1444 .l1clk0(l1clk0),
1445 .l1clk1(l1clk1),
1446 .grant_x(grant_x),
1447 .qsel0_buf(qsel0_buf),
1448 .shift_buf(shift_buf)
1449);
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464endmodule
1465
1466
1467//
1468//// scan renames
1469//assign pce_ov = tcu_pce_ov;
1470//assign stop = tcu_clk_stop;
1471//assign siclk = tcu_aclk;
1472//assign soclk = tcu_bclk;
1473//// end scan
1474//
1475//buff_macro i_buf_grant (width=1, stack=30c)
1476//(
1477// .din (arb_grant_a),
1478// .dout (grant_a),
1479// );
1480//
1481//msff_macro i_dff_grant_x (width=12, stack=30c)
1482//(
1483// .scan_in(i_dff_grant_x_scanin),
1484// .scan_out(i_dff_grant_x_scanout),
1485// .clk (l2clk),
1486// .din ({12{grant_a}}),
1487// .dout (grant_x[11:0]),
1488// .en (1'b1),
1489// );
1490//
1491//
1492//// DATAPATH SECTION
1493//
1494//msff_macro i_dff_q1_2 (width=40, stack=50c)
1495//(
1496// .scan_in(i_dff_q1_2_scanin),
1497// .scan_out(i_dff_q1_2_scanout),
1498// .clk (l2clk),
1499// .din (src_pcx_data_a[129:90]),
1500// .dout (q1_dataout[129:90]),
1501// .en (arb_qsel1_a),
1502// );
1503//
1504//msff_macro i_dff_q1_1 (width=50, stack=50c)
1505//(
1506// .scan_in(i_dff_q1_1_scanin),
1507// .scan_out(i_dff_q1_1_scanout),
1508// .clk (l2clk),
1509// .din (src_pcx_data_a[89:40]),
1510// .dout (q1_dataout[89:40]),
1511// .en (arb_qsel1_a),
1512// );
1513//
1514//msff_macro i_dff_q1_0 (width=40, stack=50c)
1515//(
1516// .scan_in(i_dff_q1_0_scanin),
1517// .scan_out(i_dff_q1_0_scanout),
1518// .clk (l2clk),
1519// .din (src_pcx_data_a[39:0]),
1520// .dout (q1_dataout[39:0]),
1521// .en (arb_qsel1_a),
1522// );
1523//
1524////assign q0_datain_ca[149:0] =
1525//// (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
1526//// (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
1527//
1528//
1529//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c)
1530//(
1531// .din0 (src_pcx_data_a[129:90]),
1532// .din1 (q1_dataout[129:90]),
1533// .sel0 (arb_qsel0_a),
1534// .sel1 (arb_shift_a),
1535// .dout (q0_datain_a[129:90]),
1536// );
1537//
1538//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c)
1539//(
1540// .din0 (src_pcx_data_a[89:40]),
1541// .din1 (q1_dataout[89:40]),
1542// .sel0 (arb_qsel0_a),
1543// .sel1 (arb_shift_a),
1544// .dout (q0_datain_a[89:40]),
1545// );
1546//
1547//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c)
1548//(
1549// .din0 (src_pcx_data_a[39:0]),
1550// .din1 (q1_dataout[39:0]),
1551// .sel0 (arb_qsel0_a),
1552// .sel1 (arb_shift_a),
1553// .dout (q0_datain_a[39:0]),
1554// );
1555//
1556//msff_macro i_dff_q0_2 (width=40, stack=50c)
1557//(
1558// .scan_in(i_dff_q0_2_scanin),
1559// .scan_out(i_dff_q0_2_scanout),
1560// .clk (l2clk),
1561// .din (q0_datain_a[129:90]),
1562// .dout (q0_dataout[129:90]),
1563// .en (arb_q0_holdbar_a),
1564// );
1565//
1566//msff_macro i_dff_q0_1 (width=50, stack=50c)
1567//(
1568// .scan_in(i_dff_q0_1_scanin),
1569// .scan_out(i_dff_q0_1_scanout),
1570// .clk (l2clk),
1571// .din (q0_datain_a[89:40]),
1572// .dout (q0_dataout[89:40]),
1573// .en (arb_q0_holdbar_a),
1574// );
1575//
1576//msff_macro i_dff_q0_0 (width=40, stack=50c)
1577//(
1578// .scan_in(i_dff_q0_0_scanin),
1579// .scan_out(i_dff_q0_0_scanout),
1580// .clk (l2clk),
1581// .din (q0_datain_a[39:0]),
1582// .dout (q0_dataout[39:0]),
1583// .en (arb_q0_holdbar_a),
1584// );
1585//
1586////MUX
1587//
1588//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c)
1589//(
1590// .din0 (q0_dataout[129:90]),
1591// .din1 ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
1592// .dout (data_x_[129:90]),
1593// );
1594//
1595//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c)
1596//(
1597// .din0 (q0_dataout[89:40]),
1598// .din1 ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
1599// .dout (data_x_[89:40]),
1600// );
1601//
1602//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c)
1603//(
1604// .din0 (q0_dataout[39:0]),
1605// .din1 ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
1606// .dout (data_x_[39:0]),
1607// );
1608//
1609//
1610//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c)
1611//(
1612// .din0 (data_x_[129:90]),
1613// .din1 (data_prev_x_[129:90]),
1614// .dout (data_out_x[129:90])
1615// );
1616//
1617//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c)
1618//(
1619// .din0 (data_x_[89:40]),
1620// .din1 (data_prev_x_[89:40]),
1621// .dout (data_out_x[89:40])
1622// );
1623//
1624//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c)
1625//(
1626// .din0 (data_x_[39:0]),
1627// .din1 (data_prev_x_[39:0]),
1628// .dout (data_out_x[39:0])
1629// );
1630//
1631//inv_macro i_inv_data_out_2 (width=40, stack=50c)
1632//(
1633// .din (data_out_x[129:90]),
1634// .dout (data_out_x_[129:90])
1635// );
1636//
1637//inv_macro i_inv_data_out_1 (width=50, stack=50c)
1638//(
1639// .din (data_out_x[89:40]),
1640// .dout (data_out_x_[89:40])
1641// );
1642//
1643//inv_macro i_inv_data_out_0 (width=40, stack=50c)
1644//(
1645// .din (data_out_x[39:0]),
1646// .dout (data_out_x_[39:0])
1647// );
1648//
1649//// fixscan start:
1650//assign i_dff_grant_x_scanin = scan_in ;
1651//assign i_dff_q1_2_scanin = i_dff_grant_x_scanout ;
1652//assign i_dff_q1_1_scanin = i_dff_q1_2_scanout ;
1653//assign i_dff_q1_0_scanin = i_dff_q1_1_scanout ;
1654//assign i_dff_q0_2_scanin = i_dff_q1_0_scanout ;
1655//assign i_dff_q0_1_scanin = i_dff_q0_2_scanout ;
1656//assign i_dff_q0_0_scanin = i_dff_q0_1_scanout ;
1657//assign scan_out = i_dff_q0_0_scanout ;
1658//// fixscan end:
1659//endmodule
1660//
1661// Local Variables:
1662// verilog-library-directories:("." "v")
1663// verilog-library-files:("./v/ccx_new_macro.v")
1664// End:
1665//
1666
1667
1668//
1669// ccx macro
1670//
1671//
1672
1673
1674
1675
1676
1677module pcx_dpsg_ccx_new_macro__type_b_r (
1678 l2clk,
1679 l1clk,
1680 pce0,
1681 pce1,
1682 pce_ov,
1683 se,
1684 stop,
1685 siclk_in,
1686 soclk_in,
1687 scan_in,
1688 grant_a,
1689 qsel0,
1690 shift,
1691 data_a,
1692 data_prev_x_l,
1693 data_x_l,
1694 scan_out);
1695wire so5;
1696wire siclk_out;
1697wire soclk_out;
1698wire l1clk0;
1699wire l1clk1;
1700wire grant_x;
1701wire qsel0_buf;
1702wire shift_buf;
1703
1704input l2clk;
1705input l1clk;
1706input pce0;
1707input pce1;
1708input pce_ov;
1709input se;
1710input stop;
1711input siclk_in;
1712input soclk_in;
1713input scan_in;
1714input grant_a;
1715input qsel0;
1716input shift;
1717input [9:0] data_a;
1718input [9:0] data_prev_x_l;
1719output [9:0] data_x_l;
1720output scan_out;
1721cl_dp1_ccxhdr c0 (
1722.si(scan_in),
1723.so(so5),
1724 .l2clk(l2clk),
1725 .pce0(pce0),
1726 .pce1(pce1),
1727 .pce_ov(pce_ov),
1728 .stop(stop),
1729 .siclk_in(siclk_in),
1730 .soclk_in(soclk_in),
1731 .siclk_out(siclk_out),
1732 .soclk_out(soclk_out),
1733 .l1clk0(l1clk0),
1734 .l1clk1(l1clk1),
1735 .se(se),
1736 .l1clk(l1clk),
1737 .grant_a(grant_a),
1738 .grant_x(grant_x),
1739 .qsel0(qsel0),
1740 .qsel0_buf(qsel0_buf),
1741 .shift(shift),
1742 .shift_buf(shift_buf)
1743);
1744
1745
1746
1747
1748
1749
1750ccx_mac_b #(10) mac_b(
1751.siclk(siclk_out),
1752.soclk(soclk_out),
1753.data_a(data_a[9:0]),
1754.data_prev_x_l(data_prev_x_l[9:0]),
1755.data_x_l(data_x_l[9:0]),
1756.si(so5),
1757.so(scan_out),
1758 .l1clk0(l1clk0),
1759 .l1clk1(l1clk1),
1760 .grant_x(grant_x),
1761 .qsel0_buf(qsel0_buf),
1762 .shift_buf(shift_buf)
1763);
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778endmodule
1779
1780`endif // `ifndef FPGA
1781
1782`ifdef FPGA
1783`timescale 1 ns / 100 ps
1784module pcx_dpsg(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a,
1785 arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a,
1786 arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a,
1787 spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a,
1788 spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a,
1789 tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);
1790
1791 output [129:0] pcx_scache_data_x_;
1792 input [7:0] arb_grant_l_a;
1793 input [7:0] arb_q0_holdbar_l_a;
1794 input [7:0] arb_qsel0_l_a;
1795 input [7:0] arb_qsel1_l_a;
1796 input [7:0] arb_shift_l_a;
1797 input [7:0] arb_grant_r_a;
1798 input [7:0] arb_q0_holdbar_r_a;
1799 input [7:0] arb_qsel0_r_a;
1800 input [7:0] arb_qsel1_r_a;
1801 input [7:0] arb_shift_r_a;
1802 input [129:0] spc0_pcx_data_a;
1803 input [129:0] spc1_pcx_data_a;
1804 input [129:0] spc2_pcx_data_a;
1805 input [129:0] spc3_pcx_data_a;
1806 input [129:0] spc4_pcx_data_a;
1807 input [129:0] spc5_pcx_data_a;
1808 input [129:0] spc6_pcx_data_a;
1809 input [129:0] spc7_pcx_data_a;
1810 input tcu_scan_en;
1811 input l2clk;
1812 input tcu_pce_ov;
1813 input ccx_aclk;
1814 input ccx_bclk;
1815 input scan_in;
1816 output scan_out;
1817
1818 wire [129:0] all_ones;
1819 wire [4:0] mac0_rep_in;
1820 wire [3:0] arb_grant_l_a_rep;
1821 wire [3:0] arb_qsel0_l_a_rep;
1822 wire [3:0] arb_qsel1_l_a_rep;
1823 wire [3:0] arb_shift_l_a_rep;
1824 wire [3:0] arb_q0_holdbar_l_a_rep;
1825 wire [4:0] mac0_rep_out;
1826 wire [4:0] mac1_rep_in;
1827 wire [4:0] mac1_rep_out;
1828 wire [4:0] mac2_rep_in;
1829 wire [4:0] mac2_rep_out;
1830 wire [4:0] mac3_rep_in;
1831 wire [4:0] mac3_rep_out;
1832 wire [4:0] mac4_rep_in;
1833 wire [7:4] arb_grant_r_a_rep;
1834 wire [7:4] arb_q0_holdbar_r_a_rep;
1835 wire [7:4] arb_qsel0_r_a_rep;
1836 wire [7:4] arb_qsel1_r_a_rep;
1837 wire [7:4] arb_shift_r_a_rep;
1838 wire [4:0] mac4_rep_out;
1839 wire [4:0] mac5_rep_in;
1840 wire [4:0] mac5_rep_out;
1841 wire [4:0] mac6_rep_in;
1842 wire [4:0] mac6_rep_out;
1843 wire scan_rep_in;
1844 wire [129:0] col0_data_x_;
1845 wire tcu_scan_en_out_0_unused;
1846 wire tcu_pce_ov_out_0_unused;
1847 wire ccx_aclk_out_0_unused;
1848 wire ccx_bclk_out_0_unused;
1849 wire pcx_mac0_scanin;
1850 wire pcx_mac0_scanout;
1851 wire [6:1] tcu_scan_en_out;
1852 wire [6:1] tcu_pce_ov_out;
1853 wire [6:1] ccx_aclk_out;
1854 wire [6:1] ccx_bclk_out;
1855 wire [129:0] col1_data_x_;
1856 wire pcx_mac1_scanin;
1857 wire pcx_mac1_scanout;
1858 wire [129:0] col2_data_x_;
1859 wire pcx_mac2_scanin;
1860 wire pcx_mac2_scanout;
1861 wire [129:0] col3_data_x_;
1862 wire pcx_mac3_scanin;
1863 wire pcx_mac3_scanout;
1864 wire [129:0] col4_data_x_;
1865 wire pcx_mac4_scanin;
1866 wire pcx_mac4_scanout;
1867 wire [129:0] col5_data_x_;
1868 wire pcx_mac5_scanin;
1869 wire pcx_mac5_scanout;
1870 wire [129:0] col7_data_x_;
1871 wire pcx_mac6_scanin;
1872 wire pcx_mac6_scanout;
1873 wire tcu_scan_en_out_7_unused;
1874 wire tcu_pce_ov_out_7_unused;
1875 wire ccx_aclk_out_7_unused;
1876 wire ccx_bclk_out_7_unused;
1877 wire pcx_mac7_scanin;
1878 wire pcx_mac7_scanout;
1879 wire [7:4] arb_grant_l_a_unused;
1880 wire [7:4] arb_q0_holdbar_l_a_unused;
1881 wire [7:4] arb_qsel0_l_a_unused;
1882 wire [7:4] arb_qsel1_l_a_unused;
1883 wire [7:4] arb_shift_l_a_unused;
1884 wire [3:0] arb_grant_r_a_unused;
1885 wire [3:0] arb_q0_holdbar_r_a_unused;
1886 wire [3:0] arb_qsel0_r_a_unused;
1887 wire [3:0] arb_qsel1_r_a_unused;
1888 wire [3:0] arb_shift_r_a_unused;
1889 wire scan_rep_out;
1890
1891 assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
1892 assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0],
1893 arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
1894 assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0],
1895 arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0],
1896 arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
1897 assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2],
1898 arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
1899 assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2],
1900 arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
1901 } = mac1_rep_out[4:0];
1902 assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1],
1903 arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
1904 assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1],
1905 arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
1906 } = mac2_rep_out[4:0];
1907 assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3],
1908 arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
1909 assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3],
1910 arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
1911 } = mac3_rep_out[4:0];
1912 assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5],
1913 arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
1914 assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5],
1915 arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
1916 } = mac4_rep_out[4:0];
1917 assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7],
1918 arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
1919 assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7],
1920 arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
1921 } = mac5_rep_out[4:0];
1922 assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4],
1923 arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
1924 assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4],
1925 arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
1926 } = mac6_rep_out[4:0];
1927 assign scan_rep_in = scan_in;
1928 assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
1929 assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
1930 assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
1931 assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
1932 assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
1933 assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
1934 assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
1935 assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
1936 assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
1937 assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
1938 assign pcx_mac0_scanin = scan_rep_out;
1939 assign pcx_mac1_scanin = pcx_mac0_scanout;
1940 assign pcx_mac2_scanin = pcx_mac1_scanout;
1941 assign pcx_mac3_scanin = pcx_mac2_scanout;
1942 assign pcx_mac4_scanin = pcx_mac3_scanout;
1943 assign pcx_mac5_scanin = pcx_mac4_scanout;
1944 assign pcx_mac6_scanin = pcx_mac5_scanout;
1945 assign pcx_mac7_scanin = pcx_mac6_scanout;
1946 assign scan_out = pcx_mac7_scanout;
1947
1948 pcx_rep_dp pcx_rep(
1949 .mac0_rep_out (mac0_rep_out[4:0]),
1950 .mac1_rep_out (mac1_rep_out[4:0]),
1951 .mac2_rep_out (mac2_rep_out[4:0]),
1952 .mac3_rep_out (mac3_rep_out[4:0]),
1953 .mac4_rep_out (mac4_rep_out[4:0]),
1954 .mac5_rep_out (mac5_rep_out[4:0]),
1955 .mac6_rep_out (mac6_rep_out[4:0]),
1956 .scan_rep_out (scan_rep_out),
1957 .mac0_rep_in (mac0_rep_in[4:0]),
1958 .mac1_rep_in (mac1_rep_in[4:0]),
1959 .mac2_rep_in (mac2_rep_in[4:0]),
1960 .mac3_rep_in (mac3_rep_in[4:0]),
1961 .mac4_rep_in (mac4_rep_in[4:0]),
1962 .mac5_rep_in (mac5_rep_in[4:0]),
1963 .mac6_rep_in (mac6_rep_in[4:0]),
1964 .scan_rep_in (scan_rep_in));
1965 pcx_mal_dp pcx_mac0(
1966 .data_out_x_ (col0_data_x_[129:0]),
1967 .tcu_scan_en_out (tcu_scan_en_out_0_unused),
1968 .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
1969 .ccx_aclk_out (ccx_aclk_out_0_unused),
1970 .ccx_bclk_out (ccx_bclk_out_0_unused),
1971 .arb_grant_a (arb_grant_l_a_rep[0]),
1972 .arb_qsel0_a (arb_qsel0_l_a_rep[0]),
1973 .arb_qsel1_a (arb_qsel1_l_a_rep[0]),
1974 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[0]),
1975 .arb_shift_a (arb_shift_l_a_rep[0]),
1976 .src_pcx_data_a (spc0_pcx_data_a[129:0]),
1977 .scan_in (pcx_mac0_scanin),
1978 .scan_out (pcx_mac0_scanout),
1979 .l2clk (l2clk),
1980 .tcu_scan_en (tcu_scan_en_out[1]),
1981 .tcu_pce_ov (tcu_pce_ov_out[1]),
1982 .ccx_aclk (ccx_aclk_out[1]),
1983 .ccx_bclk (ccx_bclk_out[1]));
1984 pcx_mbl_dp pcx_mac1(
1985 .data_out_x_ (col1_data_x_[129:0]),
1986 .tcu_scan_en_out (tcu_scan_en_out[1]),
1987 .tcu_pce_ov_out (tcu_pce_ov_out[1]),
1988 .ccx_aclk_out (ccx_aclk_out[1]),
1989 .ccx_bclk_out (ccx_bclk_out[1]),
1990 .arb_grant_a (arb_grant_l_a_rep[2]),
1991 .arb_qsel0_a (arb_qsel0_l_a_rep[2]),
1992 .arb_qsel1_a (arb_qsel1_l_a_rep[2]),
1993 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[2]),
1994 .arb_shift_a (arb_shift_l_a_rep[2]),
1995 .src_pcx_data_a (spc2_pcx_data_a[129:0]),
1996 .data_prev_x_ (col0_data_x_[129:0]),
1997 .scan_in (pcx_mac1_scanin),
1998 .scan_out (pcx_mac1_scanout),
1999 .l2clk (l2clk),
2000 .tcu_scan_en (tcu_scan_en_out[2]),
2001 .tcu_pce_ov (tcu_pce_ov_out[2]),
2002 .ccx_aclk (ccx_aclk_out[2]),
2003 .ccx_bclk (ccx_bclk_out[2]));
2004 pcx_mbl_dp pcx_mac2(
2005 .data_out_x_ (col2_data_x_[129:0]),
2006 .tcu_scan_en_out (tcu_scan_en_out[2]),
2007 .tcu_pce_ov_out (tcu_pce_ov_out[2]),
2008 .ccx_aclk_out (ccx_aclk_out[2]),
2009 .ccx_bclk_out (ccx_bclk_out[2]),
2010 .arb_grant_a (arb_grant_l_a_rep[1]),
2011 .arb_qsel0_a (arb_qsel0_l_a_rep[1]),
2012 .arb_qsel1_a (arb_qsel1_l_a_rep[1]),
2013 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[1]),
2014 .arb_shift_a (arb_shift_l_a_rep[1]),
2015 .src_pcx_data_a (spc1_pcx_data_a[129:0]),
2016 .data_prev_x_ (col1_data_x_[129:0]),
2017 .scan_in (pcx_mac2_scanin),
2018 .scan_out (pcx_mac2_scanout),
2019 .l2clk (l2clk),
2020 .tcu_scan_en (tcu_scan_en_out[3]),
2021 .tcu_pce_ov (tcu_pce_ov_out[3]),
2022 .ccx_aclk (ccx_aclk_out[3]),
2023 .ccx_bclk (ccx_bclk_out[3]));
2024 pcx_mbl_dp pcx_mac3(
2025 .data_out_x_ (col3_data_x_[129:0]),
2026 .tcu_scan_en_out (tcu_scan_en_out[3]),
2027 .tcu_pce_ov_out (tcu_pce_ov_out[3]),
2028 .ccx_aclk_out (ccx_aclk_out[3]),
2029 .ccx_bclk_out (ccx_bclk_out[3]),
2030 .arb_grant_a (arb_grant_l_a_rep[3]),
2031 .arb_qsel0_a (arb_qsel0_l_a_rep[3]),
2032 .arb_qsel1_a (arb_qsel1_l_a_rep[3]),
2033 .arb_q0_holdbar_a (arb_q0_holdbar_l_a_rep[3]),
2034 .arb_shift_a (arb_shift_l_a_rep[3]),
2035 .src_pcx_data_a (spc3_pcx_data_a[129:0]),
2036 .data_prev_x_ (col2_data_x_[129:0]),
2037 .scan_in (pcx_mac3_scanin),
2038 .scan_out (pcx_mac3_scanout),
2039 .l2clk (l2clk),
2040 .tcu_scan_en (tcu_scan_en),
2041 .tcu_pce_ov (tcu_pce_ov),
2042 .ccx_aclk (ccx_aclk),
2043 .ccx_bclk (ccx_bclk));
2044 pcx_mbl_dp pcx_mac4(
2045 .data_out_x_ (col4_data_x_[129:0]),
2046 .tcu_scan_en_out (tcu_scan_en_out[4]),
2047 .tcu_pce_ov_out (tcu_pce_ov_out[4]),
2048 .ccx_aclk_out (ccx_aclk_out[4]),
2049 .ccx_bclk_out (ccx_bclk_out[4]),
2050 .arb_grant_a (arb_grant_r_a_rep[5]),
2051 .arb_qsel0_a (arb_qsel0_r_a_rep[5]),
2052 .arb_qsel1_a (arb_qsel1_r_a_rep[5]),
2053 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[5]),
2054 .arb_shift_a (arb_shift_r_a_rep[5]),
2055 .src_pcx_data_a (spc5_pcx_data_a[129:0]),
2056 .data_prev_x_ (col3_data_x_[129:0]),
2057 .scan_in (pcx_mac4_scanin),
2058 .scan_out (pcx_mac4_scanout),
2059 .l2clk (l2clk),
2060 .tcu_scan_en (tcu_scan_en_out[3]),
2061 .tcu_pce_ov (tcu_pce_ov_out[3]),
2062 .ccx_aclk (ccx_aclk_out[3]),
2063 .ccx_bclk (ccx_bclk_out[3]));
2064 pcx_mbl_dp pcx_mac5(
2065 .data_out_x_ (col5_data_x_[129:0]),
2066 .tcu_scan_en_out (tcu_scan_en_out[5]),
2067 .tcu_pce_ov_out (tcu_pce_ov_out[5]),
2068 .ccx_aclk_out (ccx_aclk_out[5]),
2069 .ccx_bclk_out (ccx_bclk_out[5]),
2070 .arb_grant_a (arb_grant_r_a_rep[7]),
2071 .arb_qsel0_a (arb_qsel0_r_a_rep[7]),
2072 .arb_qsel1_a (arb_qsel1_r_a_rep[7]),
2073 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[7]),
2074 .arb_shift_a (arb_shift_r_a_rep[7]),
2075 .src_pcx_data_a (spc7_pcx_data_a[129:0]),
2076 .data_prev_x_ (col4_data_x_[129:0]),
2077 .scan_in (pcx_mac5_scanin),
2078 .scan_out (pcx_mac5_scanout),
2079 .l2clk (l2clk),
2080 .tcu_scan_en (tcu_scan_en_out[4]),
2081 .tcu_pce_ov (tcu_pce_ov_out[4]),
2082 .ccx_aclk (ccx_aclk_out[4]),
2083 .ccx_bclk (ccx_bclk_out[4]));
2084 pcx_mcr_dp pcx_mac6(
2085 .data_out_x_ (pcx_scache_data_x_[129:0]),
2086 .tcu_scan_en_out (tcu_scan_en_out[6]),
2087 .tcu_pce_ov_out (tcu_pce_ov_out[6]),
2088 .ccx_aclk_out (ccx_aclk_out[6]),
2089 .ccx_bclk_out (ccx_bclk_out[6]),
2090 .arb_grant_a (arb_grant_r_a_rep[4]),
2091 .arb_qsel0_a (arb_qsel0_r_a_rep[4]),
2092 .arb_qsel1_a (arb_qsel1_r_a_rep[4]),
2093 .arb_q0_holdbar_a (arb_q0_holdbar_r_a_rep[4]),
2094 .arb_shift_a (arb_shift_r_a_rep[4]),
2095 .src_pcx_data_a (spc4_pcx_data_a[129:0]),
2096 .data_crit_x_ (col5_data_x_[129:0]),
2097 .data_ncrit_x_ (col7_data_x_[129:0]),
2098 .scan_in (pcx_mac6_scanin),
2099 .scan_out (pcx_mac6_scanout),
2100 .l2clk (l2clk),
2101 .tcu_scan_en (tcu_scan_en_out[5]),
2102 .tcu_pce_ov (tcu_pce_ov_out[5]),
2103 .ccx_aclk (ccx_aclk_out[5]),
2104 .ccx_bclk (ccx_bclk_out[5]));
2105 pcx_mbr_dp pcx_mac7(
2106 .data_out_x_ (col7_data_x_[129:0]),
2107 .tcu_scan_en_out (tcu_scan_en_out_7_unused),
2108 .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
2109 .ccx_aclk_out (ccx_aclk_out_7_unused),
2110 .ccx_bclk_out (ccx_bclk_out_7_unused),
2111 .arb_grant_a (arb_grant_r_a[6]),
2112 .arb_qsel0_a (arb_qsel0_r_a[6]),
2113 .arb_qsel1_a (arb_qsel1_r_a[6]),
2114 .arb_q0_holdbar_a (arb_q0_holdbar_r_a[6]),
2115 .arb_shift_a (arb_shift_r_a[6]),
2116 .src_pcx_data_a (spc6_pcx_data_a[129:0]),
2117 .data_prev_x_ (all_ones[129:0]),
2118 .scan_in (pcx_mac7_scanin),
2119 .scan_out (pcx_mac7_scanout),
2120 .l2clk (l2clk),
2121 .tcu_scan_en (tcu_scan_en_out[6]),
2122 .tcu_pce_ov (tcu_pce_ov_out[6]),
2123 .ccx_aclk (ccx_aclk_out[6]),
2124 .ccx_bclk (ccx_bclk_out[6]));
2125endmodule
2126
2127
2128`endif // `ifdef FPGA
2129
Full OpenSPARC design & verification tarball including full HDL.