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1 | # ========== Copyright Header Begin ========================================== |
2 | # | |
3 | # OpenSPARC T2 Processor File: user_cfg.scr | |
4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | # | |
7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | # | |
9 | # This program is free software; you can redistribute it and/or modify | |
10 | # it under the terms of the GNU General Public License as published by | |
11 | # the Free Software Foundation; version 2 of the License. | |
12 | # | |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
18 | # You should have received a copy of the GNU General Public License | |
19 | # along with this program; if not, write to the Free Software | |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | # | |
22 | # For the avoidance of doubt, and except that if any non-GPL license | |
23 | # choice is available it will apply instead, Sun elects to use only | |
24 | # the General Public License version 2 (GPLv2) at this time for any | |
25 | # software where a choice of GPL license versions is made | |
26 | # available with the language indicating that GPLv2 or any later version | |
27 | # may be used, or where a choice of which version of the GPL is applied is | |
28 | # otherwise unspecified. | |
29 | # | |
30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | # CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | # have any questions. | |
33 | # | |
34 | # ========== Copyright Header End ============================================ | |
35 | source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr | |
36 | ||
37 | set rtl_files {\ | |
38 | libs/cl/cl_rtl_ext.v | |
39 | libs/cl/cl_sc1/cl_sc1.behV | |
40 | libs/cl/cl_u1/cl_u1.behV | |
41 | libs/cl/cl_dp1/cl_dp1.behV | |
42 | libs/cl/cl_u1lvt/cl_u1lvt.behV | |
43 | ||
44 | libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v | |
45 | libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v | |
46 | libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v | |
47 | ||
48 | libs/clk/rtl/clkgen_ccx_cmp.v | |
49 | ||
50 | design/sys/iop/ccx/rtl/ccx.v | |
51 | design/sys/iop/ccx/rtl/ccx_arb.v | |
52 | design/sys/iop/ccx/rtl/ccx_arc_ctl.v | |
53 | design/sys/iop/ccx/rtl/ccx_ard_dp.v | |
54 | design/sys/iop/ccx/rtl/ccx_l1clkhdr_ctl_macro.v | |
55 | design/sys/iop/ccx/rtl/ccx_new_macro.v | |
56 | design/sys/iop/ccx/rtl/ccx_rep.v | |
57 | design/sys/iop/ccx/rtl/ccx_srq_ctl.v | |
58 | design/sys/iop/ccx/rtl/ccx_trep.v | |
59 | design/sys/iop/ccx/rtl/ccx_tstg.v | |
60 | design/sys/iop/ccx/rtl/cpx.v | |
61 | design/sys/iop/ccx/rtl/cpx_bfd_dp.v | |
62 | design/sys/iop/ccx/rtl/cpx_bfg_dp.v | |
63 | design/sys/iop/ccx/rtl/cpx_dpa.v | |
64 | design/sys/iop/ccx/rtl/cpx_dpsa.v | |
65 | design/sys/iop/ccx/rtl/cpx_dpsb.v | |
66 | design/sys/iop/ccx/rtl/cpx_dpsc.v | |
67 | design/sys/iop/ccx/rtl/cpx_dpsd.v | |
68 | design/sys/iop/ccx/rtl/cpx_dpse.v | |
69 | design/sys/iop/ccx/rtl/cpx_dpsf.v | |
70 | design/sys/iop/ccx/rtl/cpx_dpsg.v | |
71 | design/sys/iop/ccx/rtl/cpx_mal_dp.v | |
72 | design/sys/iop/ccx/rtl/cpx_mar_dp.v | |
73 | design/sys/iop/ccx/rtl/cpx_mbl_dp.v | |
74 | design/sys/iop/ccx/rtl/cpx_mbr_dp.v | |
75 | design/sys/iop/ccx/rtl/cpx_mcl_dp.v | |
76 | design/sys/iop/ccx/rtl/cpx_mcr_dp.v | |
77 | design/sys/iop/ccx/rtl/cpx_ob1_dp.v | |
78 | design/sys/iop/ccx/rtl/cpx_ob2_dp.v | |
79 | design/sys/iop/ccx/rtl/cpx_rep_dp.v | |
80 | design/sys/iop/ccx/rtl/inv_diode_macro.v | |
81 | design/sys/iop/ccx/rtl/pcx.v | |
82 | design/sys/iop/ccx/rtl/pcx_bfd_dp.v | |
83 | design/sys/iop/ccx/rtl/pcx_bfg_dp.v | |
84 | design/sys/iop/ccx/rtl/pcx_dpa.v | |
85 | design/sys/iop/ccx/rtl/pcx_dpsa.v | |
86 | design/sys/iop/ccx/rtl/pcx_dpsb.v | |
87 | design/sys/iop/ccx/rtl/pcx_dpsc.v | |
88 | design/sys/iop/ccx/rtl/pcx_dpsd.v | |
89 | design/sys/iop/ccx/rtl/pcx_dpse.v | |
90 | design/sys/iop/ccx/rtl/pcx_dpsf.v | |
91 | design/sys/iop/ccx/rtl/pcx_dpsg.v | |
92 | design/sys/iop/ccx/rtl/pcx_dpsh.v | |
93 | design/sys/iop/ccx/rtl/pcx_mal_dp.v | |
94 | design/sys/iop/ccx/rtl/pcx_mar_dp.v | |
95 | design/sys/iop/ccx/rtl/pcx_mbl_dp.v | |
96 | design/sys/iop/ccx/rtl/pcx_mbr_dp.v | |
97 | design/sys/iop/ccx/rtl/pcx_mcl_dp.v | |
98 | design/sys/iop/ccx/rtl/pcx_mcr_dp.v | |
99 | design/sys/iop/ccx/rtl/pcx_ob1_dp.v | |
100 | design/sys/iop/ccx/rtl/pcx_rep_dp.v | |
101 | } | |
102 | ||
103 | set link_library [concat $link_library \ | |
104 | dw_foundation.sldb \ | |
105 | ] | |
106 | ||
107 | ||
108 | set mix_files {} | |
109 | set top_module ccx | |
110 | ||
111 | set include_paths {\ | |
112 | } | |
113 | ||
114 | set black_box_libs {} | |
115 | set black_box_designs {} | |
116 | set mem_libs {} | |
117 | ||
118 | set dont_touch_modules { \ | |
119 | n2_clk_clstr_hdr_cust \ | |
120 | n2_clk_ccx_cmp_cust \ | |
121 | n2_flop_bank_cust \ | |
122 | } | |
123 | ||
124 | set compile_effort "medium" | |
125 | ||
126 | set compile_flatten_all 1 | |
127 | ||
128 | set compile_no_new_cells_at_top_level false | |
129 | ||
130 | set default_clk cmp_gclk | |
131 | set default_clk_freq 1400 | |
132 | set default_setup_skew 0.0 | |
133 | set default_hold_skew 0.0 | |
134 | set default_clk_transition 0.05 | |
135 | set clk_list { \ | |
136 | { cmp_gclk_c2_ccx_left 1400.0 0.000 0.000 0.05} \ | |
137 | { cmp_gclk_c2_ccx_right 1400.0 0.000 0.000 0.05} \ | |
138 | } | |
139 | ||
140 | set ideal_net_list { cmp_gclk_c2_ccx_left cmp_gclk_c2_ccx_right } | |
141 | set false_path_list {} | |
142 | set enforce_input_fanout_one 0 | |
143 | set allow_outport_drive_innodes 1 | |
144 | set skip_scan 0 | |
145 | set add_lockup_latch false | |
146 | set chain_count 1 | |
147 | set scanin_port_list {} | |
148 | set scanout_port_list {} | |
149 | set scanenable_port global_shift_enable | |
150 | set has_test_stub 1 | |
151 | set scanenable_pin test_stub_no_bist/se | |
152 | set long_chain_so_0_net long_chain_so_0 | |
153 | set short_chain_so_0_net short_chain_so_0 | |
154 | set so_0_net so_0 | |
155 | set insert_extra_lockup_latch 0 | |
156 | set extra_lockup_latch_clk_list {} |