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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / cpu / rtl / cpu.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: cpu.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`define ADDR_MAP_HI 39
39`define ADDR_MAP_LO 32
40`define IO_ADDR_BIT 39
41
42// CMP space
43`define DRAM_DATA_LO 8'h00
44`define DRAM_DATA_HI 8'h7f
45
46// CPU space
47`define JBUS1 8'h80
48`define HASH_TBL_NRAM_CSR 8'h81
49`define RESERVED_1 8'h82
50`define ENET_MAC_CSR 8'h83
51`define ENET_ING_CSR 8'h84
52`define ENET_EGR_CMD_CSR 8'h85
53`define ENET_EGR_DP_CSR 8'h86
54`define RESERVED_2_LO 8'h87
55`define RESERVED_2_HI 8'h92
56`define BSC_CSR 8'h93
57`define RESERVED_3 8'h94
58`define RAND_GEN_CSR 8'h95
59`define CLOCK_UNIT_CSR 8'h96
60`define DRAM_CSR 8'h97
61`define IOB_MAN_CSR 8'h98
62`define TAP_CSR 8'h99
63`define RESERVED_4_L0 8'h9a
64`define RESERVED_4_HI 8'h9d
65`define CPU_ASI 8'h9e
66`define IOB_INT_CSR 8'h9f
67
68// L2 space
69`define L2C_CSR_LO 8'ha0
70`define L2C_CSR_HI 8'hbf
71
72// More CPU space
73`define JBUS2_LO 8'hc0
74`define JBUS2_HI 8'hfe
75`define SPI_CSR 8'hff
76
77
78//Cache Crossbar Width and Field Defines
79//======================================
80`define PCX_WIDTH 130 //PCX payload packet width , BS and
81 // SR 11/12/03 N2 Xbar Packet format change
82`define PCX_WIDTH_LESS1 129 // Needed for Astro, replacing the
83 // expression PCX_WIDTH-1
84`define CPX_WIDTH 146 //CPX payload packet width, BS and
85 // SR 11/12/03 N2 Xbar Packet format change
86`define CPX_WIDTH_LESS1 145 //Needed for Astro, replacing the
87 // expression CPX_WIDTH-1
88`define CPX_WIDTHc 146c //CPX payload packet width , BS and
89 // SR 11/12/03 N2 Xbar Packet format change
90
91`define PCX_VLD 123 //PCX packet valid
92`define PCX_RQ_HI 122 //PCX request type field
93`define PCX_RQ_LO 118
94`define PCX_NC 117 //PCX non-cacheable bit
95`define PCX_R 117 //PCX read/!write bit
96`define PCX_CP_HI 116 //PCX cpu_id field
97`define PCX_CP_LO 114
98`define PCX_TH_HI 113 //PCX Thread field
99`define PCX_TH_LO 112
100`define PCX_BF_HI 111 //PCX buffer id field
101`define PCX_INVALL 111
102`define PCX_BF_LO 109
103`define PCX_WY_HI 108 //PCX replaced L1 way field
104`define PCX_WY_LO 107
105`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
106`define PCX_P_LO 107
107`define PCX_SZ_HI 106 //PCX load/store size field
108`define PCX_SZ_LO 104
109`define PCX_ERR_HI 106 //PCX error field
110`define PCX_ERR_LO 104
111`define PCX_AD_HI 103 //PCX address field
112`define PCX_AD_LO 64
113`define PCX_DA_HI 63 //PCX Store data
114`define PCX_DA_LO 0
115
116`define PCX_SZ_1B 3'b000 // encoding for 1B access
117`define PCX_SZ_2B 3'b001 // encoding for 2B access
118`define PCX_SZ_4B 3'b010 // encoding for 4B access
119`define PCX_SZ_8B 3'b011 // encoding for 8B access
120`define PCX_SZ_16B 3'b100 // encoding for 16B access
121
122`define CPX_VLD 145 //CPX payload packet valid
123
124`define CPX_RQ_HI 144 //CPX Request type
125`define CPX_RQ_LO 141
126`define CPX_L2MISS 140
127`define CPX_ERR_HI 140 //CPX error field
128`define CPX_ERR_LO 138
129`define CPX_NC 137 //CPX non-cacheable
130`define CPX_TH_HI 136 //CPX thread ID field
131`define CPX_TH_LO 134
132
133//bits 133:128 are shared by different fields
134//for different packet types.
135
136`define CPX_IN_HI 133 //CPX Interrupt source
137`define CPX_IN_LO 128
138
139`define CPX_WYVLD 133 //CPX replaced way valid
140`define CPX_WY_HI 132 //CPX replaced I$/D$ way
141`define CPX_WY_LO 131
142`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
143`define CPX_BF_LO 128
144
145`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
146`define CPX_SI_LO 128 //used for invalidates
147
148`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
149`define CPX_P_LO 130
150
151`define CPX_ASI 130 //CPX forward request to ASI
152`define CPX_IF4B 130
153`define CPX_IINV 124
154`define CPX_DINV 123
155`define CPX_INVPA5 122
156`define CPX_INVPA4 121
157`define CPX_CPUID_HI 120
158`define CPX_CPUID_LO 118
159`define CPX_INV_PA_HI 116
160`define CPX_INV_PA_LO 112
161`define CPX_INV_IDX_HI 117
162`define CPX_INV_IDX_LO 112
163
164`define CPX_DA_HI 127 //CPX data payload
165`define CPX_DA_LO 0
166
167`define LOAD_RQ 5'b00000
168`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
169`define IMISS_RQ 5'b10000
170`define STORE_RQ 5'b00001
171`define CAS1_RQ 5'b00010
172`define CAS2_RQ 5'b00011
173`define SWAP_RQ 5'b00111
174`define STRLOAD_RQ 5'b00100
175`define STRST_RQ 5'b00101
176`define STQ_RQ 5'b00111
177`define INT_RQ 5'b01001
178`define FWD_RQ 5'b01101
179`define FWD_RPY 5'b01110
180`define RSVD_RQ 5'b11111
181
182`define LOAD_RET 4'b0000
183`define INV_RET 4'b0011
184`define ST_ACK 4'b0100
185`define AT_ACK 4'b0011
186`define INT_RET 4'b0111
187`define TEST_RET 4'b0101
188`define FP_RET 4'b1000
189`define IFILL_RET 4'b0001
190`define EVICT_REQ 4'b0011
191//`define INVAL_ACK 4'b1000
192`define INVAL_ACK 4'b0100
193`define ERR_RET 4'b1100
194`define STRLOAD_RET 4'b0010
195`define STRST_ACK 4'b0110
196`define FWD_RQ_RET 4'b1010
197`define FWD_RPY_RET 4'b1011
198`define RSVD_RET 4'b1111
199
200//End cache crossbar defines
201
202
203// Number of COS supported by EECU
204`define EECU_COS_NUM 2
205
206
207//
208// BSC bus sizes
209// =============
210//
211
212// General
213`define BSC_ADDRESS 40
214`define MAX_XFER_LEN 7'b0
215`define XFER_LEN_WIDTH 6
216
217// CTags
218`define BSC_CTAG_SZ 12
219`define EICU_CTAG_PRE 5'b11101
220`define EICU_CTAG_REM 7
221`define EIPU_CTAG_PRE 3'b011
222`define EIPU_CTAG_REM 9
223`define EECU_CTAG_PRE 8'b11010000
224`define EECU_CTAG_REM 4
225`define EEPU_CTAG_PRE 6'b010000
226`define EEPU_CTAG_REM 6
227`define L2C_CTAG_PRE 2'b00
228`define L2C_CTAG_REM 10
229`define JBI_CTAG_PRE 2'b10
230`define JBI_CTAG_REM 10
231// reinstated temporarily
232`define PCI_CTAG_PRE 7'b1101100
233`define PCI_CTAG_REM 5
234
235
236// CoS
237`define EICU_COS 1'b0
238`define EIPU_COS 1'b1
239`define EECU_COS 1'b0
240`define EEPU_COS 1'b1
241`define PCI_COS 1'b0
242
243// L2$ Bank
244`define BSC_L2_BNK_HI 8
245`define BSC_L2_BNK_LO 6
246
247// L2$ Req
248`define BSC_L2_REQ_SZ 62
249`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
250`define BSC_L2_BUS 64
251`define BSC_L2_CTAG_HI 61
252`define BSC_L2_CTAG_LO 50
253`define BSC_L2_ADD_HI 49
254`define BSC_L2_ADD_LO 10
255`define BSC_L2_LEN_HI 9
256`define BSC_L2_LEN_LO 3
257`define BSC_L2_ALLOC 2
258`define BSC_L2_COS 1
259`define BSC_L2_READ 0
260
261// L2$ Ack
262`define L2_BSC_ACK_SZ 16
263`define L2_BSC_BUS 64
264`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
265`define L2_BSC_CBA_LO 13
266`define L2_BSC_READ 12
267`define L2_BSC_CTAG_HI 11
268`define L2_BSC_CTAG_LO 0
269
270// Enet Egress Command Unit
271`define EECU_REQ_BUS 44
272`define EECU_REQ_SZ 44
273`define EECU_R_QID_HI 43
274`define EECU_R_QID_LO 40
275`define EECU_R_ADD_HI 39
276`define EECU_R_ADD_LO 0
277
278`define EECU_ACK_BUS 64
279`define EECU_ACK_SZ 5
280`define EECU_A_NACK 4
281`define EECU_A_QID_HI 3
282`define EECU_A_QID_LO 0
283
284
285// Enet Egress Packet Unit
286`define EEPU_REQ_BUS 55
287`define EEPU_REQ_SZ 55
288`define EEPU_R_TLEN_HI 54
289`define EEPU_R_TLEN_LO 48
290`define EEPU_R_SOF 47
291`define EEPU_R_EOF 46
292`define EEPU_R_PORT_HI 45
293`define EEPU_R_PORT_LO 44
294`define EEPU_R_QID_HI 43
295`define EEPU_R_QID_LO 40
296`define EEPU_R_ADD_HI 39
297`define EEPU_R_ADD_LO 0
298
299// This is cleaved in between Egress Datapath Ack's
300`define EEPU_ACK_BUS 6
301`define EEPU_ACK_SZ 6
302`define EEPU_A_EOF 5
303`define EEPU_A_NACK 4
304`define EEPU_A_QID_HI 3
305`define EEPU_A_QID_LO 0
306
307
308// Enet Egress Datapath
309`define EEDP_ACK_BUS 128
310`define EEDP_ACK_SZ 28
311`define EEDP_A_NACK 27
312`define EEDP_A_QID_HI 26
313`define EEDP_A_QID_LO 21
314`define EEDP_A_SOF 20
315`define EEDP_A_EOF 19
316`define EEDP_A_LEN_HI 18
317`define EEDP_A_LEN_LO 12
318`define EEDP_A_TAG_HI 11
319`define EEDP_A_TAG_LO 0
320`define EEDP_A_PORT_HI 5
321`define EEDP_A_PORT_LO 4
322`define EEDP_A_PORT_WIDTH 2
323
324
325// In-Order / Ordered Queue: EEPU
326// Tag is: TLEN, SOF, EOF, QID = 15
327`define EEPU_TAG_ARY (7+1+1+6)
328`define EEPU_ENTRIES 16
329`define EEPU_E_IDX 4
330`define EEPU_PORTS 4
331`define EEPU_P_IDX 2
332
333// Nack + Tag Info + CTag
334`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
335`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
336
337
338// ENET Ingress Queue Management Req
339`define EICU_REQ_BUS 64
340`define EICU_REQ_SZ 62
341`define EICU_R_CTAG_HI 61
342`define EICU_R_CTAG_LO 50
343`define EICU_R_ADD_HI 49
344`define EICU_R_ADD_LO 10
345`define EICU_R_LEN_HI 9
346`define EICU_R_LEN_LO 3
347`define EICU_R_COS 1
348`define EICU_R_READ 0
349
350
351// ENET Ingress Queue Management Ack
352`define EICU_ACK_BUS 64
353`define EICU_ACK_SZ 14
354`define EICU_A_NACK 13
355`define EICU_A_READ 12
356`define EICU_A_CTAG_HI 11
357`define EICU_A_CTAG_LO 0
358
359
360// Enet Ingress Packet Unit
361`define EIPU_REQ_BUS 128
362`define EIPU_REQ_SZ 59
363`define EIPU_R_CTAG_HI 58
364`define EIPU_R_CTAG_LO 50
365`define EIPU_R_ADD_HI 49
366`define EIPU_R_ADD_LO 10
367`define EIPU_R_LEN_HI 9
368`define EIPU_R_LEN_LO 3
369`define EIPU_R_COS 1
370`define EIPU_R_READ 0
371
372
373// ENET Ingress Packet Unit Ack
374`define EIPU_ACK_BUS 10
375`define EIPU_ACK_SZ 10
376`define EIPU_A_NACK 9
377`define EIPU_A_CTAG_HI 8
378`define EIPU_A_CTAG_LO 0
379
380
381// In-Order / Ordered Queue: PCI
382// Tag is: CTAG
383`define PCI_TAG_ARY 12
384`define PCI_ENTRIES 16
385`define PCI_E_IDX 4
386`define PCI_PORTS 2
387
388// PCI-X Request
389`define PCI_REQ_BUS 64
390`define PCI_REQ_SZ 62
391`define PCI_R_CTAG_HI 61
392`define PCI_R_CTAG_LO 50
393`define PCI_R_ADD_HI 49
394`define PCI_R_ADD_LO 10
395`define PCI_R_LEN_HI 9
396`define PCI_R_LEN_LO 3
397`define PCI_R_COS 1
398`define PCI_R_READ 0
399
400// PCI_X Acknowledge
401`define PCI_ACK_BUS 64
402`define PCI_ACK_SZ 14
403`define PCI_A_NACK 13
404`define PCI_A_READ 12
405`define PCI_A_CTAG_HI 11
406`define PCI_A_CTAG_LO 0
407
408
409`define BSC_MAX_REQ_SZ 62
410
411
412//
413// BSC array sizes
414//================
415//
416`define BSC_REQ_ARY_INDEX 6
417`define BSC_REQ_ARY_DEPTH 64
418`define BSC_REQ_ARY_WIDTH 62
419`define BSC_REQ_NXT_WIDTH 12
420`define BSC_ACK_ARY_INDEX 6
421`define BSC_ACK_ARY_DEPTH 64
422`define BSC_ACK_ARY_WIDTH 14
423`define BSC_ACK_NXT_WIDTH 12
424`define BSC_PAY_ARY_INDEX 6
425`define BSC_PAY_ARY_DEPTH 64
426`define BSC_PAY_ARY_WIDTH 256
427
428// ECC syndrome bits per memory element
429`define BSC_PAY_ECC 10
430`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
431
432
433//
434// BSC Port Definitions
435// ====================
436//
437// Bits 7 to 4 of curr_port_id
438`define BSC_PORT_NULL 4'h0
439`define BSC_PORT_SC 4'h1
440`define BSC_PORT_EICU 4'h2
441`define BSC_PORT_EIPU 4'h3
442`define BSC_PORT_EECU 4'h4
443`define BSC_PORT_EEPU 4'h8
444`define BSC_PORT_PCI 4'h9
445
446// Number of ports of each type
447`define BSC_PORT_SC_CNT 8
448
449// Bits needed to represent above
450`define BSC_PORT_SC_IDX 3
451
452// How wide the linked list pointers are
453// 60b for no payload (2CoS)
454// 80b for payload (2CoS)
455
456//`define BSC_OBJ_PTR 80
457//`define BSC_HD1_HI 69
458//`define BSC_HD1_LO 60
459//`define BSC_TL1_HI 59
460//`define BSC_TL1_LO 50
461//`define BSC_CT1_HI 49
462//`define BSC_CT1_LO 40
463//`define BSC_HD0_HI 29
464//`define BSC_HD0_LO 20
465//`define BSC_TL0_HI 19
466//`define BSC_TL0_LO 10
467//`define BSC_CT0_HI 9
468//`define BSC_CT0_LO 0
469
470`define BSC_OBJP_PTR 48
471`define BSC_PYP1_HI 47
472`define BSC_PYP1_LO 42
473`define BSC_HDP1_HI 41
474`define BSC_HDP1_LO 36
475`define BSC_TLP1_HI 35
476`define BSC_TLP1_LO 30
477`define BSC_CTP1_HI 29
478`define BSC_CTP1_LO 24
479`define BSC_PYP0_HI 23
480`define BSC_PYP0_LO 18
481`define BSC_HDP0_HI 17
482`define BSC_HDP0_LO 12
483`define BSC_TLP0_HI 11
484`define BSC_TLP0_LO 6
485`define BSC_CTP0_HI 5
486`define BSC_CTP0_LO 0
487
488`define BSC_PTR_WIDTH 192
489`define BSC_PTR_REQ_HI 191
490`define BSC_PTR_REQ_LO 144
491`define BSC_PTR_REQP_HI 143
492`define BSC_PTR_REQP_LO 96
493`define BSC_PTR_ACK_HI 95
494`define BSC_PTR_ACK_LO 48
495`define BSC_PTR_ACKP_HI 47
496`define BSC_PTR_ACKP_LO 0
497
498`define BSC_PORT_SC_PTR 96 // R, R+P
499`define BSC_PORT_EECU_PTR 48 // A+P
500`define BSC_PORT_EICU_PTR 96 // A, A+P
501`define BSC_PORT_EIPU_PTR 48 // A
502
503// I2C STATES in DRAMctl
504`define I2C_CMD_NOP 4'b0000
505`define I2C_CMD_START 4'b0001
506`define I2C_CMD_STOP 4'b0010
507`define I2C_CMD_WRITE 4'b0100
508`define I2C_CMD_READ 4'b1000
509
510
511//
512// IOB defines
513// ===========
514//
515`define IOB_ADDR_WIDTH 40
516`define IOB_LOCAL_ADDR_WIDTH 32
517
518`define IOB_CPU_INDEX 3
519`define IOB_CPU_WIDTH 8
520`define IOB_THR_INDEX 2
521`define IOB_THR_WIDTH 4
522`define IOB_CPUTHR_INDEX 5
523`define IOB_CPUTHR_WIDTH 32
524
525`define IOB_MONDO_DATA_INDEX 5
526`define IOB_MONDO_DATA_DEPTH 32
527`define IOB_MONDO_DATA_WIDTH 64
528`define IOB_MONDO_SRC_WIDTH 5
529`define IOB_MONDO_BUSY 5
530
531`define IOB_INT_TAB_INDEX 6
532`define IOB_INT_TAB_DEPTH 64
533
534`define IOB_INT_STAT_WIDTH 32
535`define IOB_INT_STAT_HI 31
536`define IOB_INT_STAT_LO 0
537
538`define IOB_INT_VEC_WIDTH 6
539`define IOB_INT_VEC_HI 5
540`define IOB_INT_VEC_LO 0
541
542`define IOB_INT_CPU_WIDTH 5
543`define IOB_INT_CPU_HI 12
544`define IOB_INT_CPU_LO 8
545
546`define IOB_INT_MASK 2
547`define IOB_INT_CLEAR 1
548`define IOB_INT_PEND 0
549
550`define IOB_DISP_TYPE_HI 17
551`define IOB_DISP_TYPE_LO 16
552`define IOB_DISP_THR_HI 12
553`define IOB_DISP_THR_LO 8
554`define IOB_DISP_VEC_HI 5
555`define IOB_DISP_VEC_LO 0
556
557`define IOB_JBI_RESET 1
558`define IOB_ENET_RESET 0
559
560`define IOB_RESET_STAT_WIDTH 3
561`define IOB_RESET_STAT_HI 3
562`define IOB_RESET_STAT_LO 1
563
564`define IOB_SERNUM_WIDTH 64
565
566`define IOB_FUSE_WIDTH 22
567
568`define IOB_TMSTAT_THERM 63
569
570`define IOB_POR_TT 6'b01 // power-on-reset trap type
571
572`define IOB_CPU_BUF_INDEX 4
573
574`define IOB_INT_BUF_INDEX 4
575`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
576
577`define IOB_IO_BUF_INDEX 4
578`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
579
580`define IOB_L2_VIS_BUF_INDEX 5
581`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
582
583`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
584`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
585
586// fixme - double check address mapping
587// CREG in `IOB_INT_CSR space
588`define IOB_DEV_ADDR_MASK 32'hfffffe07
589`define IOB_CREG_INTSTAT 32'h00000000
590`define IOB_CREG_MDATA0 32'h00000400
591`define IOB_CREG_MDATA1 32'h00000500
592`define IOB_CREG_MBUSY 32'h00000900
593`define IOB_THR_ADDR_MASK 32'hffffff07
594`define IOB_CREG_MDATA0_ALIAS 32'h00000600
595`define IOB_CREG_MDATA1_ALIAS 32'h00000700
596`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
597
598// CREG in `IOB_MAN_CSR space
599`define IOB_CREG_INTMAN 32'h00000000
600`define IOB_CREG_INTCTL 32'h00000400
601`define IOB_CREG_INTVECDISP 32'h00000800
602`define IOB_CREG_RESETSTAT 32'h00000810
603`define IOB_CREG_SERNUM 32'h00000820
604`define IOB_CREG_TMSTATCTRL 32'h00000828
605`define IOB_CREG_COREAVAIL 32'h00000830
606`define IOB_CREG_SSYSRESET 32'h00000838
607`define IOB_CREG_FUSESTAT 32'h00000840
608`define IOB_CREG_JINTV 32'h00000a00
609
610`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
611`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
612`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
613`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
614`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
615`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
616`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
617`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
618`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
619`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
620`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
621`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
622`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
623`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
624`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
625`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
626`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
627`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
628`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
629`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
630`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
631`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
632
633`define IOB_CREG_TESTSTUB 32'h80000000
634
635// Address map for TAP access of SPARC ASI
636`define IOB_ASI_PC 4'b0000
637`define IOB_ASI_BIST 4'b0001
638`define IOB_ASI_MARGIN 4'b0010
639`define IOB_ASI_DEFEATURE 4'b0011
640`define IOB_ASI_L1DD 4'b0100
641`define IOB_ASI_L1ID 4'b0101
642`define IOB_ASI_L1DT 4'b0110
643
644`define IOB_INT 2'b00
645`define IOB_RESET 2'b01
646`define IOB_IDLE 2'b10
647`define IOB_RESUME 2'b11
648
649//
650// CIOP UCB Bus Width
651// ==================
652//
653`define IOB_EECU_WIDTH 16 // ethernet egress command
654`define EECU_IOB_WIDTH 16
655
656`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
657`define NRAM_IOB_WIDTH 4
658
659`define IOB_JBI_WIDTH 16 // JBI
660`define JBI_IOB_WIDTH 16
661
662`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
663`define ENET_ING_IOB_WIDTH 8
664
665`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
666`define ENET_EGR_IOB_WIDTH 4
667
668`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
669`define ENET_MAC_IOB_WIDTH 4
670
671`define IOB_DRAM_WIDTH 4 // DRAM controller
672`define DRAM_IOB_WIDTH 4
673
674`define IOB_BSC_WIDTH 4 // BSC
675`define BSC_IOB_WIDTH 4
676
677`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
678`define SPI_IOB_WIDTH 4
679
680`define IOB_CLK_WIDTH 4 // clk unit
681`define CLK_IOB_WIDTH 4
682
683`define IOB_CLSP_WIDTH 4 // clk spine unit
684`define CLSP_IOB_WIDTH 4
685
686`define IOB_TAP_WIDTH 8 // TAP
687`define TAP_IOB_WIDTH 8
688
689
690//
691// CIOP UCB Buf ID Type
692// ====================
693//
694`define UCB_BID_CMP 2'b00
695`define UCB_BID_TAP 2'b01
696
697//
698// Interrupt Device ID
699// ===================
700//
701// Caution: DUMMY_DEV_ID has to be 9 bit wide
702// for fields to line up properly in the IOB.
703`define DUMMY_DEV_ID 9'h10 // 16
704`define UNCOR_ECC_DEV_ID 7'd17 // 17
705
706//
707// Soft Error related definitions
708// ==============================
709//
710`define COR_ECC_CNT_WIDTH 16
711
712
713//
714// CMP clock
715// =========
716//
717
718`define CMP_CLK_PERIOD 1333
719
720
721//
722// NRAM/IO Interface
723// =================
724//
725
726`define DRAM_CLK_PERIOD 6000
727
728`define NRAM_IO_DQ_WIDTH 32
729`define IO_NRAM_DQ_WIDTH 32
730
731`define NRAM_IO_ADDR_WIDTH 15
732`define NRAM_IO_BA_WIDTH 2
733
734
735//
736// NRAM/ENET Interface
737// ===================
738//
739
740`define NRAM_ENET_DATA_WIDTH 64
741`define ENET_NRAM_ADDR_WIDTH 20
742
743`define NRAM_DBG_DATA_WIDTH 40
744
745
746//
747// IO/FCRAM Interface
748// ==================
749//
750
751`define FCRAM_DATA1_HI 63
752`define FCRAM_DATA1_LO 32
753`define FCRAM_DATA0_HI 31
754`define FCRAM_DATA0_LO 0
755
756//
757// PCI Interface
758// ==================
759// Load/store size encodings
760// -------------------------
761// Size encoding
762// 000 - byte
763// 001 - half-word
764// 010 - word
765// 011 - double-word
766// 100 - quad
767`define LDST_SZ_BYTE 3'b000
768`define LDST_SZ_HALF_WORD 3'b001
769`define LDST_SZ_WORD 3'b010
770`define LDST_SZ_DOUBLE_WORD 3'b011
771`define LDST_SZ_QUAD 3'b100
772
773//
774// JBI<->SCTAG Interface
775// =======================
776// Outbound Header Format
777`define JBI_BTU_OUT_ADDR_LO 0
778`define JBI_BTU_OUT_ADDR_HI 42
779`define JBI_BTU_OUT_RSV0_LO 43
780`define JBI_BTU_OUT_RSV0_HI 43
781`define JBI_BTU_OUT_TYPE_LO 44
782`define JBI_BTU_OUT_TYPE_HI 48
783`define JBI_BTU_OUT_RSV1_LO 49
784`define JBI_BTU_OUT_RSV1_HI 51
785`define JBI_BTU_OUT_REPLACE_LO 52
786`define JBI_BTU_OUT_REPLACE_HI 56
787`define JBI_BTU_OUT_RSV2_LO 57
788`define JBI_BTU_OUT_RSV2_HI 59
789`define JBI_BTU_OUT_BTU_ID_LO 60
790`define JBI_BTU_OUT_BTU_ID_HI 71
791`define JBI_BTU_OUT_DATA_RTN 72
792`define JBI_BTU_OUT_RSV3_LO 73
793`define JBI_BTU_OUT_RSV3_HI 75
794`define JBI_BTU_OUT_CE 76
795`define JBI_BTU_OUT_RSV4_LO 77
796`define JBI_BTU_OUT_RSV4_HI 79
797`define JBI_BTU_OUT_UE 80
798`define JBI_BTU_OUT_RSV5_LO 81
799`define JBI_BTU_OUT_RSV5_HI 83
800`define JBI_BTU_OUT_DRAM 84
801`define JBI_BTU_OUT_RSV6_LO 85
802`define JBI_BTU_OUT_RSV6_HI 127
803
804// Inbound Header Format
805`define JBI_SCTAG_IN_ADDR_LO 0
806`define JBI_SCTAG_IN_ADDR_HI 39
807`define JBI_SCTAG_IN_SZ_LO 40
808`define JBI_SCTAG_IN_SZ_HI 42
809`define JBI_SCTAG_IN_RSV0 43
810`define JBI_SCTAG_IN_TAG_LO 44
811`define JBI_SCTAG_IN_TAG_HI 55
812`define JBI_SCTAG_IN_REQ_LO 56
813`define JBI_SCTAG_IN_REQ_HI 58
814`define JBI_SCTAG_IN_POISON 59
815`define JBI_SCTAG_IN_RSV1_LO 60
816`define JBI_SCTAG_IN_RSV1_HI 63
817
818`define JBI_SCTAG_REQ_WRI 3'b100
819`define JBI_SCTAG_REQ_WR8 3'b010
820`define JBI_SCTAG_REQ_RDD 3'b001
821`define JBI_SCTAG_REQ_WRI_BIT 2
822`define JBI_SCTAG_REQ_WR8_BIT 1
823`define JBI_SCTAG_REQ_RDD_BIT 0
824
825//
826// JBI->IOB Mondo Header Format
827// ============================
828//
829`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
830`define JBI_IOB_MONDO_RSV1_LO 13
831`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
832`define JBI_IOB_MONDO_TRG_LO 8
833`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
834`define JBI_IOB_MONDO_RSV0_LO 5
835`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
836`define JBI_IOB_MONDO_SRC_LO 0
837
838`define JBI_IOB_MONDO_RSV1_WIDTH 3
839`define JBI_IOB_MONDO_TRG_WIDTH 5
840`define JBI_IOB_MONDO_RSV0_WIDTH 3
841`define JBI_IOB_MONDO_SRC_WIDTH 5
842
843// JBI->IOB Mondo Bus Width/Cycle
844// ==============================
845// Cycle 1 Header[15:8]
846// Cycle 2 Header[ 7:0]
847// Cycle 3 J_AD[127:120]
848// Cycle 4 J_AD[119:112]
849// .....
850// Cycle 18 J_AD[ 7: 0]
851`define JBI_IOB_MONDO_BUS_WIDTH 8
852`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
853
854`define CLIENT_ZCP 0
855`define CLIENT_TXC 1
856`define CLIENT_TDMC 2
857`define CLIENT_RDC 3
858`define CLIENT_RCR 4
859`define CLIENT_RBR 5
860
Full OpenSPARC design & verification tarball including full HDL.