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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: db0_rtc_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module db0_rtc_dp ( | |
36 | l2clk, | |
37 | io_cmp_sync_en, | |
38 | cmp_io2x_sync_en, | |
39 | red_rtc_rep_bus, | |
40 | scan_in, | |
41 | scan_out, | |
42 | tcu_pce_ov, | |
43 | tcu_clk_stop, | |
44 | tcu_aclk, | |
45 | tcu_bclk, | |
46 | tcu_scan_en, | |
47 | l2t0_dbg0_sii_iq_dequeue, | |
48 | l2t2_dbg0_sii_iq_dequeue, | |
49 | l2t0_dbg0_sii_wib_dequeue, | |
50 | l2t2_dbg0_sii_wib_dequeue, | |
51 | l2t0_dbg0_err_event, | |
52 | l2t2_dbg0_err_event, | |
53 | l2t0_dbg0_pa_match, | |
54 | l2t2_dbg0_pa_match, | |
55 | l2t0_dbg0_xbar_vcid, | |
56 | l2t2_dbg0_xbar_vcid, | |
57 | l2b0_dbg0_sio_ctag_vld, | |
58 | l2b1_dbg0_sio_ctag_vld, | |
59 | l2b2_dbg0_sio_ctag_vld, | |
60 | l2b3_dbg0_sio_ctag_vld, | |
61 | l2b0_dbg0_sio_ack_type, | |
62 | l2b1_dbg0_sio_ack_type, | |
63 | l2b2_dbg0_sio_ack_type, | |
64 | l2b3_dbg0_sio_ack_type, | |
65 | l2b0_dbg0_sio_ack_dest, | |
66 | l2b1_dbg0_sio_ack_dest, | |
67 | l2b2_dbg0_sio_ack_dest, | |
68 | l2b3_dbg0_sio_ack_dest, | |
69 | spc0_dbg0_instr_cmt_grp0, | |
70 | spc0_dbg0_instr_cmt_grp1, | |
71 | spc2_dbg0_instr_cmt_grp0, | |
72 | spc2_dbg0_instr_cmt_grp1, | |
73 | dbg0_dbg1_debug_data, | |
74 | dbg0_dbg1_l2t0_sii_iq_dequeue, | |
75 | dbg0_dbg1_l2t2_sii_iq_dequeue, | |
76 | dbg0_dbg1_l2t0_sii_wib_dequeue, | |
77 | dbg0_dbg1_l2t2_sii_wib_dequeue, | |
78 | dbg0_dbg1_l2t0_err_event, | |
79 | dbg0_dbg1_l2t2_err_event, | |
80 | dbg0_dbg1_l2t0_pa_match, | |
81 | dbg0_dbg1_l2t2_pa_match, | |
82 | dbg0_dbg1_l2t0_xbar_vcid, | |
83 | dbg0_dbg1_l2t2_xbar_vcid, | |
84 | dbg0_dbg1_spc0_instr_cmt_grp0, | |
85 | dbg0_dbg1_spc0_instr_cmt_grp1, | |
86 | dbg0_dbg1_spc2_instr_cmt_grp0, | |
87 | dbg0_dbg1_spc2_instr_cmt_grp1, | |
88 | dbg0_dbg1_l2b0_sio_ctag_vld, | |
89 | dbg0_dbg1_l2b1_sio_ctag_vld, | |
90 | dbg0_dbg1_l2b2_sio_ctag_vld, | |
91 | dbg0_dbg1_l2b3_sio_ctag_vld, | |
92 | dbg0_dbg1_l2b0_sio_ack_type, | |
93 | dbg0_dbg1_l2b1_sio_ack_type, | |
94 | dbg0_dbg1_l2b2_sio_ack_type, | |
95 | dbg0_dbg1_l2b3_sio_ack_type, | |
96 | dbg0_dbg1_l2b0_sio_ack_dest, | |
97 | dbg0_dbg1_l2b1_sio_ack_dest, | |
98 | dbg0_dbg1_l2b2_sio_ack_dest, | |
99 | dbg0_dbg1_l2b3_sio_ack_dest); | |
100 | wire pce_ov; | |
101 | wire stop; | |
102 | wire siclk; | |
103 | wire soclk; | |
104 | wire se; | |
105 | wire ff_io_sync_en_scanin; | |
106 | wire ff_io_sync_en_scanout; | |
107 | wire dbg0_io_cmp_sync_en_2; | |
108 | wire dbg0_io_cmp_sync_en_3; | |
109 | wire dbg0_io_cmp_sync_en_4; | |
110 | wire dbg0_io_cmp_sync_en_5; | |
111 | wire dbg0_io_cmp_sync_en_32; | |
112 | wire dbg0_io_cmp_sync_en_42; | |
113 | wire dbg0_io_cmp_sync_en_52; | |
114 | wire dbg0_io_cmp_sync_en_6; | |
115 | wire dbg0_io_cmp_sync_en_62; | |
116 | wire cmp_io2x_sync_en_2; | |
117 | wire dbg0_io_cmp_sync_en_3or4; | |
118 | wire dbg0_io_cmp_sync_en_32or42; | |
119 | wire dbg0_io_cmp_sync_en_5or6; | |
120 | wire dbg0_io_cmp_sync_en_52or62; | |
121 | wire ff_red_rtc_rep_bus_slice0_scanin; | |
122 | wire ff_red_rtc_rep_bus_slice0_scanout; | |
123 | wire ff_red_rtc_rep_bus_slice1_scanin; | |
124 | wire ff_red_rtc_rep_bus_slice1_scanout; | |
125 | wire ff_red_rtc_rep_bus_slice2_scanin; | |
126 | wire ff_red_rtc_rep_bus_slice2_scanout; | |
127 | wire ff_red_rtc_rep_bus_slice3_scanin; | |
128 | wire ff_red_rtc_rep_bus_slice3_scanout; | |
129 | wire ff_red_rtc_rep_bus_slice4_scanin; | |
130 | wire ff_red_rtc_rep_bus_slice4_scanout; | |
131 | wire ff_red_rtc_rep_bus_slice5_scanin; | |
132 | wire ff_red_rtc_rep_bus_slice5_scanout; | |
133 | wire ff_red_rtc_rep_bus_slice6_scanin; | |
134 | wire ff_red_rtc_rep_bus_slice6_scanout; | |
135 | wire ff_red_rtc_rep_bus_slice7_scanin; | |
136 | wire ff_red_rtc_rep_bus_slice7_scanout; | |
137 | wire ff_rep_bus_slice0_scanin; | |
138 | wire ff_rep_bus_slice0_scanout; | |
139 | wire ff_rep_bus_slice1_scanin; | |
140 | wire ff_rep_bus_slice1_scanout; | |
141 | wire ff_rep_bus_slice2_scanin; | |
142 | wire ff_rep_bus_slice2_scanout; | |
143 | wire ff_rep_bus_slice3_scanin; | |
144 | wire ff_rep_bus_slice3_scanout; | |
145 | ||
146 | ||
147 | input l2clk; //Internal CMP clock from CCU | |
148 | input io_cmp_sync_en; // IO to CMP sync enable | |
149 | input cmp_io2x_sync_en; // CMP to IO2X sync enable | |
150 | input [331:0] red_rtc_rep_bus; // repeatability bus from rtc_dp module | |
151 | ||
152 | input scan_in; | |
153 | output scan_out; | |
154 | input tcu_pce_ov; | |
155 | input tcu_clk_stop; | |
156 | input tcu_aclk; | |
157 | input tcu_bclk; | |
158 | input tcu_scan_en; | |
159 | ||
160 | ||
161 | input l2t0_dbg0_sii_iq_dequeue; //L2t 0 dequeue from IQ | |
162 | input l2t2_dbg0_sii_iq_dequeue; //L2t 2 dequeue from IQ | |
163 | input l2t0_dbg0_sii_wib_dequeue; //L2t 0 dequeue from IOWB | |
164 | input l2t2_dbg0_sii_wib_dequeue; //L2t 2 dequeue from IOWB | |
165 | input l2t0_dbg0_err_event; //An Error event occurred in l2t 0 | |
166 | input l2t2_dbg0_err_event; //An Error event occurred in l2t 2 | |
167 | input l2t0_dbg0_pa_match; //A PA match detected in l2t 0 | |
168 | input l2t2_dbg0_pa_match; //A PA match detected in l2t 2 | |
169 | input [5:0] l2t0_dbg0_xbar_vcid; //VCID[5:0] from Xbar to L2t 0 | |
170 | input [5:0] l2t2_dbg0_xbar_vcid; //VCID[5:0] from Xbar to L2t 2 | |
171 | input l2b0_dbg0_sio_ctag_vld; //Ctag valid from L2b 0 to SIO | |
172 | input l2b1_dbg0_sio_ctag_vld; //Ctag valid from L2b 1 to SIO | |
173 | input l2b2_dbg0_sio_ctag_vld; //Ctag valid from L2b 2 to SIO | |
174 | input l2b3_dbg0_sio_ctag_vld; //Ctag valid from L2b 3 to SIO | |
175 | input l2b0_dbg0_sio_ack_type; //Read or Wr ack from L2b 0 to SIO | |
176 | input l2b1_dbg0_sio_ack_type; //Read or Wr ack from L2b 1 to SIO | |
177 | input l2b2_dbg0_sio_ack_type; //Read or Wr ack from L2b 2 to SIO | |
178 | input l2b3_dbg0_sio_ack_type; //Read or Wr ack from L2b 3 to SIO | |
179 | input l2b0_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 0 to SIO | |
180 | input l2b1_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 1 to SIO | |
181 | input l2b2_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 2 to SIO | |
182 | input l2b3_dbg0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 3 to SIO | |
183 | input [1:0] spc0_dbg0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 0 | |
184 | input [1:0] spc0_dbg0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 0 | |
185 | input [1:0] spc2_dbg0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 2 | |
186 | input [1:0] spc2_dbg0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 2 | |
187 | ||
188 | ||
189 | output [165:0] dbg0_dbg1_debug_data; // 166 bit debug data bus carrying repeatability signals to DBG1 | |
190 | output dbg0_dbg1_l2t0_sii_iq_dequeue; //L2t 0 dequeue from IQ : flopped version | |
191 | output dbg0_dbg1_l2t2_sii_iq_dequeue; //L2t 2 dequeue from IQ : flopped version | |
192 | output dbg0_dbg1_l2t0_sii_wib_dequeue; //L2t 0 dequeue from IOWB : flopped version | |
193 | output dbg0_dbg1_l2t2_sii_wib_dequeue; //L2t 2 dequeue from IOWB : flopped version | |
194 | output dbg0_dbg1_l2t0_err_event; //An Error event occurred in l2t 0 : flopped version | |
195 | output dbg0_dbg1_l2t2_err_event; //An Error event occurred in l2t 2 : flopped version | |
196 | output dbg0_dbg1_l2t0_pa_match; //A PA match detected in l2t 0 : flopped version | |
197 | output dbg0_dbg1_l2t2_pa_match; //A PA match detected in l2t 2 : flopped version | |
198 | output [5:0] dbg0_dbg1_l2t0_xbar_vcid; //VCID[5:0] from Xbar to L2t 0 : flopped version | |
199 | output [5:0] dbg0_dbg1_l2t2_xbar_vcid; //VCID[5:0] from Xbar to L2t 2 : flopped version | |
200 | ||
201 | output [1:0] dbg0_dbg1_spc0_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 0 | |
202 | output [1:0] dbg0_dbg1_spc0_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 0 | |
203 | output [1:0] dbg0_dbg1_spc2_instr_cmt_grp0;//Instruction Commited in Thread Group 0 for SPC 2 | |
204 | output [1:0] dbg0_dbg1_spc2_instr_cmt_grp1;//Instruction Commited in Thread Group 1 for SPC 2 | |
205 | ||
206 | output dbg0_dbg1_l2b0_sio_ctag_vld; //Ctag valid from L2b 0 to SIO : flopped version | |
207 | output dbg0_dbg1_l2b1_sio_ctag_vld; //Ctag valid from L2b 1 to SIO : flopped version | |
208 | output dbg0_dbg1_l2b2_sio_ctag_vld; //Ctag valid from L2b 2 to SIO : flopped version | |
209 | output dbg0_dbg1_l2b3_sio_ctag_vld; //Ctag valid from L2b 3 to SIO : flopped version | |
210 | output dbg0_dbg1_l2b0_sio_ack_type; //Read or Wr ack from L2b 0 to SIO : flopped version | |
211 | output dbg0_dbg1_l2b1_sio_ack_type; //Read or Wr ack from L2b 1 to SIO : flopped version | |
212 | output dbg0_dbg1_l2b2_sio_ack_type; //Read or Wr ack from L2b 2 to SIO : flopped version | |
213 | output dbg0_dbg1_l2b3_sio_ack_type; //Read or Wr ack from L2b 3 to SIO : flopped version | |
214 | output dbg0_dbg1_l2b0_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 0 to SIO : flopped version | |
215 | output dbg0_dbg1_l2b1_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 1 to SIO : flopped version | |
216 | output dbg0_dbg1_l2b2_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 2 to SIO : flopped version | |
217 | output dbg0_dbg1_l2b3_sio_ack_dest; //Read or Wr ack dest (NIU/DMU) from L2b 3 to SIO : flopped version | |
218 | ||
219 | // Scan reassigns | |
220 | assign pce_ov = tcu_pce_ov; | |
221 | assign stop = tcu_clk_stop; | |
222 | assign siclk = tcu_aclk; | |
223 | assign soclk = tcu_bclk; | |
224 | assign se = tcu_scan_en; | |
225 | ||
226 | wire [331:0] red_rtc_rep_bus_r,red_rtc_rep_bus_rewired; | |
227 | wire [165:0] rep_bus; | |
228 | ||
229 | // io_cmp_sync_en staging flops to stage sync_enables and to stage signnals | |
230 | // from spc0,2, l2b0,1,2,3 l2t0,2 | |
231 | ||
232 | db0_rtc_dp_msff_macro__stack_50c__width_50 ff_io_sync_en ( | |
233 | .scan_in(ff_io_sync_en_scanin), | |
234 | .scan_out(ff_io_sync_en_scanout), | |
235 | .clk ( l2clk ), | |
236 | .en ( 1'b1 ), | |
237 | .din ( {io_cmp_sync_en,dbg0_io_cmp_sync_en_2, | |
238 | dbg0_io_cmp_sync_en_3,dbg0_io_cmp_sync_en_4,dbg0_io_cmp_sync_en_5, | |
239 | dbg0_io_cmp_sync_en_2,dbg0_io_cmp_sync_en_32,dbg0_io_cmp_sync_en_42, | |
240 | dbg0_io_cmp_sync_en_52,cmp_io2x_sync_en, | |
241 | spc0_dbg0_instr_cmt_grp0[1:0],spc0_dbg0_instr_cmt_grp1[1:0], | |
242 | spc2_dbg0_instr_cmt_grp0[1:0],spc2_dbg0_instr_cmt_grp1[1:0], | |
243 | l2b0_dbg0_sio_ctag_vld,l2b1_dbg0_sio_ctag_vld,l2b2_dbg0_sio_ctag_vld, | |
244 | l2b3_dbg0_sio_ctag_vld,l2b0_dbg0_sio_ack_type,l2b1_dbg0_sio_ack_type, | |
245 | l2b2_dbg0_sio_ack_type,l2b3_dbg0_sio_ack_type,l2b0_dbg0_sio_ack_dest, | |
246 | l2b1_dbg0_sio_ack_dest,l2b2_dbg0_sio_ack_dest,l2b3_dbg0_sio_ack_dest, | |
247 | l2t0_dbg0_xbar_vcid[5:0],l2t2_dbg0_xbar_vcid[5:0], | |
248 | l2t0_dbg0_sii_iq_dequeue,l2t2_dbg0_sii_iq_dequeue,l2t0_dbg0_sii_wib_dequeue, | |
249 | l2t2_dbg0_sii_wib_dequeue,l2t0_dbg0_err_event,l2t2_dbg0_err_event, | |
250 | l2t0_dbg0_pa_match,l2t2_dbg0_pa_match} | |
251 | ), | |
252 | ||
253 | .dout ( {dbg0_io_cmp_sync_en_2,dbg0_io_cmp_sync_en_3, | |
254 | dbg0_io_cmp_sync_en_4,dbg0_io_cmp_sync_en_5,dbg0_io_cmp_sync_en_6, | |
255 | dbg0_io_cmp_sync_en_32,dbg0_io_cmp_sync_en_42,dbg0_io_cmp_sync_en_52, | |
256 | dbg0_io_cmp_sync_en_62,cmp_io2x_sync_en_2, | |
257 | dbg0_dbg1_spc0_instr_cmt_grp0[1:0],dbg0_dbg1_spc0_instr_cmt_grp1[1:0], | |
258 | dbg0_dbg1_spc2_instr_cmt_grp0[1:0],dbg0_dbg1_spc2_instr_cmt_grp1[1:0], | |
259 | dbg0_dbg1_l2b0_sio_ctag_vld,dbg0_dbg1_l2b1_sio_ctag_vld, | |
260 | dbg0_dbg1_l2b2_sio_ctag_vld,dbg0_dbg1_l2b3_sio_ctag_vld, | |
261 | dbg0_dbg1_l2b0_sio_ack_type,dbg0_dbg1_l2b1_sio_ack_type, | |
262 | dbg0_dbg1_l2b2_sio_ack_type,dbg0_dbg1_l2b3_sio_ack_type, | |
263 | dbg0_dbg1_l2b0_sio_ack_dest,dbg0_dbg1_l2b1_sio_ack_dest, | |
264 | dbg0_dbg1_l2b2_sio_ack_dest,dbg0_dbg1_l2b3_sio_ack_dest, | |
265 | dbg0_dbg1_l2t0_xbar_vcid[5:0],dbg0_dbg1_l2t2_xbar_vcid[5:0], | |
266 | dbg0_dbg1_l2t0_sii_iq_dequeue,dbg0_dbg1_l2t2_sii_iq_dequeue, | |
267 | dbg0_dbg1_l2t0_sii_wib_dequeue,dbg0_dbg1_l2t2_sii_wib_dequeue, | |
268 | dbg0_dbg1_l2t0_err_event,dbg0_dbg1_l2t2_err_event, | |
269 | dbg0_dbg1_l2t0_pa_match,dbg0_dbg1_l2t2_pa_match} ), | |
270 | .se(se), | |
271 | .siclk(siclk), | |
272 | .soclk(soclk), | |
273 | .pce_ov(pce_ov), | |
274 | .stop(stop) | |
275 | ); | |
276 | ||
277 | // OR piped versions of sync enables to generate mux selects | |
278 | ||
279 | db0_rtc_dp_or_macro__stack_1l__width_1 or_sync_3_4 | |
280 | ( | |
281 | .din0 (dbg0_io_cmp_sync_en_3), | |
282 | .din1 (dbg0_io_cmp_sync_en_4), | |
283 | .dout (dbg0_io_cmp_sync_en_3or4) | |
284 | ); | |
285 | ||
286 | db0_rtc_dp_or_macro__stack_1l__width_1 or_sync_32_42 | |
287 | ( | |
288 | .din0 (dbg0_io_cmp_sync_en_32), | |
289 | .din1 (dbg0_io_cmp_sync_en_42), | |
290 | .dout (dbg0_io_cmp_sync_en_32or42) | |
291 | ); | |
292 | ||
293 | db0_rtc_dp_or_macro__stack_1l__width_1 or_sync_5_6 | |
294 | ( | |
295 | .din0 (dbg0_io_cmp_sync_en_5), | |
296 | .din1 (dbg0_io_cmp_sync_en_6), | |
297 | .dout (dbg0_io_cmp_sync_en_5or6) | |
298 | ); | |
299 | ||
300 | db0_rtc_dp_or_macro__stack_1l__width_1 or_sync_52_62 | |
301 | ( | |
302 | .din0 (dbg0_io_cmp_sync_en_52), | |
303 | .din1 (dbg0_io_cmp_sync_en_62), | |
304 | .dout (dbg0_io_cmp_sync_en_52or62) | |
305 | ); | |
306 | ||
307 | // flop red_rtc_rep_bus bits [165:0] | |
308 | // flop the data such that the DMU data goes out over 2 back to back 700 mhz clock edges | |
309 | // on bits 82:0 , and NIU data on bits 165:83 | |
310 | ||
311 | assign red_rtc_rep_bus_rewired = { red_rtc_rep_bus[248:166],red_rtc_rep_bus[82:0], // NIU 2nd,DMU 2nd | |
312 | red_rtc_rep_bus[331:249],red_rtc_rep_bus[165:83]} ; // NIU 1st, DMU 1st | |
313 | ||
314 | ||
315 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_red_rtc_rep_bus_slice0 ( | |
316 | .scan_in(ff_red_rtc_rep_bus_slice0_scanin), | |
317 | .scan_out(ff_red_rtc_rep_bus_slice0_scanout), | |
318 | .clk ( l2clk ), | |
319 | .en ( dbg0_io_cmp_sync_en_2 ), | |
320 | .din ( red_rtc_rep_bus_rewired[71:0]), | |
321 | .dout ( red_rtc_rep_bus_r[71:0]), | |
322 | .se(se), | |
323 | .siclk(siclk), | |
324 | .soclk(soclk), | |
325 | .pce_ov(pce_ov), | |
326 | .stop(stop) | |
327 | ); | |
328 | ||
329 | db0_rtc_dp_msff_macro__stack_12r__width_12 ff_red_rtc_rep_bus_slice1 ( | |
330 | .scan_in(ff_red_rtc_rep_bus_slice1_scanin), | |
331 | .scan_out(ff_red_rtc_rep_bus_slice1_scanout), | |
332 | .clk ( l2clk ), | |
333 | .en ( dbg0_io_cmp_sync_en_2 ), | |
334 | .din ( red_rtc_rep_bus_rewired[83:72]), | |
335 | .dout ( red_rtc_rep_bus_r[83:72]), | |
336 | .se(se), | |
337 | .siclk(siclk), | |
338 | .soclk(soclk), | |
339 | .pce_ov(pce_ov), | |
340 | .stop(stop) | |
341 | ); | |
342 | ||
343 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_red_rtc_rep_bus_slice2 ( | |
344 | .scan_in(ff_red_rtc_rep_bus_slice2_scanin), | |
345 | .scan_out(ff_red_rtc_rep_bus_slice2_scanout), | |
346 | .clk ( l2clk ), | |
347 | .en ( dbg0_io_cmp_sync_en_2 ), | |
348 | .din ( red_rtc_rep_bus_rewired[155:84]), | |
349 | .dout ( red_rtc_rep_bus_r[155:84]), | |
350 | .se(se), | |
351 | .siclk(siclk), | |
352 | .soclk(soclk), | |
353 | .pce_ov(pce_ov), | |
354 | .stop(stop) | |
355 | ); | |
356 | ||
357 | db0_rtc_dp_msff_macro__stack_10r__width_10 ff_red_rtc_rep_bus_slice3 ( | |
358 | .scan_in(ff_red_rtc_rep_bus_slice3_scanin), | |
359 | .scan_out(ff_red_rtc_rep_bus_slice3_scanout), | |
360 | .clk ( l2clk ), | |
361 | .en ( dbg0_io_cmp_sync_en_2 ), | |
362 | .din ( red_rtc_rep_bus_rewired[165:156]), | |
363 | .dout ( red_rtc_rep_bus_r[165:156]), | |
364 | .se(se), | |
365 | .siclk(siclk), | |
366 | .soclk(soclk), | |
367 | .pce_ov(pce_ov), | |
368 | .stop(stop) | |
369 | ); | |
370 | ||
371 | // flop red_rtc_rep_bus bits [311:166] | |
372 | ||
373 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_red_rtc_rep_bus_slice4 ( | |
374 | .scan_in(ff_red_rtc_rep_bus_slice4_scanin), | |
375 | .scan_out(ff_red_rtc_rep_bus_slice4_scanout), | |
376 | .clk ( l2clk ), | |
377 | .en ( dbg0_io_cmp_sync_en_2 ), | |
378 | .din ( red_rtc_rep_bus_rewired[237:166]), | |
379 | .dout ( red_rtc_rep_bus_r[237:166]), | |
380 | .se(se), | |
381 | .siclk(siclk), | |
382 | .soclk(soclk), | |
383 | .pce_ov(pce_ov), | |
384 | .stop(stop) | |
385 | ); | |
386 | ||
387 | db0_rtc_dp_msff_macro__stack_12r__width_12 ff_red_rtc_rep_bus_slice5 ( | |
388 | .scan_in(ff_red_rtc_rep_bus_slice5_scanin), | |
389 | .scan_out(ff_red_rtc_rep_bus_slice5_scanout), | |
390 | .clk ( l2clk ), | |
391 | .en ( dbg0_io_cmp_sync_en_2 ), | |
392 | .din ( red_rtc_rep_bus_rewired[249:238]), | |
393 | .dout ( red_rtc_rep_bus_r[249:238]), | |
394 | .se(se), | |
395 | .siclk(siclk), | |
396 | .soclk(soclk), | |
397 | .pce_ov(pce_ov), | |
398 | .stop(stop) | |
399 | ); | |
400 | ||
401 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_red_rtc_rep_bus_slice6 ( | |
402 | .scan_in(ff_red_rtc_rep_bus_slice6_scanin), | |
403 | .scan_out(ff_red_rtc_rep_bus_slice6_scanout), | |
404 | .clk ( l2clk ), | |
405 | .en ( dbg0_io_cmp_sync_en_2 ), | |
406 | .din ( red_rtc_rep_bus_rewired[321:250]), | |
407 | .dout ( red_rtc_rep_bus_r[321:250]), | |
408 | .se(se), | |
409 | .siclk(siclk), | |
410 | .soclk(soclk), | |
411 | .pce_ov(pce_ov), | |
412 | .stop(stop) | |
413 | ); | |
414 | ||
415 | db0_rtc_dp_msff_macro__stack_10r__width_10 ff_red_rtc_rep_bus_slice7 ( | |
416 | .scan_in(ff_red_rtc_rep_bus_slice7_scanin), | |
417 | .scan_out(ff_red_rtc_rep_bus_slice7_scanout), | |
418 | .clk ( l2clk ), | |
419 | .en ( dbg0_io_cmp_sync_en_2 ), | |
420 | .din ( red_rtc_rep_bus_rewired[331:322]), | |
421 | .dout ( red_rtc_rep_bus_r[331:322]), | |
422 | .se(se), | |
423 | .siclk(siclk), | |
424 | .soclk(soclk), | |
425 | .pce_ov(pce_ov), | |
426 | .stop(stop) | |
427 | ); | |
428 | ||
429 | // Mux between red_rtc_rep_bus_r[311:166] and red_rtc_rep_bus_r[165:0] | |
430 | ||
431 | db0_rtc_dp_mux_macro__mux_aonpe__stack_72c__width_72 mux_1 | |
432 | ( | |
433 | .dout (rep_bus[71:0]), | |
434 | .din0 (red_rtc_rep_bus_r[71:0]), | |
435 | .din1 (red_rtc_rep_bus_r[237:166]), | |
436 | .sel0 (dbg0_io_cmp_sync_en_3or4), | |
437 | .sel1 (dbg0_io_cmp_sync_en_5or6) | |
438 | ) ; | |
439 | ||
440 | db0_rtc_dp_mux_macro__mux_aonpe__stack_12r__width_12 mux_2 | |
441 | ( | |
442 | .dout (rep_bus[83:72]), | |
443 | .din0 (red_rtc_rep_bus_r[83:72]), | |
444 | .din1 (red_rtc_rep_bus_r[249:238]), | |
445 | .sel0 (dbg0_io_cmp_sync_en_3or4), | |
446 | .sel1 (dbg0_io_cmp_sync_en_5or6) | |
447 | ) ; | |
448 | ||
449 | db0_rtc_dp_mux_macro__mux_aonpe__stack_72c__width_72 mux_3 | |
450 | ( | |
451 | .dout (rep_bus[155:84]), | |
452 | .din0 (red_rtc_rep_bus_r[155:84]), | |
453 | .din1 (red_rtc_rep_bus_r[321:250]), | |
454 | .sel0 (dbg0_io_cmp_sync_en_32or42), | |
455 | .sel1 (dbg0_io_cmp_sync_en_52or62) | |
456 | ) ; | |
457 | ||
458 | db0_rtc_dp_mux_macro__mux_aonpe__stack_10r__width_10 mux_4 | |
459 | ( | |
460 | .dout (rep_bus[165:156]), | |
461 | .din0 (red_rtc_rep_bus_r[165:156]), | |
462 | .din1 (red_rtc_rep_bus_r[331:322]), | |
463 | .sel0 (dbg0_io_cmp_sync_en_32or42), | |
464 | .sel1 (dbg0_io_cmp_sync_en_52or62) | |
465 | ) ; | |
466 | ||
467 | // FLop rep_bus before sending out of dbg0, enabled by cmp_io2x_sync_en_2 | |
468 | ||
469 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_rep_bus_slice0 ( | |
470 | .scan_in(ff_rep_bus_slice0_scanin), | |
471 | .scan_out(ff_rep_bus_slice0_scanout), | |
472 | .clk ( l2clk ), | |
473 | .en ( cmp_io2x_sync_en_2 ), | |
474 | .din ( rep_bus[71:0]), | |
475 | .dout ( dbg0_dbg1_debug_data[71:0]), | |
476 | .se(se), | |
477 | .siclk(siclk), | |
478 | .soclk(soclk), | |
479 | .pce_ov(pce_ov), | |
480 | .stop(stop) | |
481 | ); | |
482 | ||
483 | db0_rtc_dp_msff_macro__stack_12r__width_12 ff_rep_bus_slice1 ( | |
484 | .scan_in(ff_rep_bus_slice1_scanin), | |
485 | .scan_out(ff_rep_bus_slice1_scanout), | |
486 | .clk ( l2clk ), | |
487 | .en ( cmp_io2x_sync_en_2 ), | |
488 | .din ( rep_bus[83:72]), | |
489 | .dout ( dbg0_dbg1_debug_data[83:72]), | |
490 | .se(se), | |
491 | .siclk(siclk), | |
492 | .soclk(soclk), | |
493 | .pce_ov(pce_ov), | |
494 | .stop(stop) | |
495 | ); | |
496 | ||
497 | db0_rtc_dp_msff_macro__stack_72c__width_72 ff_rep_bus_slice2 ( | |
498 | .scan_in(ff_rep_bus_slice2_scanin), | |
499 | .scan_out(ff_rep_bus_slice2_scanout), | |
500 | .clk ( l2clk ), | |
501 | .en ( cmp_io2x_sync_en_2 ), | |
502 | .din ( rep_bus[155:84]), | |
503 | .dout ( dbg0_dbg1_debug_data[155:84]), | |
504 | .se(se), | |
505 | .siclk(siclk), | |
506 | .soclk(soclk), | |
507 | .pce_ov(pce_ov), | |
508 | .stop(stop) | |
509 | ); | |
510 | ||
511 | db0_rtc_dp_msff_macro__stack_10r__width_10 ff_rep_bus_slice3 ( | |
512 | .scan_in(ff_rep_bus_slice3_scanin), | |
513 | .scan_out(ff_rep_bus_slice3_scanout), | |
514 | .clk ( l2clk ), | |
515 | .en ( cmp_io2x_sync_en_2 ), | |
516 | .din ( rep_bus[165:156]), | |
517 | .dout ( dbg0_dbg1_debug_data[165:156]), | |
518 | .se(se), | |
519 | .siclk(siclk), | |
520 | .soclk(soclk), | |
521 | .pce_ov(pce_ov), | |
522 | .stop(stop) | |
523 | ); | |
524 | ||
525 | ||
526 | // fixscan start: | |
527 | assign ff_io_sync_en_scanin = scan_in ; | |
528 | assign ff_red_rtc_rep_bus_slice0_scanin = ff_io_sync_en_scanout ; | |
529 | assign ff_red_rtc_rep_bus_slice1_scanin = ff_red_rtc_rep_bus_slice0_scanout; | |
530 | assign ff_red_rtc_rep_bus_slice2_scanin = ff_red_rtc_rep_bus_slice1_scanout; | |
531 | assign ff_red_rtc_rep_bus_slice3_scanin = ff_red_rtc_rep_bus_slice2_scanout; | |
532 | assign ff_red_rtc_rep_bus_slice4_scanin = ff_red_rtc_rep_bus_slice3_scanout; | |
533 | assign ff_red_rtc_rep_bus_slice5_scanin = ff_red_rtc_rep_bus_slice4_scanout; | |
534 | assign ff_red_rtc_rep_bus_slice6_scanin = ff_red_rtc_rep_bus_slice5_scanout; | |
535 | assign ff_red_rtc_rep_bus_slice7_scanin = ff_red_rtc_rep_bus_slice6_scanout; | |
536 | assign ff_rep_bus_slice0_scanin = ff_red_rtc_rep_bus_slice7_scanout; | |
537 | assign ff_rep_bus_slice1_scanin = ff_rep_bus_slice0_scanout; | |
538 | assign ff_rep_bus_slice2_scanin = ff_rep_bus_slice1_scanout; | |
539 | assign ff_rep_bus_slice3_scanin = ff_rep_bus_slice2_scanout; | |
540 | assign scan_out = ff_rep_bus_slice3_scanout; | |
541 | // fixscan end: | |
542 | endmodule | |
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | // any PARAMS parms go into naming of macro | |
550 | ||
551 | module db0_rtc_dp_msff_macro__stack_50c__width_50 ( | |
552 | din, | |
553 | clk, | |
554 | en, | |
555 | se, | |
556 | scan_in, | |
557 | siclk, | |
558 | soclk, | |
559 | pce_ov, | |
560 | stop, | |
561 | dout, | |
562 | scan_out); | |
563 | wire l1clk; | |
564 | wire siclk_out; | |
565 | wire soclk_out; | |
566 | wire [48:0] so; | |
567 | ||
568 | input [49:0] din; | |
569 | ||
570 | ||
571 | input clk; | |
572 | input en; | |
573 | input se; | |
574 | input scan_in; | |
575 | input siclk; | |
576 | input soclk; | |
577 | input pce_ov; | |
578 | input stop; | |
579 | ||
580 | ||
581 | ||
582 | output [49:0] dout; | |
583 | ||
584 | ||
585 | output scan_out; | |
586 | ||
587 | ||
588 | ||
589 | ||
590 | cl_dp1_l1hdr_8x c0_0 ( | |
591 | .l2clk(clk), | |
592 | .pce(en), | |
593 | .aclk(siclk), | |
594 | .bclk(soclk), | |
595 | .l1clk(l1clk), | |
596 | .se(se), | |
597 | .pce_ov(pce_ov), | |
598 | .stop(stop), | |
599 | .siclk_out(siclk_out), | |
600 | .soclk_out(soclk_out) | |
601 | ); | |
602 | dff #(50) d0_0 ( | |
603 | .l1clk(l1clk), | |
604 | .siclk(siclk_out), | |
605 | .soclk(soclk_out), | |
606 | .d(din[49:0]), | |
607 | .si({scan_in,so[48:0]}), | |
608 | .so({so[48:0],scan_out}), | |
609 | .q(dout[49:0]) | |
610 | ); | |
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | endmodule | |
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | // | |
642 | // or macro for ports = 2,3 | |
643 | // | |
644 | // | |
645 | ||
646 | ||
647 | ||
648 | ||
649 | ||
650 | module db0_rtc_dp_or_macro__stack_1l__width_1 ( | |
651 | din0, | |
652 | din1, | |
653 | dout); | |
654 | input [0:0] din0; | |
655 | input [0:0] din1; | |
656 | output [0:0] dout; | |
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | or2 #(1) d0_0 ( | |
664 | .in0(din0[0:0]), | |
665 | .in1(din1[0:0]), | |
666 | .out(dout[0:0]) | |
667 | ); | |
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | endmodule | |
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | // any PARAMS parms go into naming of macro | |
688 | ||
689 | module db0_rtc_dp_msff_macro__stack_72c__width_72 ( | |
690 | din, | |
691 | clk, | |
692 | en, | |
693 | se, | |
694 | scan_in, | |
695 | siclk, | |
696 | soclk, | |
697 | pce_ov, | |
698 | stop, | |
699 | dout, | |
700 | scan_out); | |
701 | wire l1clk; | |
702 | wire siclk_out; | |
703 | wire soclk_out; | |
704 | wire [70:0] so; | |
705 | ||
706 | input [71:0] din; | |
707 | ||
708 | ||
709 | input clk; | |
710 | input en; | |
711 | input se; | |
712 | input scan_in; | |
713 | input siclk; | |
714 | input soclk; | |
715 | input pce_ov; | |
716 | input stop; | |
717 | ||
718 | ||
719 | ||
720 | output [71:0] dout; | |
721 | ||
722 | ||
723 | output scan_out; | |
724 | ||
725 | ||
726 | ||
727 | ||
728 | cl_dp1_l1hdr_8x c0_0 ( | |
729 | .l2clk(clk), | |
730 | .pce(en), | |
731 | .aclk(siclk), | |
732 | .bclk(soclk), | |
733 | .l1clk(l1clk), | |
734 | .se(se), | |
735 | .pce_ov(pce_ov), | |
736 | .stop(stop), | |
737 | .siclk_out(siclk_out), | |
738 | .soclk_out(soclk_out) | |
739 | ); | |
740 | dff #(72) d0_0 ( | |
741 | .l1clk(l1clk), | |
742 | .siclk(siclk_out), | |
743 | .soclk(soclk_out), | |
744 | .d(din[71:0]), | |
745 | .si({scan_in,so[70:0]}), | |
746 | .so({so[70:0],scan_out}), | |
747 | .q(dout[71:0]) | |
748 | ); | |
749 | ||
750 | ||
751 | ||
752 | ||
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | endmodule | |
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | ||
782 | ||
783 | // any PARAMS parms go into naming of macro | |
784 | ||
785 | module db0_rtc_dp_msff_macro__stack_12r__width_12 ( | |
786 | din, | |
787 | clk, | |
788 | en, | |
789 | se, | |
790 | scan_in, | |
791 | siclk, | |
792 | soclk, | |
793 | pce_ov, | |
794 | stop, | |
795 | dout, | |
796 | scan_out); | |
797 | wire l1clk; | |
798 | wire siclk_out; | |
799 | wire soclk_out; | |
800 | wire [10:0] so; | |
801 | ||
802 | input [11:0] din; | |
803 | ||
804 | ||
805 | input clk; | |
806 | input en; | |
807 | input se; | |
808 | input scan_in; | |
809 | input siclk; | |
810 | input soclk; | |
811 | input pce_ov; | |
812 | input stop; | |
813 | ||
814 | ||
815 | ||
816 | output [11:0] dout; | |
817 | ||
818 | ||
819 | output scan_out; | |
820 | ||
821 | ||
822 | ||
823 | ||
824 | cl_dp1_l1hdr_8x c0_0 ( | |
825 | .l2clk(clk), | |
826 | .pce(en), | |
827 | .aclk(siclk), | |
828 | .bclk(soclk), | |
829 | .l1clk(l1clk), | |
830 | .se(se), | |
831 | .pce_ov(pce_ov), | |
832 | .stop(stop), | |
833 | .siclk_out(siclk_out), | |
834 | .soclk_out(soclk_out) | |
835 | ); | |
836 | dff #(12) d0_0 ( | |
837 | .l1clk(l1clk), | |
838 | .siclk(siclk_out), | |
839 | .soclk(soclk_out), | |
840 | .d(din[11:0]), | |
841 | .si({scan_in,so[10:0]}), | |
842 | .so({so[10:0],scan_out}), | |
843 | .q(dout[11:0]) | |
844 | ); | |
845 | ||
846 | ||
847 | ||
848 | ||
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | ||
862 | ||
863 | ||
864 | ||
865 | endmodule | |
866 | ||
867 | ||
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | ||
877 | ||
878 | ||
879 | // any PARAMS parms go into naming of macro | |
880 | ||
881 | module db0_rtc_dp_msff_macro__stack_10r__width_10 ( | |
882 | din, | |
883 | clk, | |
884 | en, | |
885 | se, | |
886 | scan_in, | |
887 | siclk, | |
888 | soclk, | |
889 | pce_ov, | |
890 | stop, | |
891 | dout, | |
892 | scan_out); | |
893 | wire l1clk; | |
894 | wire siclk_out; | |
895 | wire soclk_out; | |
896 | wire [8:0] so; | |
897 | ||
898 | input [9:0] din; | |
899 | ||
900 | ||
901 | input clk; | |
902 | input en; | |
903 | input se; | |
904 | input scan_in; | |
905 | input siclk; | |
906 | input soclk; | |
907 | input pce_ov; | |
908 | input stop; | |
909 | ||
910 | ||
911 | ||
912 | output [9:0] dout; | |
913 | ||
914 | ||
915 | output scan_out; | |
916 | ||
917 | ||
918 | ||
919 | ||
920 | cl_dp1_l1hdr_8x c0_0 ( | |
921 | .l2clk(clk), | |
922 | .pce(en), | |
923 | .aclk(siclk), | |
924 | .bclk(soclk), | |
925 | .l1clk(l1clk), | |
926 | .se(se), | |
927 | .pce_ov(pce_ov), | |
928 | .stop(stop), | |
929 | .siclk_out(siclk_out), | |
930 | .soclk_out(soclk_out) | |
931 | ); | |
932 | dff #(10) d0_0 ( | |
933 | .l1clk(l1clk), | |
934 | .siclk(siclk_out), | |
935 | .soclk(soclk_out), | |
936 | .d(din[9:0]), | |
937 | .si({scan_in,so[8:0]}), | |
938 | .so({so[8:0],scan_out}), | |
939 | .q(dout[9:0]) | |
940 | ); | |
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | endmodule | |
962 | ||
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
972 | // also for pass-gate with decoder | |
973 | ||
974 | ||
975 | ||
976 | ||
977 | ||
978 | // any PARAMS parms go into naming of macro | |
979 | ||
980 | module db0_rtc_dp_mux_macro__mux_aonpe__stack_72c__width_72 ( | |
981 | din0, | |
982 | sel0, | |
983 | din1, | |
984 | sel1, | |
985 | dout); | |
986 | wire buffout0; | |
987 | wire buffout1; | |
988 | ||
989 | input [71:0] din0; | |
990 | input sel0; | |
991 | input [71:0] din1; | |
992 | input sel1; | |
993 | output [71:0] dout; | |
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | cl_dp1_muxbuff2_8x c0_0 ( | |
1000 | .in0(sel0), | |
1001 | .in1(sel1), | |
1002 | .out0(buffout0), | |
1003 | .out1(buffout1) | |
1004 | ); | |
1005 | mux2s #(72) d0_0 ( | |
1006 | .sel0(buffout0), | |
1007 | .sel1(buffout1), | |
1008 | .in0(din0[71:0]), | |
1009 | .in1(din1[71:0]), | |
1010 | .dout(dout[71:0]) | |
1011 | ); | |
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | endmodule | |
1026 | ||
1027 | ||
1028 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1029 | // also for pass-gate with decoder | |
1030 | ||
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | // any PARAMS parms go into naming of macro | |
1036 | ||
1037 | module db0_rtc_dp_mux_macro__mux_aonpe__stack_12r__width_12 ( | |
1038 | din0, | |
1039 | sel0, | |
1040 | din1, | |
1041 | sel1, | |
1042 | dout); | |
1043 | wire buffout0; | |
1044 | wire buffout1; | |
1045 | ||
1046 | input [11:0] din0; | |
1047 | input sel0; | |
1048 | input [11:0] din1; | |
1049 | input sel1; | |
1050 | output [11:0] dout; | |
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | cl_dp1_muxbuff2_8x c0_0 ( | |
1057 | .in0(sel0), | |
1058 | .in1(sel1), | |
1059 | .out0(buffout0), | |
1060 | .out1(buffout1) | |
1061 | ); | |
1062 | mux2s #(12) d0_0 ( | |
1063 | .sel0(buffout0), | |
1064 | .sel1(buffout1), | |
1065 | .in0(din0[11:0]), | |
1066 | .in1(din1[11:0]), | |
1067 | .dout(dout[11:0]) | |
1068 | ); | |
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | endmodule | |
1083 | ||
1084 | ||
1085 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1086 | // also for pass-gate with decoder | |
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | // any PARAMS parms go into naming of macro | |
1093 | ||
1094 | module db0_rtc_dp_mux_macro__mux_aonpe__stack_10r__width_10 ( | |
1095 | din0, | |
1096 | sel0, | |
1097 | din1, | |
1098 | sel1, | |
1099 | dout); | |
1100 | wire buffout0; | |
1101 | wire buffout1; | |
1102 | ||
1103 | input [9:0] din0; | |
1104 | input sel0; | |
1105 | input [9:0] din1; | |
1106 | input sel1; | |
1107 | output [9:0] dout; | |
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | cl_dp1_muxbuff2_8x c0_0 ( | |
1114 | .in0(sel0), | |
1115 | .in1(sel1), | |
1116 | .out0(buffout0), | |
1117 | .out1(buffout1) | |
1118 | ); | |
1119 | mux2s #(10) d0_0 ( | |
1120 | .sel0(buffout0), | |
1121 | .sel1(buffout1), | |
1122 | .in0(din0[9:0]), | |
1123 | .in1(din1[9:0]), | |
1124 | .dout(dout[9:0]) | |
1125 | ); | |
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | endmodule | |
1140 |