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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu (
36 tcu_aclk, // input () <= ()
37 tcu_bclk, // input () <= ()
38 tcu_pce_ov, // input () <= ()
39 tcu_dmu_io_clk_stop, // input () <= ()
40 tcu_div_bypass, // input () <= ()
41 tcu_test_protect, // input () <= ()
42 ccu_io_out, // input (clstr) <= ()
43 cluster_arst_l, // input (clstr) <= ()
44 ccu_serdes_dtm, // input (clstr) <= ()
45 gclk, // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
46 ncu_dmu_data, // input (dmu_dsn) <= ()
47 ncu_dmu_mmu_addr_vld, // input (dmu_dsn) <= ()
48 ncu_dmu_mondo_ack, // input (dmu_dsn) <= ()
49 ncu_dmu_mondo_id, // input (dmu_dsn) <= ()
50 ncu_dmu_mondo_nack, // input (dmu_dsn) <= ()
51 ncu_dmu_pio_data, // input (dmu_dsn) <= ()
52 ncu_dmu_pio_hdr_vld, // input (dmu_dsn) <= ()
53 ncu_dmu_stall, // input (dmu_dsn) <= ()
54 ncu_dmu_vld, // input (dmu_dsn) <= ()
55 ncu_dmu_mondo_id_par, // input (dmu_dsn) <= () n2 RAS
56 ncu_dmu_d_pei, // input (dmu_dsn) <= () n2 RAS
57 ncu_dmu_siicr_pei, // input (dmu_dsn) <= () n2 RAS
58 ncu_dmu_ctag_uei, // input (dmu_dsn) <= () n2 RAS
59 ncu_dmu_ctag_cei, // input (dmu_dsn) <= () n2 RAS
60 ncu_dmu_ncucr_pei, // input (dmu_dsn) <= () n2 RAS
61 ncu_dmu_iei, // input (dmu_dsn) <= () n2 RAS
62
63 p2d_ce_int, // input (dmu_ilu) <= ()
64 p2d_csr_ack, // input (dmu_ilu) <= ()
65 p2d_csr_rcd, // input (dmu_ilu) <= ()
66 p2d_csr_req, // input (dmu_ilu) <= ()
67 p2d_cto_req, // input (dmu_ilu) <= ()
68 p2d_cto_tag, // input (dmu_ilu) <= ()
69 p2d_drain, // input (dmu_ilu) <= ()
70 p2d_ecd_rptr, // input (dmu_ilu) <= ()
71 p2d_ech_rptr, // input (dmu_ilu) <= ()
72 p2d_erd_rptr, // input (dmu_ilu) <= ()
73 p2d_erh_rptr, // input (dmu_ilu) <= ()
74 p2d_ibc_ack, // input (dmu_ilu) <= ()
75 p2d_idb_data, // input (dmu_ilu) <= ()
76 p2d_idb_dpar, // input (dmu_ilu) <= ()
77 p2d_ihb_data, // input (dmu_ilu) <= ()
78 p2d_ihb_dpar, // input (dmu_ilu) <= ()
79 d2p_ihb_rd, // output (dmu_ilu) => ()
80 d2p_idb_rd, // output (dmu_tmu) => ()
81 p2d_ihb_wptr, // input (dmu_ilu) <= ()
82 p2d_mps, // input (dmu_ilu) <= ()
83 p2d_oe_int, // input (dmu_ilu) <= ()
84 p2d_spare, // input (dmu_ilu) <= ()
85 p2d_ue_int, // input (dmu_ilu) <= ()
86 p2d_npwr_stall_en , // N2+ Bug 106560
87 rst_por_, // input (dmu_dmc,dmu_ilu) <= ()
88 rst_dmu_async_por_, // input (dmu_ilu) <= ()
89 rst_wmr_, // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
90 tcu_scan_en, // input () <= ()
91 scan_in, // input () <= ()
92 tcu_se_scancollar_in, // input () <= ()
93 tcu_se_scancollar_out, // input () <= ()
94 sii_dmu_wrack_tag, // input (dmu_dsn) <= ()
95 sii_dmu_wrack_par, // input (dmu_dsn) <= () n2 RAS
96 sii_dmu_wrack_vld, // input (dmu_dsn) <= ()
97 sio_dmu_data, // input (dmu_dsn) <= ()
98 sio_dmu_hdr_vld, // input (dmu_dsn) <= ()
99 sio_dmu_parity, // input (dmu_dsn) <= ()
100 tcu_array_bypass, // input () <= ()
101 tcu_array_wr_inhibit, // input () <= ()
102 tcu_mbist_bisi_en, // input () <= ()
103 tcu_mbist_user_mode, // input () <= ()
104 tcu_dmu_mbist_start, // input () <= ()
105 tcu_dmu_mbist_scan_in, // input () <= ()
106 tcu_atpg_mode, // input () <= ()
107 dmu_tcu_mbist_done, // output () <= ()
108 dmu_tcu_mbist_fail, // output () <= ()
109 dmu_tcu_mbist_scan_out, // output () <= ()
110 d2p_csr_ack, // output (dmu_ilu) => ()
111 d2p_csr_rcd, // output (dmu_ilu) => ()
112 d2p_csr_req, // output (dmu_ilu) => ()
113 d2p_cto_ack, // output (dmu_ilu) => ()
114 d2p_ech_wptr, // output (dmu_ilu) => ()
115 d2p_edb_addr, // output (dmu_ilu) => ()
116 d2p_edb_data, // output (dmu_ilu) => ()
117 d2p_edb_dpar, // output (dmu_ilu) => ()
118 d2p_edb_we, // output (dmu_ilu) => ()
119 d2p_ehb_addr, // output (dmu_ilu) => ()
120 d2p_ehb_data, // output (dmu_ilu) => ()
121 d2p_ehb_dpar, // output (dmu_ilu) => ()
122 d2p_ehb_we, // output (dmu_ilu) => ()
123 d2p_erh_wptr, // output (dmu_ilu) => ()
124 d2p_ibc_nhc, // output (dmu_ilu) => ()
125 d2p_ibc_pdc, // output (dmu_ilu) => ()
126 d2p_ibc_phc, // output (dmu_ilu) => ()
127 d2p_ibc_req, // output (dmu_ilu) => ()
128 d2p_idb_addr, // output (dmu_ilu) => ()
129 d2p_ihb_addr, // output (dmu_ilu) => ()
130 d2p_spare, // output (dmu_ilu) => ()
131 dmu_ncu_data, // output (dmu_dsn) => ()
132 dmu_ncu_stall, // output (dmu_dsn) => ()
133 dmu_ncu_vld, // output (dmu_dsn) => ()
134 dmu_ncu_wrack_tag, // output (dmu_dsn) => ()
135 dmu_ncu_wrack_vld, // output (dmu_dsn) => ()
136 dmu_ncu_wrack_par, // output (dmu_dsn) => () n2 RAS
137 dmu_ncu_d_pe, // output (dmu_dsn) => () n2 RAS
138 dmu_ncu_siicr_pe, // output (dmu_dsn) => () n2 RAS
139 dmu_ncu_ctag_ue, // output (dmu_dsn) => () n2 RAS
140 dmu_ncu_ctag_ce, // output (dmu_dsn) => () n2 RAS
141 dmu_ncu_ncucr_pe, // output (dmu_dsn) => () n2 RAS
142 dmu_ncu_ie, // output (dmu_dsn) => () n2 RAS
143 dmu_sii_be, // output (dmu_dsn) => ()
144 dmu_sii_data, // output (dmu_dsn) => ()
145 dmu_sii_datareq, // output (dmu_dsn) => ()
146 dmu_sii_datareq16, // output (dmu_dsn) => ()
147 dmu_sii_hdr_vld, // output (dmu_dsn) => ()
148 dmu_sii_parity, // output (dmu_dsn) => ()
149 dmu_sii_be_parity, // output (dmu_dsn) => ()
150 dmu_sii_reqbypass, // output (dmu_dsn) => ()
151 dmu_mio_debug_bus_a, // output (dmu_cru) => ()
152 dmu_mio_debug_bus_b, // output (dmu_cru) => ()
153 scan_out, // output () => ()
154 dmu_dbg_err_event, // output () => ()
155 dbg1_dmu_stall, // output () => ()
156 dbg1_dmu_resume, // output () => ()
157 dmu_dbg1_stall_ack, // output () => ()
158// efuse signals
159 efu_dmu_data, // input () => ()
160 efu_dmu_xfer_en, // input () => ()
161 efu_dmu_clr, // input () => ()
162 dmu_efu_data, // output () => ()
163 dmu_efu_xfer_en, // output () => ()
164//SV n2 5-31-05
165 dmu_psr_rate_scale, // output (ilu) => (psr)
166//BP n2 5-24-05 peu pll en, tx lane enable, rx lane enable
167 dmu_psr_pll_en_sds0, // output (ilu) => (peu)
168 dmu_psr_pll_en_sds1, // output (ilu) => (peu)
169 dmu_psr_rx_en_b0_sds0, // output (ilu) => (peu)
170 dmu_psr_rx_en_b1_sds0, // output (ilu) => (peu)
171 dmu_psr_rx_en_b2_sds0, // output (ilu) => (peu)
172 dmu_psr_rx_en_b3_sds0, // output (ilu) => (peu)
173 dmu_psr_rx_en_b0_sds1, // output (ilu) => (peu)
174 dmu_psr_rx_en_b1_sds1, // output (ilu) => (peu)
175 dmu_psr_rx_en_b2_sds1, // output (ilu) => (peu)
176 dmu_psr_rx_en_b3_sds1, // output (ilu) => (peu)
177 dmu_psr_tx_en_b0_sds0, // output (ilu) => (peu)
178 dmu_psr_tx_en_b1_sds0, // output (ilu) => (peu)
179 dmu_psr_tx_en_b2_sds0, // output (ilu) => (peu)
180 dmu_psr_tx_en_b3_sds0, // output (ilu) => (peu)
181 dmu_psr_tx_en_b0_sds1, // output (ilu) => (peu)
182 dmu_psr_tx_en_b1_sds1, // output (ilu) => (peu)
183 dmu_psr_tx_en_b2_sds1, // output (ilu) => (peu)
184 dmu_psr_tx_en_b3_sds1, // output (ilu) => (peu)
185 d2p_req_id // output (cru) => (peu)
186
187 );
188
189input tcu_aclk;
190input tcu_bclk;
191input tcu_pce_ov;
192input tcu_dmu_io_clk_stop;
193input tcu_div_bypass;
194input tcu_test_protect;
195input ccu_io_out;
196input cluster_arst_l;
197input ccu_serdes_dtm;
198input gclk;
199input [31:0] ncu_dmu_data;
200input ncu_dmu_mmu_addr_vld;
201input ncu_dmu_mondo_ack;
202input [5:0] ncu_dmu_mondo_id;
203input ncu_dmu_mondo_nack;
204input [63:0] ncu_dmu_pio_data;
205input ncu_dmu_pio_hdr_vld;
206input ncu_dmu_stall;
207input ncu_dmu_vld;
208input ncu_dmu_mondo_id_par; // input (dmu_dsn) <= () n2 RAS
209input ncu_dmu_d_pei; // input (dmu_dsn) <= () n2 RAS
210input ncu_dmu_siicr_pei; // input (dmu_dsn) <= () n2 RAS
211input ncu_dmu_ctag_uei; // input (dmu_dsn) <= () n2 RAS
212input ncu_dmu_ctag_cei; // input (dmu_dsn) <= () n2 RAS
213input ncu_dmu_ncucr_pei; // input (dmu_dsn) <= () n2 RAS
214input ncu_dmu_iei; // input (dmu_dsn) <= () n2 RAS
215input p2d_ce_int;
216input p2d_csr_ack;
217input [95:0] p2d_csr_rcd;
218input p2d_csr_req;
219input p2d_cto_req;
220input [4:0] p2d_cto_tag;
221input p2d_drain;
222input [7:0] p2d_ecd_rptr;
223input [5:0] p2d_ech_rptr;
224input [7:0] p2d_erd_rptr;
225input [5:0] p2d_erh_rptr;
226input p2d_ibc_ack;
227input [127:0] p2d_idb_data;
228input [3:0] p2d_idb_dpar;
229input [127:0] p2d_ihb_data;
230input [3:0] p2d_ihb_dpar;
231output d2p_ihb_rd; //BP n2 4-1-05these two are for circuit issues to peu rams
232output d2p_idb_rd; //BP n2 4-1-05these two are for circuit issues to peu rams
233input [6:0] p2d_ihb_wptr;
234input [2:0] p2d_mps;
235input p2d_oe_int;
236input [4:0] p2d_spare;
237input p2d_ue_int;
238input p2d_npwr_stall_en ; // N2+ Bug 106560
239input rst_por_;
240input rst_dmu_async_por_; //BP n2 8.05-05 async reset to set SERDES csr for por1
241input rst_wmr_;
242input tcu_scan_en;
243input scan_in;
244input tcu_se_scancollar_in;
245input tcu_se_scancollar_out;
246input [3:0] sii_dmu_wrack_tag;
247input sii_dmu_wrack_par; // input (dmu_dsn) <= () n2 RAS
248input sii_dmu_wrack_vld;
249input [127:0] sio_dmu_data;
250input sio_dmu_hdr_vld;
251input [7:0] sio_dmu_parity;
252input tcu_array_bypass;
253input tcu_array_wr_inhibit;
254input tcu_mbist_bisi_en; // input mbist
255input tcu_mbist_user_mode; // input mbist
256input [1:0] tcu_dmu_mbist_start; // input mbist
257input tcu_dmu_mbist_scan_in; // input mbist
258input tcu_atpg_mode; // input mbist
259output [1:0] dmu_tcu_mbist_done; // output mbist
260output [1:0] dmu_tcu_mbist_fail; // output mbist
261output dmu_tcu_mbist_scan_out; // output mbist
262output d2p_csr_ack;
263output [95:0] d2p_csr_rcd;
264output d2p_csr_req;
265output d2p_cto_ack;
266output [5:0] d2p_ech_wptr;
267output [7:0] d2p_edb_addr;
268output [127:0] d2p_edb_data;
269output [3:0] d2p_edb_dpar;
270output d2p_edb_we;
271output [5:0] d2p_ehb_addr;
272output [127:0] d2p_ehb_data;
273output [3:0] d2p_ehb_dpar;
274output d2p_ehb_we;
275output [5:0] d2p_erh_wptr;
276output [7:0] d2p_ibc_nhc;
277output [11:0] d2p_ibc_pdc;
278output [7:0] d2p_ibc_phc;
279output d2p_ibc_req;
280output [7:0] d2p_idb_addr;
281output [5:0] d2p_ihb_addr;
282output [4:0] d2p_spare;
283output [31:0] dmu_ncu_data;
284output dmu_ncu_stall;
285output dmu_ncu_vld;
286output [3:0] dmu_ncu_wrack_tag;
287output dmu_ncu_wrack_vld;
288output dmu_ncu_wrack_par; // output (dmu_dsn) => () n2 RAS
289output dmu_ncu_d_pe; // output (dmu_dsn) => () n2 RAS
290output dmu_ncu_siicr_pe; // output (dmu_dsn) => () n2 RAS
291output dmu_ncu_ctag_ue; // output (dmu_dsn) => () n2 RAS
292output dmu_ncu_ctag_ce; // output (dmu_dsn) => () n2 RAS
293output dmu_ncu_ncucr_pe; // output (dmu_dsn) => () n2 RAS
294output dmu_ncu_ie; // output (dmu_dsn) => () n2 RAS
295output [15:0] dmu_sii_be;
296output [127:0] dmu_sii_data;
297output dmu_sii_datareq;
298output dmu_sii_datareq16;
299output dmu_sii_hdr_vld;
300output [7:0] dmu_sii_parity;
301output dmu_sii_be_parity;
302output dmu_sii_reqbypass;
303output [7:0] dmu_mio_debug_bus_a;
304output [7:0] dmu_mio_debug_bus_b;
305output scan_out;
306output dmu_dbg_err_event;
307input dbg1_dmu_stall;
308input dbg1_dmu_resume;
309output dmu_dbg1_stall_ack;
310// efuse signals
311input efu_dmu_data; // input () => ()
312input efu_dmu_xfer_en; // input () => ()
313input efu_dmu_clr; // input () => ()
314output dmu_efu_data; // output () => ()
315output dmu_efu_xfer_en; // output () => ()
316//SV n2 5-31-05
317output [1:0] dmu_psr_rate_scale;
318// BP n2 5-24-05 peu pll enable tx-lane enable rx-lane enable
319output dmu_psr_pll_en_sds0;
320output dmu_psr_pll_en_sds1;
321output dmu_psr_rx_en_b0_sds0;
322output dmu_psr_rx_en_b1_sds0;
323output dmu_psr_rx_en_b2_sds0;
324output dmu_psr_rx_en_b3_sds0;
325output dmu_psr_rx_en_b0_sds1;
326output dmu_psr_rx_en_b1_sds1;
327output dmu_psr_rx_en_b2_sds1;
328output dmu_psr_rx_en_b3_sds1;
329output dmu_psr_tx_en_b0_sds0;
330output dmu_psr_tx_en_b1_sds0;
331output dmu_psr_tx_en_b2_sds0;
332output dmu_psr_tx_en_b3_sds0;
333output dmu_psr_tx_en_b0_sds1;
334output dmu_psr_tx_en_b1_sds1;
335output dmu_psr_tx_en_b2_sds1;
336output dmu_psr_tx_en_b3_sds1;
337output [15:0] d2p_req_id; //BP 8-18-05
338
339
340wire l1clk;
341wire por_;
342/*
343wire ncu_dmu_mondo_id_par; // input (dmu_dsn) <= () n2 RAS
344wire ncu_dmu_d_pei; // input (dmu_dsn) <= () n2 RAS
345wire ncu_dmu_siicr_pei; // input (dmu_dsn) <= () n2 RAS
346wire ncu_dmu_ctag_uei; // input (dmu_dsn) <= () n2 RAS
347wire ncu_dmu_ctag_cei; // input (dmu_dsn) <= () n2 RAS
348wire ncu_dmu_ncucr_pei; // input (dmu_dsn) <= () n2 RAS
349wire ncu_dmu_iei; // input (dmu_dsn) <= () n2 RAS
350wire sii_dmu_wrack_par; // input (dmu_dsn) <= () n2 RAS
351wire dmu_ncu_wrack_par; // output (dmu_dsn) => () n2 RAS
352wire dmu_ncu_d_pe; // output (dmu_dsn) => () n2 RAS
353wire dmu_ncu_siicr_pe; // output (dmu_dsn) => () n2 RAS
354wire dmu_ncu_ctag_ue; // output (dmu_dsn) => () n2 RAS
355wire dmu_ncu_ctag_ce; // output (dmu_dsn) => () n2 RAS
356wire dmu_ncu_ncucr_pe; // output (dmu_dsn) => () n2 RAS
357wire dmu_ncu_ie; // output (dmu_dsn) => () n2 RAS
358*/
359wire [36:0] d2j_addr;
360wire [15:0] d2j_bmsk;
361wire [31:0] d2j_csr_ring_in;
362wire [15:0] d2j_ctag;
363wire [127:0] d2j_data;
364//wire [42:13] d2j_tsb_base;
365wire [31:0] j2d_csr_ring_out;
366wire [127:0] j2d_d_data;
367wire [15:0] j2d_di_ctag;
368//wire [19:0] j2d_ext_int_l;
369wire [42:6] j2d_mmu_addr;
370wire [35:0] j2d_p_addr;
371wire [15:0] j2d_p_bmsk;
372wire [127:0] j2d_p_data;
373wire [127:0] k2y_buf_data;
374wire [31:0] k2y_csr_ring_out;
375wire [123:0] k2y_rcd;
376wire [127:0] y2k_buf_data;
377wire [31:0] y2k_csr_ring_in;
378wire [115:0] y2k_rcd;
379wire [3:0] d2j_cmd;
380wire d2j_cmd_vld;
381wire [4:0] d2j_data_par;
382wire d2j_data_vld;
383wire [5:0] cr2ds_dbg_sel_a;
384wire [5:0] cr2ds_dbg_sel_b;
385wire [7:0] ds2cr_dbg_a;
386wire [7:0] ds2cr_dbg_b;
387wire [7:0] dmu_mio_debug_bus_a;
388wire [7:0] dmu_mio_debug_bus_b;
389wire [3:0] d2j_p_wrack_tag;
390wire d2j_p_wrack_vld;
391//wire [4:0] d2j_spare;
392//wire d2j_tsb_enable;
393//wire [3:0] d2j_tsb_size;
394wire j2d_d_data_err;
395wire [3:0] j2d_d_data_par;
396wire j2d_d_data_vld;
397wire [3:0] j2d_d_wrack_tag;
398wire j2d_d_wrack_vld;
399wire [1:0] j2d_di_cmd;
400wire j2d_di_cmd_vld;
401//wire j2d_i2c0_int_l;
402//wire j2d_i2c1_int_l;
403wire j2d_instance_id;
404//wire j2d_jbc_int_l;
405//wire j2d_jid;
406wire j2d_mmu_addr_vld;
407wire [3:0] j2d_p_cmd;
408wire j2d_p_cmd_vld;
409wire [10:0] j2d_p_ctag;
410wire [3:0] j2d_p_data_par;
411wire j2d_p_data_vld;
412//wire [4:0] j2d_spare;
413wire [7:0] k2y_buf_addr;
414wire k2y_buf_addr_vld_monitor;
415wire [3:0] k2y_buf_dpar;
416wire [5:0] k2y_dbg_sel_a;
417wire [5:0] k2y_dbg_sel_b;
418wire [4:0] k2y_dou_dptr;
419wire k2y_dou_err;
420wire k2y_dou_vld;
421wire k2y_rcd_deq;
422wire k2y_rcd_enq;
423wire k2y_rel_enq;
424wire [8:0] k2y_rel_rcd;
425wire [7:0] y2k_buf_addr;
426wire y2k_buf_addr_vld_monitor;
427wire [3:0] y2k_buf_dpar;
428wire [7:0] y2k_dbg_a;
429wire [7:0] y2k_dbg_b;
430wire y2k_int_l;
431wire [2:0] y2k_mps;
432wire y2k_rcd_deq;
433wire y2k_rcd_enq;
434wire y2k_rel_enq;
435wire [8:0] y2k_rel_rcd;
436
437wire mb0_dcache_read_unused;
438wire mb0_dcache_write_unused;
439wire [6:0] mb0_dcache_index_unused;
440wire [1:0] mb0_dcache_way_unused;
441wire mb0_icache_read_unused;
442wire mb0_icache_write_unused;
443wire [7:0] mb0_icache_index_unused;
444wire mb0_icache_word_unused;
445wire [1:0] mb0_icache_way_unused;
446wire [7:0] mb0_write_data_unused;
447wire mb0_done_unused;
448wire mb0_dcache_fail_unused;
449
450
451wire mb0_icache_fail_unused;
452
453wire cb0_dcache_read_unused;
454wire cb0_dcache_write_unused;
455wire [6:0] cb0_dcache_index_unused;
456wire [1:0] cb0_dcache_way_unused;
457wire cb0_icache_read_unused;
458wire cb0_icache_write_unused;
459wire [7:0] cb0_icache_index_unused;
460wire cb0_icache_word_unused;
461wire [1:0] cb0_icache_way_unused;
462wire [7:0] cb0_write_data_unused;
463wire cb0_done_unused;
464wire cb0_dcache_fail_unused;
465wire cb0_icache_fail_unused;
466wire dmu_mb0_scanout,dmu_cb0_scanout;
467assign j2d_instance_id = 1'b0;
468wire dsn_dmc_iei;
469wire ds2cl_stall;
470
471wire dmu_cb0_run;
472wire [5:0] dmu_cb0_addr;
473wire [32:0] dmu_cb0_wdata_key;
474wire dmu_cb0_mmu_ptb_wr_en;
475wire dmu_cb0_mmu_ptb_rd_en;
476wire dmu_cb0_mmu_ptb_lkup_en;
477wire [63:0] mmu_ptb_hit;
478wire dmu_cb0_mmu_vtb_wr_en;
479wire dmu_cb0_mmu_vtb_rd_en;
480wire dmu_cb0_mmu_vtb_lkup_en;
481wire dmu_cb0_hld;
482wire [63:0] mmu_vtb_hit;
483wire [3:0] vtb_dout_4msb;
484wire [32:0] mmu_ptb_read_data;
485wire [29:0] vtb2csr_rd;
486
487wire [63:0] dev_tsb_read_data;
488wire dmu_mb0_run;
489wire [8:0] dmu_mb0_addr;
490wire [7:0] dmu_mb0_wdata;
491wire dmu_mb0_dev_wr_en;
492wire dmu_mb0_dev_rd_en;
493wire dmu_mb0_tsb_wr_en;
494wire dmu_mb0_tsb_rd_en;
495wire dmu_mb0_tdb_wr_en;
496wire dmu_mb0_tdb_rd_en;
497wire [7:0] tdb_dout_8msb;
498wire [51:0] tdb2csr_rd;
499wire [148:0] dmu_diu_read_data;
500wire dmu_mb0_diu_wr_en;
501wire dmu_mb0_diu_rd_en;
502wire [131:0] dmu_dou_pio_read_data;
503wire [131:0] dmu_dou_dma_read_data;
504wire dmu_mb0_dou_pio_data_wr_en;
505wire dmu_mb0_dou_pio_data_rd_en;
506wire dmu_mb0_dou_dma_data_wr_en;
507wire dmu_mb0_dou_dma_data_rd_en;
508wire iol2clk,aclk,bclk,so,pce_ov,wmr_;
509wire efu_dmu_data,efu_dmu_xfer_en, efu_dmu_clr, dmu_efu_data, dmu_efu_xfer_en;
510wire array_wr_inhibit;
511wire il2cl_gr_16 ;
512
513`ifdef IOMMU_SAT
514`else
515clkgen_dmu_io dmu_clkgen(
516//OUTPUTS
517 .l2clk (iol2clk), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
518 .aclk (aclk), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
519 .bclk (bclk), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
520 .scan_out (), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
521 .aclk_wmr (), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
522 .pce_ov (pce_ov), // output (dmu_dmc,dmu_mb0,dmu_cb0) => ()
523 .wmr_protect (), // output () => ()
524 .wmr_ (wmr_), // output () => ()
525 .por_ (por_), // output () => ()
526 .cmp_slow_sync_en (), // output () => ()
527 .slow_cmp_sync_en (), // output () => ()
528 .array_wr_inhibit (array_wr_inhibit), // output () => ()
529//INPUTS
530 .tcu_atpg_mode (tcu_atpg_mode), // input () <= ()
531 .tcu_wr_inhibit (tcu_array_wr_inhibit), // input () <= ()
532 .tcu_clk_stop (tcu_dmu_io_clk_stop), // input () <= ()
533 .tcu_pce_ov (tcu_pce_ov), // input () <= ()
534 .rst_wmr_protect (1'b0), // input () <= ()
535 .rst_wmr_ (rst_wmr_), // input () <= ()
536 .rst_por_ (rst_por_), // input () <= ()
537 .ccu_cmp_slow_sync_en (1'b0), // input () <= ()
538 .ccu_slow_cmp_sync_en (1'b0), // input () <= ()
539 .tcu_div_bypass (tcu_div_bypass), // input () <= ()
540// .tcu_div_bypass (1'b0), // input () <= ()
541 .ccu_div_ph (ccu_io_out), // input () <= ()
542 .cluster_div_en (1'b1), // input () <= ()
543 .gclk (gclk), // input () <= ()
544 .cluster_arst_l (cluster_arst_l), // input () <= ()
545 .clk_ext (1'b0), // input () <= ()
546 .ccu_serdes_dtm (1'b0), // input () <= ()
547 .scan_en (tcu_scan_en), // input () <= ()
548 .scan_in (scan_in), // input () <= ()
549 .tcu_aclk (tcu_aclk), // input () <= ()
550 .tcu_bclk (tcu_bclk) // input () <= ()
551 );
552
553
554// L1 Clock header
555
556
557 cl_a1_l1hdr_8x clkgen_l1 (
558 .l2clk(iol2clk),
559 .pce(1'b1),
560 .l1clk(l1clk),
561 .se(tcu_scan_en),
562 .pce_ov(pce_ov),
563//SV .stop(tcu_soc6io_clk_stop)
564 .stop(1'b0)
565 );
566`endif
567
568
569`ifdef NO_DMC
570`else
571dmu_dmc dmc (
572 .l2clk (iol2clk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
573 .l1clk (l1clk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
574 .j2d_rst_l (wmr_), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
575 .j2d_por_l (por_), // input (dmu_dmc,dmu_ilu) <= ()
576 .scan_in (scan_in), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
577 .tcu_scan_en (tcu_scan_en), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
578 .tcu_array_bypass (tcu_array_bypass), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
579 .tcu_se_scancollar_in (tcu_se_scancollar_in), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
580 .tcu_se_scancollar_out (tcu_se_scancollar_out), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
581 .tcu_array_wr_inhibit (array_wr_inhibit), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
582 .tcu_pce_ov (pce_ov), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
583//SV .tcu_clk_stop (tcu_soc6io_clk_stop), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
584 .tcu_aclk (aclk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
585 .tcu_bclk (bclk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
586 .scan_out (scan_out), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
587 .j2d_spare ({5{1'b0}}), // input (dmu_dmc) <= ()
588 .cr2ds_dbg_sel_a (cr2ds_dbg_sel_a[5:0]), // output () => (dmu_dsn)
589 .cr2ds_dbg_sel_b (cr2ds_dbg_sel_b[5:0]), // output () => (dmu_dsn)
590 .ds2cr_dbg_a (ds2cr_dbg_a[7:0]), // input () <= (dmu_dsn)
591 .ds2cr_dbg_b (ds2cr_dbg_b[7:0]), // input () <= (dmu_dsn)
592 .dmu_mio_debug_bus_a (dmu_mio_debug_bus_a[7:0]), // output (dmu_dmc) => ()
593 .dmu_mio_debug_bus_b (dmu_mio_debug_bus_b[7:0]), // output (dmu_dmc) => ()
594 .y2k_int_l (y2k_int_l), // input (dmu_dmc) <= (dmu_ilu)
595// .j2d_ext_int_l (j2d_ext_int_l), // input (dmu_dmc) <= ()
596// .j2d_i2c0_int_l (j2d_i2c0_int_l), // input (dmu_dmc) <= ()
597// .j2d_i2c1_int_l (j2d_i2c1_int_l), // input (dmu_dmc) <= ()
598// .j2d_jbc_int_l (j2d_jbc_int_l), // input (dmu_dmc) <= ()
599 .j2d_jid (1'b0), // input (dmu_dmc) <= ()
600 .j2d_instance_id (j2d_instance_id), // input (dmu_dmc) <= ()
601 .j2d_csr_ring_out (j2d_csr_ring_out[31:0]), // input (dmu_dmc) <= (dmu_dsn)
602 .d2j_csr_ring_in (d2j_csr_ring_in[31:0]), // output (dmu_dmc) => (dmu_dsn)
603 .k2y_csr_ring_out (k2y_csr_ring_out[31:0]), // output (dmu_dmc) => (dmu_ilu)
604 .y2k_csr_ring_in (y2k_csr_ring_in[31:0]), // input (dmu_dmc) <= (dmu_ilu)
605 .d2j_cmd (d2j_cmd[3:0]), // output (dmu_dmc) => (dmu_dsn)
606 .d2j_addr (d2j_addr[36:0]), // output (dmu_dmc) => (dmu_dsn)
607 .d2j_ctag (d2j_ctag[15:0]), // output (dmu_dmc) => (dmu_dsn)
608 .d2j_cmd_vld (d2j_cmd_vld), // output (dmu_dmc) => (dmu_dsn)
609 .d2j_data (d2j_data[127:0]), // output (dmu_dmc) => (dmu_dsn)
610 .d2j_bmsk (d2j_bmsk[15:0]), // output (dmu_dmc) => (dmu_dsn)
611 .d2j_data_par (d2j_data_par[4:0]), // output (dmu_dmc) => (dmu_dsn)
612 .d2j_data_vld (d2j_data_vld), // output (dmu_dmc) => (dmu_dsn)
613 .d2j_p_wrack_tag (d2j_p_wrack_tag[3:0]), // output (dmu_dmc) => (dmu_dsn)
614 .d2j_p_wrack_vld (d2j_p_wrack_vld), // output (dmu_dmc) => (dmu_dsn)
615 .y2k_rel_rcd (y2k_rel_rcd[8:0]), // input (dmu_dmc) <= (dmu_ilu)
616 .y2k_rel_enq (y2k_rel_enq), // input (dmu_dmc) <= (dmu_ilu)
617 .d2j_spare (), // output (dmu_dmc) => ()
618 .y2k_mps (y2k_mps[2:0]), // input (dmu_dmc) <= (dmu_ilu)
619 .y2k_buf_addr_vld_monitor (y2k_buf_addr_vld_monitor), // input (dmu_dmc) <= (dmu_ilu)
620 .y2k_buf_addr (y2k_buf_addr[7:0]), // input (dmu_dmc) <= (dmu_ilu)
621 .k2y_buf_data (k2y_buf_data[127:0]), // output (dmu_dmc) => (dmu_ilu)
622 .k2y_buf_dpar (k2y_buf_dpar[3:0]), // output (dmu_dmc) => (dmu_ilu)
623 .j2d_d_wrack_tag (j2d_d_wrack_tag[3:0]), // input (dmu_dmc) <= (dmu_dsn)
624 .j2d_d_wrack_vld (j2d_d_wrack_vld), // input (dmu_dmc) <= (dmu_dsn)
625 .j2d_di_cmd (j2d_di_cmd[1:0]), // input (dmu_dmc) <= (dmu_dsn)
626 .j2d_di_ctag (j2d_di_ctag[15:0]), // input (dmu_dmc) <= (dmu_dsn)
627 .j2d_di_cmd_vld (j2d_di_cmd_vld), // input (dmu_dmc) <= (dmu_dsn)
628 .j2d_p_cmd (j2d_p_cmd[3:0]), // input (dmu_dmc) <= (dmu_dsn)
629 .j2d_p_addr (j2d_p_addr[35:0]), // input (dmu_dmc) <= (dmu_dsn)
630 .j2d_p_bmsk (j2d_p_bmsk[15:0]), // input (dmu_dmc) <= (dmu_dsn)
631 .j2d_p_ctag (j2d_p_ctag[10:0]), // input (dmu_dmc) <= (dmu_dsn)
632 .j2d_p_cmd_vld (j2d_p_cmd_vld), // input (dmu_dmc) <= (dmu_dsn)
633 .j2d_d_data (j2d_d_data[127:0]), // input (dmu_dmc) <= (dmu_dsn)
634 .j2d_d_data_par (j2d_d_data_par[3:0]), // input (dmu_dmc) <= (dmu_dsn)
635 .j2d_d_data_err (j2d_d_data_err), // input (dmu_dmc) <= (dmu_dsn)
636 .j2d_d_data_vld (j2d_d_data_vld), // input (dmu_dmc) <= (dmu_dsn)
637 .j2d_p_data (j2d_p_data[127:0]), // input (dmu_dmc) <= (dmu_dsn)
638 .j2d_p_data_par (j2d_p_data_par[3:0]), // input (dmu_dmc) <= (dmu_dsn)
639 .j2d_p_data_vld (j2d_p_data_vld), // input (dmu_dmc) <= (dmu_dsn)
640 .k2y_dou_dptr (k2y_dou_dptr[4:0]), // output (dmu_dmc) => (dmu_ilu)
641 .k2y_dou_err (k2y_dou_err), // output (dmu_dmc) => (dmu_ilu)
642 .k2y_dou_vld (k2y_dou_vld), // output (dmu_dmc) => (dmu_ilu)
643 .j2d_mmu_addr (j2d_mmu_addr[42:6]), // input (dmu_dmc) <= (dmu_dsn)
644 .j2d_mmu_addr_vld (j2d_mmu_addr_vld), // input (dmu_dmc) <= (dmu_dsn)
645// .d2j_tsb_base (d2j_tsb_base[42:13]), // output (dmu_dmc) => ()
646// .d2j_tsb_enable (d2j_tsb_enable), // output (dmu_dmc) => ()
647// .d2j_tsb_size (d2j_tsb_size[3:0]), // output (dmu_dmc) => ()
648 .k2y_buf_addr_vld_monitor (k2y_buf_addr_vld_monitor), // output (dmu_dmc) => (dmu_ilu)
649 .k2y_buf_addr (k2y_buf_addr[7:0]), // output (dmu_dmc) => (dmu_ilu)
650 .y2k_buf_data (y2k_buf_data[127:0]), // input (dmu_dmc) <= (dmu_ilu)
651 .y2k_buf_dpar (y2k_buf_dpar[3:0]), // input (dmu_dmc) <= (dmu_ilu)
652 .k2y_rcd_deq (k2y_rcd_deq), // output (dmu_dmc) => (dmu_ilu)
653 .y2k_rcd (y2k_rcd[115:0]), // input (dmu_dmc) <= (dmu_ilu)
654 .y2k_rcd_enq (y2k_rcd_enq), // input (dmu_dmc) <= (dmu_ilu)
655 .k2y_rcd (k2y_rcd[123:0]), // output (dmu_dmc) => (dmu_ilu)
656 .k2y_rcd_enq (k2y_rcd_enq), // output (dmu_dmc) => (dmu_ilu)
657 .y2k_rcd_deq (y2k_rcd_deq), // input (dmu_dmc) <= (dmu_ilu)
658 .k2y_rel_rcd (k2y_rel_rcd[8:0]), // output (dmu_dmc) => (dmu_ilu)
659 .k2y_rel_enq (k2y_rel_enq), // output (dmu_dmc) => (dmu_ilu)
660 .k2y_dbg_sel_a (k2y_dbg_sel_a[5:0]), // output (dmu_dmc) => (dmu_ilu)
661 .k2y_dbg_sel_b (k2y_dbg_sel_b[5:0]), // output (dmu_dmc) => (dmu_ilu)
662 .y2k_dbg_a (y2k_dbg_a[7:0]), // input (dmu_dmc) <= (dmu_ilu)
663 .y2k_dbg_b (y2k_dbg_b[7:0]), // input (dmu_dmc) <= (dmu_ilu)
664 .dsn_dmc_iei (dsn_dmc_iei), // input (dmu_dmc) <= (dmu_ilu)
665 .dmu_dbg_err_event (dmu_dbg_err_event), // input (imu) => ()
666 .ds2cl_stall (ds2cl_stall), // output (dmu_dsn) => (dmu_dmc/clu)
667 .dmu_cb0_run (dmu_cb0_run), // input (dmu_dmc) <= (dmu_cb0)
668 .dmu_cb0_addr (dmu_cb0_addr), // input (dmu_dmc) <= (dmu_cb0)
669 .dmu_cb0_wdata_key (dmu_cb0_wdata_key), // input (dmu_dmc) <= (dmu_cb0)
670 .dmu_cb0_mmu_vtb_wr_en (dmu_cb0_mmu_vtb_wr_en), // input (dmu_dmc) <= (dmu_cb0)
671 .dmu_cb0_mmu_vtb_rd_en (dmu_cb0_mmu_vtb_rd_en), // input (dmu_dmc) <= (dmu_cb0)
672 .dmu_cb0_mmu_vtb_lkup_en (dmu_cb0_mmu_vtb_lkup_en), // input (dmu_dmc) <= (dmu_cb0)
673 .dmu_cb0_mmu_ptb_wr_en (dmu_cb0_mmu_ptb_wr_en), // input (dmu_dmc) <= (dmu_cb0)
674 .dmu_cb0_mmu_ptb_rd_en (dmu_cb0_mmu_ptb_rd_en), // input (dmu_dmc) <= (dmu_cb0)
675 .dmu_cb0_mmu_ptb_lkup_en (dmu_cb0_mmu_ptb_lkup_en), // input (dmu_dmc) <= (dmu_cb0)
676 .dmu_cb0_hld (dmu_cb0_hld), // input (dmu_dmc) <= (dmu_cb0)
677 .vtb2csr_rd (vtb2csr_rd), // output (dmu_dmc) => (dmu_cb0)
678 .vtb_dout_4msb (vtb_dout_4msb), // output (dmu_dmc) => (dmu_cb0)
679 .mmu_ptb_read_data (mmu_ptb_read_data), // output (dmu_dmc) => (dmu_cb0)
680 .mmu_vtb_hit (mmu_vtb_hit), // output (dmu_dmc) => (dmu_cb0)
681 .mmu_ptb_hit (mmu_ptb_hit), // output (dmu_dmc) => (dmu_cb0)
682 .tdb_dout_8msb (tdb_dout_8msb), // output (dmu_dmc) => (dmu_mb0)
683 .dmu_mb0_run (dmu_mb0_run), // input (dmu_dmc) <= (dmu_mb0)
684 .dmu_mb0_addr (dmu_mb0_addr), // input (dmu_dmc) <= (dmu_mb0)
685 .dmu_mb0_wdata (dmu_mb0_wdata), // input (dmu_dmc) <= (dmu_mb0)
686 .dmu_mb0_tdb_wr_en (dmu_mb0_tdb_wr_en), // input (dmu_dmc) <= (dmu_mb0)
687 .dmu_mb0_tdb_rd_en (dmu_mb0_tdb_rd_en), // input (dmu_dmc) <= (dmu_mb0)
688 .tdb2csr_rd (tdb2csr_rd), // output (dmu_dmc) => (dmu_mb0)
689 .dmu_mb0_dev_wr_en (dmu_mb0_dev_wr_en), // input (dmu_dmc) <= (dmu_mb0)
690 .dmu_mb0_dev_rd_en (dmu_mb0_dev_rd_en), // input (dmu_dmc) <= (dmu_mb0)
691 .dmu_mb0_tsb_wr_en (dmu_mb0_tsb_wr_en), // input (dmu_dmc) <= (dmu_mb0)
692 .dmu_mb0_tsb_rd_en (dmu_mb0_tsb_rd_en), // input (dmu_dmc) <= (dmu_mb0)
693 .dev_tsb_read_data (dev_tsb_read_data), // output (dmu_dmc) => (dmu_mb0)
694 .dmu_diu_read_data (dmu_diu_read_data), // output (dmu_dmc) => (dmu_mb0)
695 .dmu_mb0_diu_wr_en (dmu_mb0_diu_wr_en), // input (dmu_dmc) <= (dmu_mb0)
696 .dmu_mb0_diu_rd_en (dmu_mb0_diu_rd_en), // input (dmu_dmc) <= (dmu_mb0)
697 .dmu_mb0_dou_dma_data_wr_en (dmu_mb0_dou_dma_data_wr_en), // input (dmu_dmc) <= (dmu_mb0)
698 .dmu_mb0_dou_dma_data_rd_en (dmu_mb0_dou_dma_data_rd_en), // input (dmu_dmc) <= (dmu_mb0)
699 .dmu_mb0_dou_pio_data_wr_en (dmu_mb0_dou_pio_data_wr_en), // input (dmu_dmc) <= (dmu_mb0)
700 .dmu_mb0_dou_pio_data_rd_en (dmu_mb0_dou_pio_data_rd_en), // input (dmu_dmc) <= (dmu_mb0)
701 .dmu_dou_pio_read_data (dmu_dou_pio_read_data), // output (dmu_dmc) => (dmu_mb0)
702 .dmu_dou_dma_read_data (dmu_dou_dma_read_data), // output (dmu_dmc) => (dmu_mb0)
703 .efu_dmu_data (efu_dmu_data), // input efu to devtsb
704 .efu_dmu_xfer_en (efu_dmu_xfer_en), // input efu to devtsb
705 .efu_dmu_clr (efu_dmu_clr), // input efu to devtsb
706 .dmu_efu_data (dmu_efu_data), // output of devtsb to efu
707 .dmu_efu_xfer_en (dmu_efu_xfer_en), // output of devtsb to efu
708 .d2p_idb_rd (d2p_idb_rd), // rd en to peu idb ram
709 .d2p_req_id (d2p_req_id), // req id to peu for messages BP 8-18-05
710 .p2d_npwr_stall_en (p2d_npwr_stall_en), // non-posted write stall enable from peu
711 .il2cl_gr_16 (il2cl_gr_16) // greater than 16 pio stall from ilu
712
713
714 );
715`endif // `ifdef NO_DMC
716
717`ifdef NO_DSN
718`else
719dmu_dsn dsn (
720 .l1clk (l1clk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
721 .rst_l (wmr_), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
722 .dmu_sii_hdr_vld (dmu_sii_hdr_vld), // output (dmu_dsn) => ()
723 .dmu_sii_reqbypass (dmu_sii_reqbypass), // output (dmu_dsn) => ()
724 .dmu_sii_datareq (dmu_sii_datareq), // output (dmu_dsn) => ()
725 .dmu_sii_datareq16 (dmu_sii_datareq16), // output (dmu_dsn) => ()
726 .dmu_sii_data (dmu_sii_data[127:0]), // output (dmu_dsn) => ()
727 .dmu_sii_parity (dmu_sii_parity[7:0]), // output (dmu_dsn) => ()
728 .dmu_sii_be_parity (dmu_sii_be_parity), // output (dmu_dsn) => ()
729 .dmu_sii_be (dmu_sii_be[15:0]), // output (dmu_dsn) => ()
730 .sii_dmu_wrack_tag (sii_dmu_wrack_tag[3:0]), // input (dmu_dsn) <= ()
731 .sii_dmu_wrack_par (sii_dmu_wrack_par), // input (dmu_dsn) <= () n2 RAS
732 .sii_dmu_wrack_vld (sii_dmu_wrack_vld), // input (dmu_dsn) <= ()
733 .sio_dmu_hdr_vld (sio_dmu_hdr_vld), // input (dmu_dsn) <= ()
734 .sio_dmu_data (sio_dmu_data[127:0]), // input (dmu_dsn) <= ()
735 .sio_dmu_parity (sio_dmu_parity[7:0]), // input (dmu_dsn) <= ()
736 .dmu_ncu_stall (dmu_ncu_stall), // output (dmu_dsn) => ()
737 .ncu_dmu_vld (ncu_dmu_vld), // input (dmu_dsn) <= ()
738 .ncu_dmu_data (ncu_dmu_data[31:0]), // input (dmu_dsn) <= ()
739 .ncu_dmu_stall (ncu_dmu_stall), // input (dmu_dsn) <= ()
740 .dmu_ncu_vld (dmu_ncu_vld), // output (dmu_dsn) => ()
741 .dmu_ncu_data (dmu_ncu_data[31:0]), // output (dmu_dsn) => ()
742 .j2d_csr_ring_out (j2d_csr_ring_out[31:0]), // output (dmu_dsn) => (dmu_dmc)
743 .d2j_csr_ring_in (d2j_csr_ring_in[31:0]), // input (dmu_dsn) <= (dmu_dmc)
744 .ncu_dmu_pio_hdr_vld (ncu_dmu_pio_hdr_vld), // input (dmu_dsn) <= ()
745 .ncu_dmu_mmu_addr_vld (ncu_dmu_mmu_addr_vld), // input (dmu_dsn) <= ()
746 .ncu_dmu_pio_data (ncu_dmu_pio_data[63:0]), // input (dmu_dsn) <= ()
747 .dmu_ncu_wrack_vld (dmu_ncu_wrack_vld), // output (dmu_dsn) => ()
748 .dmu_ncu_wrack_tag (dmu_ncu_wrack_tag[3:0]), // output (dmu_dsn) => ()
749 .dmu_ncu_wrack_par (dmu_ncu_wrack_par), // output (dmu_dsn) => () n2 RAS
750 .dmu_ncu_d_pe (dmu_ncu_d_pe), // output (dmu_dsn) => () n2 RAS
751 .dmu_ncu_siicr_pe (dmu_ncu_siicr_pe), // output (dmu_dsn) => () n2 RAS
752 .dmu_ncu_ctag_ue (dmu_ncu_ctag_ue), // output (dmu_dsn) => () n2 RAS
753 .dmu_ncu_ctag_ce (dmu_ncu_ctag_ce), // output (dmu_dsn) => () n2 RAS
754 .dmu_ncu_ncucr_pe (dmu_ncu_ncucr_pe), // output (dmu_dsn) => () n2 RAS
755 .dmu_ncu_ie (dmu_ncu_ie), // output (dmu_dsn) => () n2 RAS
756 .ncu_dmu_mondo_ack (ncu_dmu_mondo_ack), // input (dmu_dsn) <= ()
757 .ncu_dmu_mondo_nack (ncu_dmu_mondo_nack), // input (dmu_dsn) <= ()
758 .ncu_dmu_mondo_id (ncu_dmu_mondo_id[5:0]), // input (dmu_dsn) <= ()
759 .ncu_dmu_mondo_id_par (ncu_dmu_mondo_id_par), // input (dmu_dsn) <= () n2 RAS
760 .ncu_dmu_d_pei (ncu_dmu_d_pei), // input (dmu_dsn) <= () n2 RAS
761 .ncu_dmu_siicr_pei (ncu_dmu_siicr_pei), // input (dmu_dsn) <= () n2 RAS
762 .ncu_dmu_ctag_uei (ncu_dmu_ctag_uei), // input (dmu_dsn) <= () n2 RAS
763 .ncu_dmu_ctag_cei (ncu_dmu_ctag_cei), // input (dmu_dsn) <= () n2 RAS
764 .ncu_dmu_ncucr_pei (ncu_dmu_ncucr_pei), // input (dmu_dsn) <= () n2 RAS
765 .ncu_dmu_iei (ncu_dmu_iei), // input (dmu_dsn) <= () n2 RAS
766 .d2j_cmd (d2j_cmd[3:0]), // input (dmu_dsn) <= (dmu_dmc)
767 .d2j_addr (d2j_addr[36:0]), // input (dmu_dsn) <= (dmu_dmc)
768 .d2j_ctag (d2j_ctag[15:0]), // input (dmu_dsn) <= (dmu_dmc)
769 .d2j_cmd_vld (d2j_cmd_vld), // input (dmu_dsn) <= (dmu_dmc)
770 .d2j_data (d2j_data[127:0]), // input (dmu_dsn) <= (dmu_dmc)
771 .d2j_bmsk (d2j_bmsk[15:0]), // input (dmu_dsn) <= (dmu_dmc)
772 .d2j_data_par (d2j_data_par[4:0]), // input (dmu_dsn) <= (dmu_dmc)
773 .d2j_data_vld (d2j_data_vld), // input (dmu_dsn) <= (dmu_dmc)
774 .j2d_d_wrack_tag (j2d_d_wrack_tag[3:0]), // output (dmu_dsn) => (dmu_dmc)
775 .j2d_d_wrack_vld (j2d_d_wrack_vld), // output (dmu_dsn) => (dmu_dmc)
776 .d2j_p_wrack_tag (d2j_p_wrack_tag[3:0]), // input (dmu_dsn) <= (dmu_dmc)
777 .d2j_p_wrack_vld (d2j_p_wrack_vld), // input (dmu_dsn) <= (dmu_dmc)
778 .j2d_di_cmd (j2d_di_cmd[1:0]), // output (dmu_dsn) => (dmu_dmc)
779 .j2d_di_ctag (j2d_di_ctag[15:0]), // output (dmu_dsn) => (dmu_dmc)
780 .j2d_di_cmd_vld (j2d_di_cmd_vld), // output (dmu_dsn) => (dmu_dmc)
781 .j2d_p_cmd (j2d_p_cmd[3:0]), // output (dmu_dsn) => (dmu_dmc)
782 .j2d_p_addr (j2d_p_addr[35:0]), // output (dmu_dsn) => (dmu_dmc)
783 .j2d_p_bmsk (j2d_p_bmsk[15:0]), // output (dmu_dsn) => (dmu_dmc)
784 .j2d_p_ctag (j2d_p_ctag[10:0]), // output (dmu_dsn) => (dmu_dmc)
785 .j2d_p_cmd_vld (j2d_p_cmd_vld), // output (dmu_dsn) => (dmu_dmc)
786 .j2d_d_data (j2d_d_data[127:0]), // output (dmu_dsn) => (dmu_dmc)
787 .j2d_d_data_par (j2d_d_data_par[3:0]), // output (dmu_dsn) => (dmu_dmc)
788 .j2d_d_data_err (j2d_d_data_err), // output (dmu_dsn) => (dmu_dmc)
789 .j2d_d_data_vld (j2d_d_data_vld), // output (dmu_dsn) => (dmu_dmc)
790 .j2d_p_data (j2d_p_data[127:0]), // output (dmu_dsn) => (dmu_dmc)
791 .j2d_p_data_par (j2d_p_data_par[3:0]), // output (dmu_dsn) => (dmu_dmc)
792 .j2d_p_data_vld (j2d_p_data_vld), // output (dmu_dsn) => (dmu_dmc)
793 .j2d_mmu_addr_vld (j2d_mmu_addr_vld), // output (dmu_dsn) => (dmu_dmc)
794 .j2d_mmu_addr (j2d_mmu_addr[42:6]), // output (dmu_dsn) => (dmu_dmc)
795 .dsn_dmc_iei (dsn_dmc_iei), // output (dmu_dsn) => (dmu_dmc)
796 .cr2ds_dbg_sel_a (cr2ds_dbg_sel_a[5:0]), // input () <= (dmu_cru)
797 .cr2ds_dbg_sel_b (cr2ds_dbg_sel_b[5:0]), // input () <= (dmu_cru)
798 .ds2cr_dbg_a (ds2cr_dbg_a[7:0]), // output (dmu_dsn) => (dmu_dmc)
799 .ds2cr_dbg_b (ds2cr_dbg_b[7:0]), // output (dmu_dsn) => (dmu_dmc)
800 .dbg1_dmu_stall (dbg1_dmu_stall), // output (dmu_dsn) => (dmu_dmc)
801 .dbg1_dmu_resume (dbg1_dmu_resume), // output (dmu_dsn) => (dmu_dmc)
802 .dmu_dbg1_stall_ack (dmu_dbg1_stall_ack), // output (dmu_dsn) => (dmu_dmc)
803 .ds2cl_stall (ds2cl_stall) // output (dmu_dsn) => (dmu_dmc/clu)
804 );
805`endif // `ifdef NO_DSN
806
807`ifdef NO_ILU
808`else
809dmu_ilu ilu (
810 .l1clk (l1clk), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
811 .rst_wmr_ (rst_wmr_), // input (dmu_ilu) <= ()
812 .rst_dmu_async_por_ (rst_dmu_async_por_), // input (dmu_ilu) <= ()
813 .j2d_por_l (por_), // input (dmu_dmc,dmu_ilu) <= ()
814 .j2d_rst_l (wmr_), // input (dmu_dmc,dmu_dsn,dmu_ilu) <= ()
815 .j2d_instance_id (j2d_instance_id), // input (dmu_ilu) <= ()
816 .p2d_ihb_wptr (p2d_ihb_wptr[6:0]), // input (dmu_ilu) <= ()
817 .p2d_ihb_data (p2d_ihb_data[127:0]), // input (dmu_ilu) <= ()
818 .d2p_ihb_addr (d2p_ihb_addr[5:0]), // output (dmu_ilu) => ()
819 .p2d_ihb_dpar (p2d_ihb_dpar[3:0]), // input (dmu_ilu) <= ()
820 .d2p_ihb_rd (d2p_ihb_rd), // output (dmu_ilu) => ()
821 .d2p_idb_addr (d2p_idb_addr[7:0]), // output (dmu_ilu) => ()
822 .p2d_idb_data (p2d_idb_data[127:0]), // input (dmu_ilu) <= ()
823 .p2d_idb_dpar (p2d_idb_dpar[3:0]), // input (dmu_ilu) <= ()
824 .d2p_ibc_req (d2p_ibc_req), // output (dmu_ilu) => ()
825 .p2d_ibc_ack (p2d_ibc_ack), // input (dmu_ilu) <= ()
826 .d2p_ibc_nhc (d2p_ibc_nhc[7:0]), // output (dmu_ilu) => ()
827 .d2p_ibc_phc (d2p_ibc_phc[7:0]), // output (dmu_ilu) => ()
828 .d2p_ibc_pdc (d2p_ibc_pdc[11:0]), // output (dmu_ilu) => ()
829 .p2d_cto_req (p2d_cto_req), // input (dmu_ilu) <= ()
830 .p2d_cto_tag (p2d_cto_tag[4:0]), // input (dmu_ilu) <= ()
831 .d2p_cto_ack (d2p_cto_ack), // output (dmu_ilu) => ()
832 .d2p_ech_wptr (d2p_ech_wptr[5:0]), // output (dmu_ilu) => ()
833 .p2d_ech_rptr (p2d_ech_rptr[5:0]), // input (dmu_ilu) <= ()
834 .d2p_erh_wptr (d2p_erh_wptr[5:0]), // output (dmu_ilu) => ()
835 .p2d_erh_rptr (p2d_erh_rptr[5:0]), // input (dmu_ilu) <= ()
836 .p2d_ecd_rptr (p2d_ecd_rptr[7:0]), // input (dmu_ilu) <= ()
837 .p2d_erd_rptr (p2d_erd_rptr[7:0]), // input (dmu_ilu) <= ()
838 .d2p_ehb_we (d2p_ehb_we), // output (dmu_ilu) => ()
839 .d2p_ehb_addr (d2p_ehb_addr[5:0]), // output (dmu_ilu) => ()
840 .d2p_ehb_data (d2p_ehb_data[127:0]), // output (dmu_ilu) => ()
841 .d2p_ehb_dpar (d2p_ehb_dpar[3:0]), // output (dmu_ilu) => ()
842 .d2p_edb_we (d2p_edb_we), // output (dmu_ilu) => ()
843 .d2p_edb_addr (d2p_edb_addr[7:0]), // output (dmu_ilu) => ()
844 .d2p_edb_data (d2p_edb_data[127:0]), // output (dmu_ilu) => ()
845 .d2p_edb_dpar (d2p_edb_dpar[3:0]), // output (dmu_ilu) => ()
846 .p2d_drain (p2d_drain), // input (dmu_ilu) <= ()
847 .p2d_mps (p2d_mps[2:0]), // input (dmu_ilu) <= ()
848 .p2d_ue_int (p2d_ue_int), // input (dmu_ilu) <= ()
849 .p2d_ce_int (p2d_ce_int), // input (dmu_ilu) <= ()
850 .p2d_oe_int (p2d_oe_int), // input (dmu_ilu) <= ()
851 .k2y_buf_addr_vld_monitor (k2y_buf_addr_vld_monitor), // input (dmu_ilu) <= (dmu_dmc)
852 .k2y_buf_addr (k2y_buf_addr[7:0]), // input (dmu_ilu) <= (dmu_dmc)
853 .y2k_buf_data (y2k_buf_data[127:0]), // output (dmu_ilu) => (dmu_dmc)
854 .y2k_buf_dpar (y2k_buf_dpar[3:0]), // output (dmu_ilu) => (dmu_dmc)
855 .y2k_buf_addr_vld_monitor (y2k_buf_addr_vld_monitor), // output (dmu_ilu) => (dmu_dmc)
856 .y2k_buf_addr (y2k_buf_addr[7:0]), // output (dmu_ilu) => (dmu_dmc)
857 .k2y_buf_data (k2y_buf_data[127:0]), // input (dmu_ilu) <= (dmu_dmc)
858 .k2y_buf_dpar (k2y_buf_dpar[3:0]), // input (dmu_ilu) <= (dmu_dmc)
859 .k2y_rcd_deq (k2y_rcd_deq), // input (dmu_ilu) <= (dmu_dmc)
860 .y2k_rcd (y2k_rcd[115:0]), // output (dmu_ilu) => (dmu_dmc)
861 .y2k_rcd_enq (y2k_rcd_enq), // output (dmu_ilu) => (dmu_dmc)
862 .k2y_rcd (k2y_rcd[123:0]), // input (dmu_ilu) <= (dmu_dmc)
863 .k2y_rcd_enq (k2y_rcd_enq), // input (dmu_ilu) <= (dmu_dmc)
864 .y2k_rcd_deq (y2k_rcd_deq), // output (dmu_ilu) => (dmu_dmc)
865 .k2y_rel_rcd (k2y_rel_rcd[8:0]), // input (dmu_ilu) <= (dmu_dmc)
866 .k2y_rel_enq (k2y_rel_enq), // input (dmu_ilu) <= (dmu_dmc)
867 .y2k_rel_rcd (y2k_rel_rcd[8:0]), // output (dmu_ilu) => (dmu_dmc)
868 .y2k_rel_enq (y2k_rel_enq), // output (dmu_ilu) => (dmu_dmc)
869 .k2y_dou_dptr (k2y_dou_dptr[4:0]), // input (dmu_ilu) <= (dmu_dmc)
870 .k2y_dou_err (k2y_dou_err), // input (dmu_ilu) <= (dmu_dmc)
871 .k2y_dou_vld (k2y_dou_vld), // input (dmu_ilu) <= (dmu_dmc)
872 .y2k_mps (y2k_mps[2:0]), // output (dmu_ilu) => (dmu_dmc)
873 .y2k_int_l (y2k_int_l), // output (dmu_ilu) => (dmu_dmc)
874 .k2y_csr_ring_out (k2y_csr_ring_out[31:0]), // input (dmu_ilu) <= (dmu_dmc)
875 .y2k_csr_ring_in (y2k_csr_ring_in[31:0]), // output (dmu_ilu) => (dmu_dmc)
876 .d2p_csr_req (d2p_csr_req), // output (dmu_ilu) => ()
877 .p2d_csr_ack (p2d_csr_ack), // input (dmu_ilu) <= ()
878 .d2p_csr_rcd (d2p_csr_rcd[95:0]), // output (dmu_ilu) => ()
879 .p2d_csr_req (p2d_csr_req), // input (dmu_ilu) <= ()
880 .d2p_csr_ack (d2p_csr_ack), // output (dmu_ilu) => ()
881 .p2d_csr_rcd (p2d_csr_rcd[95:0]), // input (dmu_ilu) <= ()
882 .k2y_dbg_sel_a (k2y_dbg_sel_a[5:0]), // input (dmu_ilu) <= (dmu_dmc)
883 .k2y_dbg_sel_b (k2y_dbg_sel_b[5:0]), // input (dmu_ilu) <= (dmu_dmc)
884 .y2k_dbg_a (y2k_dbg_a[7:0]), // output (dmu_ilu) => (dmu_dmc)
885 .y2k_dbg_b (y2k_dbg_b[7:0]), // output (dmu_ilu) => (dmu_dmc)
886 .p2d_spare (p2d_spare[4:0]), // input (dmu_ilu) <= ()
887 .d2p_spare (d2p_spare[4:0]), // output (dmu_ilu) => ()
888 .dmu_psr_rate_scale (dmu_psr_rate_scale), // output (dmu_ilu) => ()
889 .dmu_psr_pll_en_sds0 (dmu_psr_pll_en_sds0), // output (dmu_ilu) => (peu)
890 .dmu_psr_pll_en_sds1 (dmu_psr_pll_en_sds1), // output (dmu_ilu) => (peu)
891 .dmu_psr_rx_en_b0_sds0 (dmu_psr_rx_en_b0_sds0), // output (dmu_ilu) => (peu)
892 .dmu_psr_rx_en_b1_sds0 (dmu_psr_rx_en_b1_sds0), // output (dmu_ilu) => (peu)
893 .dmu_psr_rx_en_b2_sds0 (dmu_psr_rx_en_b2_sds0), // output (dmu_ilu) => (peu)
894 .dmu_psr_rx_en_b3_sds0 (dmu_psr_rx_en_b3_sds0), // output (dmu_ilu) => (peu)
895 .dmu_psr_rx_en_b0_sds1 (dmu_psr_rx_en_b0_sds1), // output (dmu_ilu) => (peu)
896 .dmu_psr_rx_en_b1_sds1 (dmu_psr_rx_en_b1_sds1), // output (dmu_ilu) => (peu)
897 .dmu_psr_rx_en_b2_sds1 (dmu_psr_rx_en_b2_sds1), // output (dmu_ilu) => (peu)
898 .dmu_psr_rx_en_b3_sds1 (dmu_psr_rx_en_b3_sds1), // output (dmu_ilu) => (peu)
899 .dmu_psr_tx_en_b0_sds0 (dmu_psr_tx_en_b0_sds0), // output (dmu_ilu) => (peu)
900 .dmu_psr_tx_en_b1_sds0 (dmu_psr_tx_en_b1_sds0), // output (dmu_ilu) => (peu)
901 .dmu_psr_tx_en_b2_sds0 (dmu_psr_tx_en_b2_sds0), // output (dmu_ilu) => (peu)
902 .dmu_psr_tx_en_b3_sds0 (dmu_psr_tx_en_b3_sds0), // output (dmu_ilu) => (peu)
903 .dmu_psr_tx_en_b0_sds1 (dmu_psr_tx_en_b0_sds1), // output (dmu_ilu) => (peu)
904 .dmu_psr_tx_en_b1_sds1 (dmu_psr_tx_en_b1_sds1), // output (dmu_ilu) => (peu)
905 .dmu_psr_tx_en_b2_sds1 (dmu_psr_tx_en_b2_sds1), // output (dmu_ilu) => (peu)
906 .dmu_psr_tx_en_b3_sds1 (dmu_psr_tx_en_b3_sds1), // output (dmu_ilu) => (peu)
907 .tcu_test_protect (tcu_test_protect), // input (tcu) => (ilu)
908 .il2cl_gr_16 (il2cl_gr_16) // output (ilu) => (crm)
909
910 );
911`endif // `ifdef NO_ILU
912
913`ifdef NO_MB0
914`else
915dmu_mb0 mb0 (
916 .scan_in (tcu_dmu_mbist_scan_in),
917 .scan_out (dmu_mb0_scanout),
918 .l1clk (l1clk),
919 .tcu_aclk (aclk),
920 .tcu_bclk (bclk),
921 .rst_ (wmr_),
922 .tcu_dmu_mb0_start (tcu_dmu_mbist_start[0]),
923 .dmu_mb0_bisi_mode (tcu_mbist_bisi_en),
924 .dmu_mb0_user_mode (tcu_mbist_user_mode),
925 .dmu_mb0_run (dmu_mb0_run),
926 .dmu_mb0_addr (dmu_mb0_addr),
927 .dmu_mb0_wdata (dmu_mb0_wdata),
928 .dmu_mb0_diu_wr_en (dmu_mb0_diu_wr_en),
929 .dmu_mb0_diu_rd_en (dmu_mb0_diu_rd_en),
930 .dmu_mb0_tdb_wr_en (dmu_mb0_tdb_wr_en),
931 .dmu_mb0_tdb_rd_en (dmu_mb0_tdb_rd_en),
932 .dmu_mb0_dou_dma_data_wr_en (dmu_mb0_dou_dma_data_wr_en),
933 .dmu_mb0_dou_dma_data_rd_en (dmu_mb0_dou_dma_data_rd_en),
934 .dmu_mb0_dou_pio_data_wr_en (dmu_mb0_dou_pio_data_wr_en),
935 .dmu_mb0_dou_pio_data_rd_en (dmu_mb0_dou_pio_data_rd_en),
936 .dmu_mb0_dev_wr_en (dmu_mb0_dev_wr_en),
937 .dmu_mb0_dev_rd_en (dmu_mb0_dev_rd_en),
938 .dmu_mb0_tsb_wr_en (dmu_mb0_tsb_wr_en),
939 .dmu_mb0_tsb_rd_en (dmu_mb0_tsb_rd_en),
940 .dmu_mb0_done (dmu_tcu_mbist_done[0]),
941 .dmu_mb0_fail (dmu_tcu_mbist_fail[0]),
942 .dmu_diu_read_data (dmu_diu_read_data),
943 .dmu_tdb_read_data ({tdb_dout_8msb,tdb2csr_rd}),
944 .dmu_dou_dma_read_data (dmu_dou_dma_read_data),
945 .dmu_dou_pio_read_data (dmu_dou_pio_read_data),
946 .dev_tsb_read_data (dev_tsb_read_data)
947
948);
949
950
951`endif // `ifdef NO_MB0
952
953
954/* CAM BIST Place Holder */
955
956`ifdef NO_CB0
957`else
958dmu_cb0 cb0 (
959 .dmu_cb0_run (dmu_cb0_run),
960 .dmu_cb0_addr (dmu_cb0_addr),
961 .dmu_cb0_wdata_key (dmu_cb0_wdata_key),
962 .dmu_cb0_mmu_vtb_wr_en (dmu_cb0_mmu_vtb_wr_en),
963 .dmu_cb0_mmu_vtb_rd_en (dmu_cb0_mmu_vtb_rd_en),
964 .dmu_cb0_mmu_vtb_lkup_en (dmu_cb0_mmu_vtb_lkup_en),
965 .dmu_cb0_mmu_ptb_wr_en (dmu_cb0_mmu_ptb_wr_en),
966 .dmu_cb0_mmu_ptb_rd_en (dmu_cb0_mmu_ptb_rd_en),
967 .dmu_cb0_mmu_ptb_lkup_en (dmu_cb0_mmu_ptb_lkup_en),
968 .dmu_cb0_hld (dmu_cb0_hld),
969 .dmu_cb0_done (dmu_tcu_mbist_done[1]),
970 .dmu_cb0_fail (dmu_tcu_mbist_fail[1]),
971 .scan_out (dmu_tcu_mbist_scan_out),
972 .l1clk (l1clk),
973 .scan_in (dmu_mb0_scanout),
974 .tcu_aclk (aclk),
975 .tcu_bclk (bclk),
976 .rst_ (wmr_),
977 .tcu_dmu_cb0_start (tcu_dmu_mbist_start[1]),
978 .dmu_cb0_bisi_mode (tcu_mbist_bisi_en),
979 .dmu_cb0_user_mode (tcu_mbist_user_mode),
980 .mmu_vtb_read_data ({vtb_dout_4msb,vtb2csr_rd[5:1],vtb2csr_rd[29:6]}),
981 .mmu_ptb_read_data (mmu_ptb_read_data),
982 .mmu_vtb_hit (mmu_vtb_hit),
983 .mmu_ptb_hit (mmu_ptb_hit)
984) ;
985
986`endif // `ifdef NO_CB0
987
988
989
990
991endmodule
992
993
Full OpenSPARC design & verification tarball including full HDL.