projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: dmu_clu.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module dmu_clu | |
| 36 | ( | |
| 37 | // clock/reset | |
| 38 | clk, | |
| 39 | rst_l, | |
| 40 | ||
| 41 | // jbc: dmc req/cpl port | |
| 42 | d2j_cmd, | |
| 43 | d2j_addr, | |
| 44 | d2j_ctag, | |
| 45 | d2j_cmd_vld, | |
| 46 | d2j_data, | |
| 47 | d2j_bmsk, | |
| 48 | d2j_data_par, | |
| 49 | d2j_data_vld, | |
| 50 | ||
| 51 | // jbc : jbc req/cpl port | |
| 52 | j2d_d_wrack_tag, | |
| 53 | j2d_d_wrack_vld, | |
| 54 | j2d_di_cmd, | |
| 55 | j2d_di_ctag, | |
| 56 | j2d_di_cmd_vld, | |
| 57 | j2d_p_cmd, | |
| 58 | j2d_p_addr, | |
| 59 | j2d_p_bmsk, | |
| 60 | j2d_p_ctag, | |
| 61 | j2d_p_cmd_vld, | |
| 62 | j2d_d_data, | |
| 63 | j2d_d_data_par, | |
| 64 | j2d_d_data_err, | |
| 65 | j2d_d_data_vld, | |
| 66 | j2d_p_data, | |
| 67 | j2d_p_data_par, | |
| 68 | j2d_p_data_vld, | |
| 69 | ||
| 70 | // ilu: dou-dma status port | |
| 71 | k2y_dou_dptr, | |
| 72 | k2y_dou_err, | |
| 73 | k2y_dou_vld, | |
| 74 | ||
| 75 | // psb: sbd access port | |
| 76 | cl2ps_e_cmd_type, | |
| 77 | cl2ps_e_trn, | |
| 78 | cl2ps_e_wr_data, | |
| 79 | cl2ps_e_req, | |
| 80 | ps2cl_e_rd_data, | |
| 81 | ps2cl_e_gnt, | |
| 82 | ||
| 83 | // pmu: icr port | |
| 84 | cl2pm_rcd_full, | |
| 85 | pm2cl_rcd, | |
| 86 | pm2cl_rcd_enq, | |
| 87 | ||
| 88 | // cmu: epr port | |
| 89 | cl2cm_rcd, | |
| 90 | cl2cm_rcd_enq, | |
| 91 | cm2cl_rcd_full, | |
| 92 | ||
| 93 | // mmu: tcr port | |
| 94 | cl2mm_tcr_ack, | |
| 95 | mm2cl_tcr_rcd, | |
| 96 | mm2cl_tcr_req, | |
| 97 | ||
| 98 | // mmu : tdr port | |
| 99 | cl2mm_tdr_rcd, | |
| 100 | cl2mm_tdr_vld, | |
| 101 | ||
| 102 | // rmu: dou dma buffer rel port | |
| 103 | rm2cl_bufrel, | |
| 104 | rm2cl_bufrel_enq, | |
| 105 | ||
| 106 | // tmu: diu buffer mgr port | |
| 107 | cl2tm_dma_rptr, | |
| 108 | cl2tm_int_rptr, | |
| 109 | tm2cl_dma_wptr, | |
| 110 | tm2cl_pio_wptr, | |
| 111 | ||
| 112 | // diu: data read port | |
| 113 | cl2di_addr, | |
| 114 | cl2di_rd_en, | |
| 115 | di2cl_data, | |
| 116 | di2cl_bmask, | |
| 117 | di2cl_dpar, | |
| 118 | ||
| 119 | // dou : data write port | |
| 120 | cl2do_dma_data, | |
| 121 | cl2do_dma_dpar, | |
| 122 | cl2do_dma_addr, | |
| 123 | cl2do_dma_wr, | |
| 124 | cl2do_pio_data, | |
| 125 | cl2do_pio_dpar, | |
| 126 | cl2do_pio_addr, | |
| 127 | cl2do_pio_wr, | |
| 128 | ||
| 129 | // cru : debug ports | |
| 130 | cl2cr_dbg_a, | |
| 131 | cl2cr_dbg_b, | |
| 132 | cr2cl_dbg_sel_a, | |
| 133 | cr2cl_dbg_sel_b, | |
| 134 | ||
| 135 | // cru : config packet setup | |
| 136 | cr2cl_bus_num, | |
| 137 | // for N2 dbg quiescing | |
| 138 | ds2cl_stall, | |
| 139 | // force 1 outstanding non-posted write | |
| 140 | p2d_npwr_stall_en, | |
| 141 | rm2crm_npwr_wrack, | |
| 142 | // enables for 2 fixes for bug 107207 from spare imu | |
| 143 | im2crm_bc_stall_en, | |
| 144 | im2crm_ilu_stall_en, | |
| 145 | il2cl_gr_16 | |
| 146 | ); | |
| 147 | ||
| 148 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
| 149 | ||
| 150 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
| 151 | ||
| 152 | // -------------------------------------------------------- | |
| 153 | // Clock/Reset Signals | |
| 154 | // -------------------------------------------------------- | |
| 155 | ||
| 156 | input clk; | |
| 157 | input rst_l; | |
| 158 | ||
| 159 | // -------------------------------------------------------- | |
| 160 | // JBC Interface | |
| 161 | // -------------------------------------------------------- | |
| 162 | ||
| 163 | // ----- CTM: DMC Req/Cpl Port ----- | |
| 164 | ||
| 165 | // command port | |
| 166 | output [(`FIRE_D2J_CMD_WDTH - 1):0] d2j_cmd; | |
| 167 | output [(`FIRE_D2J_ADDR_WDTH - 1):0] d2j_addr; | |
| 168 | output [(`FIRE_D2J_CTAG_WDTH - 1):0] d2j_ctag; | |
| 169 | output d2j_cmd_vld; | |
| 170 | ||
| 171 | // data port | |
| 172 | output [(`FIRE_D2J_DATA_WDTH - 1):0] d2j_data; | |
| 173 | output [(`FIRE_D2J_BMSK_WDTH - 1):0] d2j_bmsk; | |
| 174 | output [(`FIRE_D2J_DPAR_WDTH - 1):0] d2j_data_par; | |
| 175 | output d2j_data_vld; | |
| 176 | ||
| 177 | // ----- CTM: DMA Wrack Port ----- | |
| 178 | input [(`FIRE_J2D_D_WRACK_WDTH - 1):0] j2d_d_wrack_tag; | |
| 179 | input j2d_d_wrack_vld; | |
| 180 | ||
| 181 | // ----- CRM: Req/Cpl Command Port ----- | |
| 182 | ||
| 183 | // completion port | |
| 184 | input [(`FIRE_J2D_DI_CMD_WDTH - 1):0] j2d_di_cmd; | |
| 185 | input [(`FIRE_J2D_DI_CTAG_WDTH - 1):0] j2d_di_ctag; | |
| 186 | input j2d_di_cmd_vld; | |
| 187 | ||
| 188 | // request port | |
| 189 | input [(`FIRE_J2D_P_CMD_WDTH - 1):0] j2d_p_cmd; | |
| 190 | input [(`FIRE_J2D_P_ADDR_WDTH - 1):0] j2d_p_addr; | |
| 191 | input [(`FIRE_J2D_P_BMSK_WDTH - 1):0] j2d_p_bmsk; | |
| 192 | input [(`FIRE_J2D_P_CTAG_WDTH - 1):0] j2d_p_ctag; | |
| 193 | input j2d_p_cmd_vld; | |
| 194 | ||
| 195 | // ----- CRM: Req/Cpl Data Port ----- | |
| 196 | ||
| 197 | // completion port | |
| 198 | input [(`FIRE_J2D_D_DATA_WDTH - 1):0] j2d_d_data; | |
| 199 | input [(`FIRE_J2D_D_DPAR_WDTH - 1):0] j2d_d_data_par; | |
| 200 | input j2d_d_data_err; | |
| 201 | input j2d_d_data_vld; | |
| 202 | ||
| 203 | // request port | |
| 204 | input [(`FIRE_J2D_P_DATA_WDTH - 1):0] j2d_p_data; | |
| 205 | input [(`FIRE_J2D_P_DPAR_WDTH - 1):0] j2d_p_data_par; | |
| 206 | input j2d_p_data_vld; | |
| 207 | ||
| 208 | // -------------------------------------------------------- | |
| 209 | // ILU Interface | |
| 210 | // -------------------------------------------------------- | |
| 211 | ||
| 212 | // ----- CRM: DOU-DMA Status Port ----- | |
| 213 | output [(`FIRE_DLC_DOU_REL_WDTH - 1):0] k2y_dou_dptr; | |
| 214 | output k2y_dou_err; | |
| 215 | output k2y_dou_vld; | |
| 216 | ||
| 217 | // -------------------------------------------------------- | |
| 218 | // PSB Interface | |
| 219 | // -------------------------------------------------------- | |
| 220 | ||
| 221 | // ----- CRM: Scoreboard Access Port ----- | |
| 222 | output [(`FIRE_DLC_PSR_CMD_TYPE_WDTH - 1):0] cl2ps_e_cmd_type; | |
| 223 | output [(`FIRE_DLC_PSR_TRN_WDTH - 1):0] cl2ps_e_trn; | |
| 224 | output [(`FIRE_DLC_PSR_PIO_DATA_WDTH - 1):0] cl2ps_e_wr_data; | |
| 225 | output cl2ps_e_req; | |
| 226 | input [(`FIRE_DLC_PSR_DMA_DATA_WDTH - 1):0] ps2cl_e_rd_data; | |
| 227 | input ps2cl_e_gnt; | |
| 228 | ||
| 229 | // -------------------------------------------------------- | |
| 230 | // PMU Interface | |
| 231 | // -------------------------------------------------------- | |
| 232 | ||
| 233 | // ----- CTM: Ingress Command Record (ICR) Port ----- | |
| 234 | output cl2pm_rcd_full; | |
| 235 | input [(`FIRE_DLC_ICR_REC_WDTH - 1):0] pm2cl_rcd; | |
| 236 | input pm2cl_rcd_enq; | |
| 237 | ||
| 238 | // -------------------------------------------------------- | |
| 239 | // CMU Interface | |
| 240 | // -------------------------------------------------------- | |
| 241 | ||
| 242 | // ----- CRM: Egress Packet Record (EPR) Port ----- | |
| 243 | output [(`FIRE_DLC_EPR_REC_WDTH - 1):0] cl2cm_rcd; | |
| 244 | output cl2cm_rcd_enq; | |
| 245 | input cm2cl_rcd_full; | |
| 246 | ||
| 247 | // -------------------------------------------------------- | |
| 248 | // MMU Interface | |
| 249 | // -------------------------------------------------------- | |
| 250 | ||
| 251 | // ----- CTM: Tablewalk Command Record (TCR) Port ----- | |
| 252 | output cl2mm_tcr_ack; | |
| 253 | input [(`FIRE_DLC_TCR_WDTH - 1):0] mm2cl_tcr_rcd; | |
| 254 | input mm2cl_tcr_req; | |
| 255 | ||
| 256 | // ----- CRM: Tablewalk Data Record (TDR) Port ----- | |
| 257 | output [(`FIRE_DLC_TDR_WDTH - 1):0] cl2mm_tdr_rcd; | |
| 258 | output cl2mm_tdr_vld; | |
| 259 | ||
| 260 | // -------------------------------------------------------- | |
| 261 | // RMU Interface | |
| 262 | // -------------------------------------------------------- | |
| 263 | ||
| 264 | // ----- CTM: DOU DMA Buffer Release Port ----- | |
| 265 | input [(`FIRE_DLC_DOU_REL_WDTH - 1):0] rm2cl_bufrel; | |
| 266 | input rm2cl_bufrel_enq; | |
| 267 | ||
| 268 | // -------------------------------------------------------- | |
| 269 | // TMU Interface | |
| 270 | // -------------------------------------------------------- | |
| 271 | ||
| 272 | // ----- CTM: DIU Buffer Manager Port ----- | |
| 273 | output [(`FIRE_DLC_DMA_RPTR_WDTH - 1):0] cl2tm_dma_rptr; | |
| 274 | output [(`FIRE_DLC_INT_RPTR_WDTH - 1):0] cl2tm_int_rptr; | |
| 275 | input [(`FIRE_DLC_DMA_WPTR_WDTH - 1):0] tm2cl_dma_wptr; | |
| 276 | input [(`FIRE_DLC_PIO_WPTR_WDTH - 1):0] tm2cl_pio_wptr; | |
| 277 | ||
| 278 | // -------------------------------------------------------- | |
| 279 | // DIU Interface | |
| 280 | // -------------------------------------------------------- | |
| 281 | ||
| 282 | // ----- CTM: Data Buffer Read Port ----- | |
| 283 | output [(`FIRE_DLC_CRD_ADDR_WDTH - 1):0] cl2di_addr; | |
| 284 | output cl2di_rd_en; | |
| 285 | input [(`FIRE_DLC_CRD_DATA_WDTH - 1):0] di2cl_data; | |
| 286 | input [(`FIRE_DLC_CRD_BMASK_WDTH - 1):0] di2cl_bmask; | |
| 287 | input [(`FIRE_DLC_CRD_DPAR_WDTH - 1):0] di2cl_dpar; | |
| 288 | ||
| 289 | // -------------------------------------------------------- | |
| 290 | // DOU Interface | |
| 291 | // -------------------------------------------------------- | |
| 292 | ||
| 293 | // ----- CRM: DMA Data Buffer Write Port ----- | |
| 294 | output [(`FIRE_DLC_CDD_DATA_WDTH - 1):0] cl2do_dma_data; | |
| 295 | output [(`FIRE_DLC_CDD_DPAR_WDTH - 1):0] cl2do_dma_dpar; | |
| 296 | output [(`FIRE_DLC_CDD_ADDR_WDTH - 1):0] cl2do_dma_addr; | |
| 297 | output cl2do_dma_wr; | |
| 298 | ||
| 299 | // ----- CRM: PIO Data Buffer Write Port ----- | |
| 300 | output [(`FIRE_DLC_CPD_DATA_WDTH - 1):0] cl2do_pio_data; | |
| 301 | output [(`FIRE_DLC_CPD_DPAR_WDTH - 1):0] cl2do_pio_dpar; | |
| 302 | output [(`FIRE_DLC_CPD_ADDR_WDTH - 1):0] cl2do_pio_addr; | |
| 303 | output cl2do_pio_wr; | |
| 304 | ||
| 305 | // -------------------------------------------------------- | |
| 306 | // CRU Interface | |
| 307 | // -------------------------------------------------------- | |
| 308 | ||
| 309 | // ----- Debug Ports ----- | |
| 310 | output [`FIRE_DBG_DATA_BITS] cl2cr_dbg_a; | |
| 311 | output [`FIRE_DBG_DATA_BITS] cl2cr_dbg_b; | |
| 312 | input [5:0] cr2cl_dbg_sel_a; | |
| 313 | input [5:0] cr2cl_dbg_sel_b; | |
| 314 | ||
| 315 | // ----- Config Packet Setup ----- | |
| 316 | input [`FIRE_PCIE_BUS_NUM_BITS] cr2cl_bus_num; | |
| 317 | ||
| 318 | // ----- Config Packet Setup ----- | |
| 319 | input ds2cl_stall; | |
| 320 | ||
| 321 | // ----- force 1 outstanding non-posted write ----- | |
| 322 | input p2d_npwr_stall_en; | |
| 323 | input rm2crm_npwr_wrack; | |
| 324 | ||
| 325 | input im2crm_bc_stall_en; | |
| 326 | input im2crm_ilu_stall_en; | |
| 327 | input il2cl_gr_16; | |
| 328 | ||
| 329 | ||
| 330 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
| 331 | ||
| 332 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 333 | ||
| 334 | // -------------------------------------------------------- | |
| 335 | // CTM-CRM Sub-block Interface | |
| 336 | // -------------------------------------------------------- | |
| 337 | ||
| 338 | // ----- Unsupported Request Record (URR) Port ----- | |
| 339 | wire [(`FIRE_DLC_CLU_URR_WDTH - 1):0] ctm2crm_rcd; | |
| 340 | wire ctm2crm_rcd_enq; | |
| 341 | wire crm2ctm_rcd_deq; | |
| 342 | ||
| 343 | // ----- DMA/INT Tag Return Port ----- | |
| 344 | wire [3:0] crm2ctm_tag; | |
| 345 | wire crm2ctm_tag_enq; | |
| 346 | ||
| 347 | // ----- Debug Ports ----- | |
| 348 | wire [`FIRE_DBG_DATA_BITS] ctm_dbg0_bus_a; | |
| 349 | wire [`FIRE_DBG_DATA_BITS] ctm_dbg0_bus_b; | |
| 350 | wire [`FIRE_DBG_DATA_BITS] ctm_dbg1_bus_a; | |
| 351 | wire [`FIRE_DBG_DATA_BITS] ctm_dbg1_bus_b; | |
| 352 | wire [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_a; | |
| 353 | wire [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_b; | |
| 354 | wire [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_a; | |
| 355 | wire [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_b; | |
| 356 | ||
| 357 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
| 358 | ||
| 359 | // CTM Sub-block | |
| 360 | dmu_clu_ctm ctm | |
| 361 | ( | |
| 362 | // clock/reset | |
| 363 | .clk (clk), | |
| 364 | .rst_l (rst_l), | |
| 365 | ||
| 366 | // jbc: dmc req/cpl port | |
| 367 | .d2j_cmd (d2j_cmd), | |
| 368 | .d2j_addr (d2j_addr), | |
| 369 | .d2j_ctag (d2j_ctag), | |
| 370 | .d2j_cmd_vld (d2j_cmd_vld), | |
| 371 | .d2j_data (d2j_data), | |
| 372 | .d2j_bmsk (d2j_bmsk), | |
| 373 | .d2j_data_par (d2j_data_par), | |
| 374 | .d2j_data_vld (d2j_data_vld), | |
| 375 | ||
| 376 | // jbc : dma wrack port | |
| 377 | .j2d_d_wrack_tag (j2d_d_wrack_tag), | |
| 378 | .j2d_d_wrack_vld (j2d_d_wrack_vld), | |
| 379 | ||
| 380 | // pmu : icr port | |
| 381 | .cl2pm_rcd_full (cl2pm_rcd_full), | |
| 382 | .pm2cl_rcd (pm2cl_rcd), | |
| 383 | .pm2cl_rcd_enq (pm2cl_rcd_enq), | |
| 384 | ||
| 385 | // mmu : tcr port | |
| 386 | .cl2mm_tcr_ack (cl2mm_tcr_ack), | |
| 387 | .mm2cl_tcr_rcd (mm2cl_tcr_rcd), | |
| 388 | .mm2cl_tcr_req (mm2cl_tcr_req), | |
| 389 | ||
| 390 | // rmu : dou dma buffer rel port | |
| 391 | .rm2cl_bufrel (rm2cl_bufrel), | |
| 392 | .rm2cl_bufrel_enq (rm2cl_bufrel_enq), | |
| 393 | ||
| 394 | // tmu: diu buffer mgr port | |
| 395 | .cl2tm_dma_rptr (cl2tm_dma_rptr), | |
| 396 | .cl2tm_int_rptr (cl2tm_int_rptr), | |
| 397 | .tm2cl_dma_wptr (tm2cl_dma_wptr), | |
| 398 | .tm2cl_pio_wptr (tm2cl_pio_wptr), | |
| 399 | ||
| 400 | // diu : data read port | |
| 401 | .cl2di_addr (cl2di_addr), | |
| 402 | .cl2di_rd_en (cl2di_rd_en), | |
| 403 | .di2cl_data (di2cl_data), | |
| 404 | .di2cl_bmask (di2cl_bmask), | |
| 405 | .di2cl_dpar (di2cl_dpar), | |
| 406 | ||
| 407 | // crm : urr port | |
| 408 | .ctm2crm_rcd (ctm2crm_rcd), | |
| 409 | .ctm2crm_rcd_enq (ctm2crm_rcd_enq), | |
| 410 | .crm2ctm_rcd_deq (crm2ctm_rcd_deq), | |
| 411 | ||
| 412 | // crm: dma tag return port | |
| 413 | .crm2ctm_tag (crm2ctm_tag), | |
| 414 | .crm2ctm_tag_enq (crm2ctm_tag_enq), | |
| 415 | ||
| 416 | // cru : debug ports | |
| 417 | .ctm_dbg0_bus_a (ctm_dbg0_bus_a), | |
| 418 | .ctm_dbg0_bus_b (ctm_dbg0_bus_b), | |
| 419 | .ctm_dbg1_bus_a (ctm_dbg1_bus_a), | |
| 420 | .ctm_dbg1_bus_b (ctm_dbg1_bus_b), | |
| 421 | .cr2cl_dbg_sel_a (cr2cl_dbg_sel_a[2:0]), | |
| 422 | .cr2cl_dbg_sel_b (cr2cl_dbg_sel_b[2:0]), | |
| 423 | .ds2cl_stall (ds2cl_stall) | |
| 424 | ); | |
| 425 | ||
| 426 | // CRM Sub-block | |
| 427 | dmu_clu_crm crm | |
| 428 | ( | |
| 429 | // clock/reset | |
| 430 | .clk (clk), | |
| 431 | .rst_l (rst_l), | |
| 432 | ||
| 433 | // jbc: dma/int cpl port | |
| 434 | .j2d_di_cmd (j2d_di_cmd), | |
| 435 | .j2d_di_ctag (j2d_di_ctag), | |
| 436 | .j2d_di_cmd_vld (j2d_di_cmd_vld), | |
| 437 | .j2d_d_data (j2d_d_data), | |
| 438 | .j2d_d_data_par (j2d_d_data_par), | |
| 439 | .j2d_d_data_err (j2d_d_data_err), | |
| 440 | .j2d_d_data_vld (j2d_d_data_vld), | |
| 441 | ||
| 442 | // jbc: pio rd/wr req port | |
| 443 | .j2d_p_cmd (j2d_p_cmd), | |
| 444 | .j2d_p_addr (j2d_p_addr), | |
| 445 | .j2d_p_bmsk (j2d_p_bmsk), | |
| 446 | .j2d_p_ctag (j2d_p_ctag), | |
| 447 | .j2d_p_cmd_vld (j2d_p_cmd_vld), | |
| 448 | .j2d_p_data (j2d_p_data), | |
| 449 | .j2d_p_data_par (j2d_p_data_par), | |
| 450 | .j2d_p_data_vld (j2d_p_data_vld), | |
| 451 | ||
| 452 | // ilu: dou-dma status port | |
| 453 | .k2y_dou_dptr (k2y_dou_dptr), | |
| 454 | .k2y_dou_err (k2y_dou_err), | |
| 455 | .k2y_dou_vld (k2y_dou_vld), | |
| 456 | ||
| 457 | // psb : sbd access port | |
| 458 | .cl2ps_e_cmd_type (cl2ps_e_cmd_type), | |
| 459 | .cl2ps_e_trn (cl2ps_e_trn), | |
| 460 | .cl2ps_e_wr_data (cl2ps_e_wr_data), | |
| 461 | .cl2ps_e_req (cl2ps_e_req), | |
| 462 | .ps2cl_e_rd_data (ps2cl_e_rd_data), | |
| 463 | .ps2cl_e_gnt (ps2cl_e_gnt), | |
| 464 | ||
| 465 | // cmu : epr port | |
| 466 | .cl2cm_rcd (cl2cm_rcd), | |
| 467 | .cl2cm_rcd_enq (cl2cm_rcd_enq), | |
| 468 | .cm2cl_rcd_full (cm2cl_rcd_full), | |
| 469 | ||
| 470 | // mmu: tdr port | |
| 471 | .cl2mm_tdr_rcd (cl2mm_tdr_rcd), | |
| 472 | .cl2mm_tdr_vld (cl2mm_tdr_vld), | |
| 473 | ||
| 474 | // dou: data write port | |
| 475 | .cl2do_dma_data (cl2do_dma_data), | |
| 476 | .cl2do_dma_dpar (cl2do_dma_dpar), | |
| 477 | .cl2do_dma_addr (cl2do_dma_addr), | |
| 478 | .cl2do_dma_wr (cl2do_dma_wr), | |
| 479 | .cl2do_pio_data (cl2do_pio_data), | |
| 480 | .cl2do_pio_dpar (cl2do_pio_dpar), | |
| 481 | .cl2do_pio_addr (cl2do_pio_addr), | |
| 482 | .cl2do_pio_wr (cl2do_pio_wr), | |
| 483 | ||
| 484 | // ctm : urr port | |
| 485 | .crm2ctm_rcd_deq (crm2ctm_rcd_deq), | |
| 486 | .ctm2crm_rcd (ctm2crm_rcd), | |
| 487 | .ctm2crm_rcd_enq (ctm2crm_rcd_enq), | |
| 488 | ||
| 489 | // ctm: dma/int tag return port | |
| 490 | .crm2ctm_tag (crm2ctm_tag), | |
| 491 | .crm2ctm_tag_enq (crm2ctm_tag_enq), | |
| 492 | ||
| 493 | // cru : debug ports | |
| 494 | .crm_dbg0_bus_a (crm_dbg0_bus_a), | |
| 495 | .crm_dbg0_bus_b (crm_dbg0_bus_b), | |
| 496 | .crm_dbg1_bus_a (crm_dbg1_bus_a), | |
| 497 | .crm_dbg1_bus_b (crm_dbg1_bus_b), | |
| 498 | .cr2cl_dbg_sel_a (cr2cl_dbg_sel_a[2:0]), | |
| 499 | .cr2cl_dbg_sel_b (cr2cl_dbg_sel_b[2:0]), | |
| 500 | ||
| 501 | // cru : config packet setup | |
| 502 | .cr2cl_bus_num (cr2cl_bus_num), | |
| 503 | ||
| 504 | // force 1 outstanding non-posted pio write | |
| 505 | .p2d_npwr_stall_en (p2d_npwr_stall_en), | |
| 506 | .rm2crm_npwr_wrack (rm2crm_npwr_wrack), | |
| 507 | ||
| 508 | .im2crm_bc_stall_en (im2crm_bc_stall_en), | |
| 509 | .im2crm_ilu_stall_en (im2crm_ilu_stall_en), | |
| 510 | .il2cl_gr_16 (il2cl_gr_16), | |
| 511 | ||
| 512 | // used to keep ehb from filling for stall | |
| 513 | .d2j_cmd_bit3 (d2j_cmd[3]), | |
| 514 | .d2j_cmd_vld (d2j_cmd_vld) | |
| 515 | ); | |
| 516 | ||
| 517 | // DEBUG | |
| 518 | dmu_clu_debug debug | |
| 519 | ( | |
| 520 | // clock | |
| 521 | .clk (clk), | |
| 522 | .rst_l (rst_l), | |
| 523 | ||
| 524 | // cru : debug ports | |
| 525 | .cl2cr_dbg_a (cl2cr_dbg_a), | |
| 526 | .cl2cr_dbg_b (cl2cr_dbg_b), | |
| 527 | .cr2cl_dbg_sel_a (cr2cl_dbg_sel_a[5:3]), | |
| 528 | .cr2cl_dbg_sel_b (cr2cl_dbg_sel_b[5:3]), | |
| 529 | ||
| 530 | // ctm : debug ports | |
| 531 | .ctm_dbg0_bus_a (ctm_dbg0_bus_a), | |
| 532 | .ctm_dbg0_bus_b (ctm_dbg0_bus_b), | |
| 533 | .ctm_dbg1_bus_a (ctm_dbg1_bus_a), | |
| 534 | .ctm_dbg1_bus_b (ctm_dbg1_bus_b), | |
| 535 | ||
| 536 | // crm : debug ports | |
| 537 | .crm_dbg0_bus_a (crm_dbg0_bus_a), | |
| 538 | .crm_dbg0_bus_b (crm_dbg0_bus_b), | |
| 539 | .crm_dbg1_bus_a (crm_dbg1_bus_a), | |
| 540 | .crm_dbg1_bus_b (crm_dbg1_bus_b) | |
| 541 | ); | |
| 542 | ||
| 543 | endmodule // dmu_clu |