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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_clu_crm_datactl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
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32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_clu_crm_datactl | |
36 | ( | |
37 | // clock/reset | |
38 | clk, | |
39 | rst_l, | |
40 | ||
41 | // jbc: dma data ctl port | |
42 | dctag_typ, | |
43 | dctag_dptr, | |
44 | dctag_misc, | |
45 | j2d_di_cmd, | |
46 | j2d_di_cmd_vld, | |
47 | j2d_d_data_err, | |
48 | j2d_d_data_vld, | |
49 | ||
50 | // jbc: pio data ctl port | |
51 | pctag_trnsnum, | |
52 | j2d_p_cmd_vld, | |
53 | j2d_p_data_vld, | |
54 | ||
55 | // mmu: tdr port | |
56 | tdr_mtag, | |
57 | tdr_cerr, | |
58 | cl2mm_tdr_vld, | |
59 | ||
60 | // dou: data ctl port | |
61 | cl2do_dma_addr, | |
62 | cl2do_dma_wr, | |
63 | cl2do_pio_addr, | |
64 | cl2do_pio_wr, | |
65 | ||
66 | // ilu: cacheline sts port | |
67 | k2y_dou_dptr, | |
68 | k2y_dou_err, | |
69 | k2y_dou_vld | |
70 | ); | |
71 | ||
72 | // synopsys sync_set_reset "rst_l" | |
73 | ||
74 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
75 | ||
76 | parameter DCTAG_DPTR_WDTH = 5; | |
77 | parameter DCTAG_MISC_WDTH = 6; | |
78 | parameter PCTAG_TRNSNUM_WDTH = 4; | |
79 | ||
80 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
81 | ||
82 | // -------------------------------------------------------- | |
83 | // Clock/Reset Signals | |
84 | // -------------------------------------------------------- | |
85 | ||
86 | input clk; | |
87 | input rst_l; | |
88 | ||
89 | // -------------------------------------------------------- | |
90 | // JBC Interface | |
91 | // -------------------------------------------------------- | |
92 | ||
93 | // ----- DMA/INT Cpl Port ----- | |
94 | input dctag_typ; | |
95 | input [(DCTAG_DPTR_WDTH - 1):0] dctag_dptr; | |
96 | input [(DCTAG_MISC_WDTH - 1):0] dctag_misc; | |
97 | input [(`FIRE_J2D_DI_CMD_WDTH - 1):0] j2d_di_cmd; | |
98 | input j2d_di_cmd_vld; | |
99 | input j2d_d_data_err; | |
100 | input j2d_d_data_vld; | |
101 | ||
102 | // ----- PIO Rd/Wr Req Port ----- | |
103 | input [(PCTAG_TRNSNUM_WDTH - 1):0] pctag_trnsnum; | |
104 | input j2d_p_cmd_vld; | |
105 | input j2d_p_data_vld; | |
106 | ||
107 | // -------------------------------------------------------- | |
108 | // MMU Interface | |
109 | // -------------------------------------------------------- | |
110 | ||
111 | // ----- Tablewalk Data Record (TDR) Port ----- | |
112 | output [(`FIRE_DLC_TDR_MTAG_WDTH - 1):0] tdr_mtag; | |
113 | output tdr_cerr; | |
114 | output cl2mm_tdr_vld; | |
115 | ||
116 | // -------------------------------------------------------- | |
117 | // DOU Interface | |
118 | // -------------------------------------------------------- | |
119 | ||
120 | // ----- DMA Data Buffer Write Port ----- | |
121 | output [(`FIRE_DLC_CDD_ADDR_WDTH - 1):0] cl2do_dma_addr; | |
122 | output cl2do_dma_wr; | |
123 | ||
124 | // ----- PIO Data Buffer Write Port ----- | |
125 | output [(`FIRE_DLC_CPD_ADDR_WDTH - 1):0] cl2do_pio_addr; | |
126 | output cl2do_pio_wr; | |
127 | ||
128 | // -------------------------------------------------------- | |
129 | // ILU Interface | |
130 | // -------------------------------------------------------- | |
131 | ||
132 | // ----- DOU-DMA Status Port ----- | |
133 | output [(`FIRE_DLC_DOU_REL_WDTH - 1):0] k2y_dou_dptr; | |
134 | output k2y_dou_err; | |
135 | output k2y_dou_vld; | |
136 | ||
137 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
138 | ||
139 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
140 | ||
141 | // ********** Flops ********** | |
142 | ||
143 | // misc register for dma/mmu | |
144 | reg [(DCTAG_MISC_WDTH - 1):0] misc_reg; | |
145 | ||
146 | // mmu regs | |
147 | reg tdr_cerr; | |
148 | reg mmu_vld_s0; | |
149 | reg mmu_vld_s1; | |
150 | reg mmu_vld_s2; | |
151 | reg mmu_vld_s3; | |
152 | ||
153 | // dma regs | |
154 | reg [1:0] dma_row_wrptr; | |
155 | reg dma_wr_s0; | |
156 | reg dma_wr_s1; | |
157 | reg dma_wr_s2; | |
158 | reg dma_wr_s3; | |
159 | ||
160 | // pio regs | |
161 | reg [(`FIRE_DLC_CPD_ADDR_WDTH - 1):0] pio_buf_addr; | |
162 | reg cl2do_pio_wr; | |
163 | ||
164 | // ilu cl_sts regs | |
165 | reg ilu_vld_s0; | |
166 | reg ilu_vld_s1; | |
167 | reg ilu_vld_s2; | |
168 | reg ilu_vld_s3; | |
169 | reg data_derr_s0; | |
170 | reg data_derr_s1; | |
171 | reg data_derr_s2; | |
172 | reg k2y_dou_err; | |
173 | ||
174 | // ********** Non-Flops ****** | |
175 | ||
176 | // next misc register for dma/mmu | |
177 | reg [(DCTAG_MISC_WDTH - 1):0] nxt_misc_reg; | |
178 | ||
179 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
180 | ||
181 | wire [4:0] dma_blk_wrptr; | |
182 | wire [1:0] dma_row_wrptr_inc; | |
183 | wire [1:0] pio_row_wrptr_inc; | |
184 | ||
185 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
186 | ||
187 | // -------------------------------------------------------- | |
188 | // DCTAG_MISC - TDR_CERR REGISTERS | |
189 | // -------------------------------------------------------- | |
190 | ||
191 | // tdr_cerr = (1'b1 if j2d_di_cmd = 2'b01), (1'b0 if j2d_di_cmd = 2'b00) | |
192 | ||
193 | // next misc reg value | |
194 | always @(dctag_dptr or dctag_misc or dctag_typ) | |
195 | begin | |
196 | nxt_misc_reg[5] = dctag_misc[5]; | |
197 | if (dctag_typ) // 1 = mmu, 0 = dma | |
198 | nxt_misc_reg[4:0] = dctag_misc[4:0]; | |
199 | else | |
200 | nxt_misc_reg[4:0] = dctag_dptr; | |
201 | end | |
202 | ||
203 | // misc/tdr_cerr regs | |
204 | always @(posedge clk) | |
205 | if (~rst_l) | |
206 | begin | |
207 | misc_reg <= 6'b0; | |
208 | tdr_cerr <= 1'b0; | |
209 | end | |
210 | else if (j2d_di_cmd_vld) | |
211 | begin | |
212 | misc_reg <= nxt_misc_reg; | |
213 | tdr_cerr <= j2d_di_cmd[0]; | |
214 | end | |
215 | ||
216 | // output tdr_mtag | |
217 | assign tdr_mtag = misc_reg; | |
218 | ||
219 | // dma blk_wr_ptr | |
220 | assign dma_blk_wrptr = misc_reg[4:0]; | |
221 | ||
222 | // -------------------------------------------------------- | |
223 | // MMU TDR CONTROL | |
224 | // -------------------------------------------------------- | |
225 | ||
226 | // mmu tdr_vld - shift reg to gen tdr_enq to mmu | |
227 | always @(posedge clk) | |
228 | if (~rst_l) | |
229 | begin | |
230 | mmu_vld_s0 <= 1'b0; | |
231 | mmu_vld_s1 <= 1'b0; | |
232 | mmu_vld_s2 <= 1'b0; | |
233 | mmu_vld_s3 <= 1'b0; | |
234 | end | |
235 | else | |
236 | begin | |
237 | casez ({j2d_di_cmd_vld, dctag_typ, j2d_d_data_vld}) | |
238 | ||
239 | // 0in < case -parallel -full | |
240 | ||
241 | 3'b0_zz, | |
242 | 3'b1_0z : | |
243 | begin | |
244 | mmu_vld_s0 <= 1'b0; | |
245 | mmu_vld_s1 <= mmu_vld_s0; | |
246 | mmu_vld_s2 <= mmu_vld_s1; | |
247 | mmu_vld_s3 <= mmu_vld_s2; | |
248 | end | |
249 | 3'b1_10 : | |
250 | begin | |
251 | mmu_vld_s0 <= 1'b0; | |
252 | mmu_vld_s1 <= 1'b0; | |
253 | mmu_vld_s2 <= 1'b0; | |
254 | mmu_vld_s3 <= 1'b1; | |
255 | end | |
256 | 3'b1_11 : | |
257 | begin | |
258 | mmu_vld_s0 <= 1'b1; | |
259 | mmu_vld_s1 <= 1'b1; | |
260 | mmu_vld_s2 <= 1'b1; | |
261 | mmu_vld_s3 <= 1'b1; | |
262 | end | |
263 | endcase | |
264 | end | |
265 | ||
266 | // output tdr_enq to mmu | |
267 | assign cl2mm_tdr_vld = mmu_vld_s3; | |
268 | ||
269 | // -------------------------------------------------------- | |
270 | // ILU CACHELINE STATUS CONTROL | |
271 | // -------------------------------------------------------- | |
272 | ||
273 | // ilu cl_sts_enq - shift reg to gen cl_sts_enq to ilu | |
274 | always @(posedge clk) | |
275 | if (~rst_l) | |
276 | begin // reset pipeline | |
277 | ilu_vld_s0 <= 1'b0; | |
278 | ilu_vld_s1 <= 1'b0; | |
279 | ilu_vld_s2 <= 1'b0; | |
280 | ilu_vld_s3 <= 1'b0; | |
281 | end | |
282 | else if (j2d_di_cmd_vld & ~j2d_di_cmd[1] & ~j2d_di_cmd[0]) | |
283 | begin // 4 data beat rd_cpl | |
284 | ilu_vld_s0 <= ~dctag_typ; | |
285 | ilu_vld_s1 <= 1'b0; | |
286 | ilu_vld_s2 <= 1'b0; | |
287 | ilu_vld_s3 <= 1'b0; | |
288 | end | |
289 | else if (j2d_di_cmd_vld & ~j2d_di_cmd[1] & j2d_di_cmd[0]) | |
290 | begin // 0 data beat rd_cpl | |
291 | ilu_vld_s0 <= 1'b0; | |
292 | ilu_vld_s1 <= 1'b0; | |
293 | ilu_vld_s2 <= 1'b0; | |
294 | ilu_vld_s3 <= ~dctag_typ; | |
295 | end | |
296 | else | |
297 | begin // ilu enq pipeline | |
298 | ilu_vld_s0 <= 1'b0; | |
299 | ilu_vld_s1 <= ilu_vld_s0; | |
300 | ilu_vld_s2 <= ilu_vld_s1; | |
301 | ilu_vld_s3 <= ilu_vld_s2; | |
302 | end | |
303 | ||
304 | // pipe j2d_d_data_err | |
305 | always @(posedge clk) | |
306 | if (~rst_l) | |
307 | begin // reset pipeline | |
308 | data_derr_s0 <= 1'b0; | |
309 | data_derr_s1 <= 1'b0; | |
310 | data_derr_s2 <= 1'b0; | |
311 | end | |
312 | else begin | |
313 | data_derr_s0 <= j2d_d_data_err; | |
314 | data_derr_s1 <= data_derr_s0; | |
315 | data_derr_s2 <= data_derr_s1; | |
316 | end | |
317 | ||
318 | // output ilu cacheline status | |
319 | always @(posedge clk) | |
320 | if (~rst_l) | |
321 | begin // reset pipeline | |
322 | k2y_dou_err <= 1'b0; | |
323 | end | |
324 | else begin | |
325 | k2y_dou_err <= (j2d_d_data_err | data_derr_s0 | data_derr_s1 | | |
326 | data_derr_s2 | (j2d_di_cmd_vld & j2d_di_cmd[0])); | |
327 | end | |
328 | ||
329 | // output cl_sts_enq to ilu | |
330 | assign k2y_dou_vld = ilu_vld_s3; | |
331 | ||
332 | // output cl_sts dptr to ilu | |
333 | assign k2y_dou_dptr = misc_reg[4:0]; | |
334 | ||
335 | // -------------------------------------------------------- | |
336 | // DOU DATA BUFFER : DMA CONTROL | |
337 | // -------------------------------------------------------- | |
338 | ||
339 | // dma data buffer wr_enq - shift reg to gen wr_enq to dou | |
340 | always @(posedge clk) | |
341 | if (~rst_l) | |
342 | begin | |
343 | dma_wr_s0 <= 1'b0; | |
344 | dma_wr_s1 <= 1'b0; | |
345 | dma_wr_s2 <= 1'b0; | |
346 | dma_wr_s3 <= 1'b0; | |
347 | end | |
348 | else if (j2d_di_cmd_vld & j2d_d_data_vld) | |
349 | begin | |
350 | dma_wr_s0 <= ~dctag_typ; | |
351 | dma_wr_s1 <= ~dctag_typ; | |
352 | dma_wr_s2 <= ~dctag_typ; | |
353 | dma_wr_s3 <= ~dctag_typ; | |
354 | end | |
355 | else | |
356 | begin | |
357 | dma_wr_s0 <= 1'b0; | |
358 | dma_wr_s1 <= dma_wr_s0; | |
359 | dma_wr_s2 <= dma_wr_s1; | |
360 | dma_wr_s3 <= dma_wr_s2; | |
361 | end | |
362 | ||
363 | // output dma wr_enq to dou | |
364 | assign cl2do_dma_wr = dma_wr_s3; | |
365 | ||
366 | // dma row_wr_ptr incrementer | |
367 | assign dma_row_wrptr_inc = ((dma_row_wrptr + 1'b1) & {2{~j2d_di_cmd_vld}}); | |
368 | ||
369 | // dma row_wr_ptr register | |
370 | always @(posedge clk) | |
371 | if (~rst_l) | |
372 | dma_row_wrptr <= 2'b0; | |
373 | else if (j2d_d_data_vld) | |
374 | dma_row_wrptr <= dma_row_wrptr_inc; | |
375 | ||
376 | // dma complete wr_address | |
377 | assign cl2do_dma_addr = {dma_blk_wrptr, dma_row_wrptr}; | |
378 | ||
379 | // -------------------------------------------------------- | |
380 | // DOU DATA BUFFER : PIO CONTROL | |
381 | // -------------------------------------------------------- | |
382 | ||
383 | // pio data buffer wr_enq | |
384 | always @(posedge clk) | |
385 | if (~rst_l) | |
386 | cl2do_pio_wr <= 1'b0; | |
387 | else | |
388 | cl2do_pio_wr <= j2d_p_data_vld; | |
389 | ||
390 | // pio blk_wr_ptr | |
391 | /* always @(posedge clk) | |
392 | // if (~rst_l) | |
393 | // pio_buf_addr[5:2] <= 4'b0; | |
394 | // else if (j2d_p_cmd_vld) | |
395 | // pio_buf_addr[5:2] <= pctag_trnsnum; | |
396 | // | |
397 | // // pio row_wr_ptr incrementer | |
398 | // assign pio_row_wrptr_inc = (pio_buf_addr[1:0] + 1'b1) & {2{~j2d_p_cmd_vld}}; | |
399 | // | |
400 | // // pio row_wr_ptr register | |
401 | // always @(posedge clk) | |
402 | // if (~rst_l) | |
403 | // pio_buf_addr[1:0] <= 2'b0; | |
404 | // else if (j2d_p_data_vld) | |
405 | // pio_buf_addr[1:0] <= pio_row_wrptr_inc; | |
406 | */ | |
407 | always @(posedge clk) | |
408 | if (~rst_l) | |
409 | pio_buf_addr[5:0] <= 6'b0; | |
410 | else if (j2d_p_cmd_vld) | |
411 | pio_buf_addr[5:0] <= {2'b00,pctag_trnsnum}; | |
412 | ||
413 | // pio complete wr_address | |
414 | assign cl2do_pio_addr = pio_buf_addr; | |
415 | ||
416 | endmodule // dmu_clu_crm_datactl |