Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_clu_crm_datapipe.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_clu_crm_datapipe | |
36 | ( | |
37 | // clock | |
38 | clk, | |
39 | rst_l, | |
40 | ||
41 | // jbc: dma data port | |
42 | j2d_d_data_vld, | |
43 | j2d_d_data, | |
44 | j2d_d_data_par, | |
45 | j2d_d_data_err, | |
46 | ||
47 | // jbc: pio data port | |
48 | j2d_p_data, | |
49 | j2d_p_data_par, | |
50 | ||
51 | // mmu: tdr port | |
52 | tdr_data, | |
53 | tdr_dpar, | |
54 | tdr_derr, | |
55 | ||
56 | // dou: data port | |
57 | cl2do_dma_data, | |
58 | cl2do_dma_dpar, | |
59 | cl2do_pio_data, | |
60 | cl2do_pio_dpar | |
61 | ); | |
62 | ||
63 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
64 | ||
65 | // -------------------------------------------------------- | |
66 | // Clock Signal | |
67 | // -------------------------------------------------------- | |
68 | ||
69 | input clk; | |
70 | input rst_l; | |
71 | ||
72 | // -------------------------------------------------------- | |
73 | // JBC Interface | |
74 | // -------------------------------------------------------- | |
75 | ||
76 | // Data Port -> DMA Resp | |
77 | input j2d_d_data_vld; // dma data vld | |
78 | input [(`FIRE_J2D_D_DATA_WDTH - 1):0] j2d_d_data; // dma rd data | |
79 | input [(`FIRE_J2D_D_DPAR_WDTH - 1):0] j2d_d_data_par; // data parity | |
80 | input j2d_d_data_err; // data status | |
81 | ||
82 | // Data Port -> PIO Req | |
83 | input [(`FIRE_J2D_P_DATA_WDTH - 1):0] j2d_p_data; // pio wr data | |
84 | input [(`FIRE_J2D_P_DPAR_WDTH - 1):0] j2d_p_data_par; // data parity | |
85 | ||
86 | // -------------------------------------------------------- | |
87 | // MMU Interface | |
88 | // -------------------------------------------------------- | |
89 | ||
90 | // Tablewalk Data Record (TDR) Port | |
91 | output [(`FIRE_DLC_TDR_DATA_WDTH - 1):0] tdr_data; | |
92 | output [(`FIRE_DLC_TDR_DPAR_WDTH - 1):0] tdr_dpar; | |
93 | output tdr_derr; | |
94 | ||
95 | // -------------------------------------------------------- | |
96 | // DOU Interface | |
97 | // -------------------------------------------------------- | |
98 | ||
99 | // DMA Data Buffer Write Port | |
100 | output [(`FIRE_DLC_CDD_DATA_WDTH - 1):0] cl2do_dma_data; // dma rd data | |
101 | output [(`FIRE_DLC_CDD_DPAR_WDTH - 1):0] cl2do_dma_dpar; // dma data par | |
102 | ||
103 | // PIO Data Buffer Write Port | |
104 | output [(`FIRE_DLC_CPD_DATA_WDTH - 1):0] cl2do_pio_data; // pio wr data | |
105 | output [(`FIRE_DLC_CPD_DPAR_WDTH - 1):0] cl2do_pio_dpar; // pio data par | |
106 | ||
107 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
108 | ||
109 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
110 | ||
111 | // ********** Flops ********** | |
112 | ||
113 | // dma data_regs | |
114 | reg [(`FIRE_J2D_D_DATA_WDTH - 1):0] dma_data_reg; | |
115 | reg [(`FIRE_J2D_D_DPAR_WDTH - 1):0] dma_dpar_reg; | |
116 | reg mmu_derr_reg; | |
117 | ||
118 | // pio data_regs | |
119 | reg [(`FIRE_J2D_P_DATA_WDTH - 1):0] pio_data_reg; | |
120 | reg [(`FIRE_J2D_P_DPAR_WDTH - 1):0] pio_dpar_reg; | |
121 | ||
122 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
123 | ||
124 | // -------------------------------------------------------- | |
125 | // Sequential Logic | |
126 | // -------------------------------------------------------- | |
127 | ||
128 | // pio: piped data path | |
129 | always @(posedge clk) | |
130 | if (~rst_l) | |
131 | begin | |
132 | pio_data_reg <= `FIRE_J2D_P_DATA_WDTH'b0; | |
133 | pio_dpar_reg <= `FIRE_J2D_P_DPAR_WDTH'b0; | |
134 | end | |
135 | else begin | |
136 | pio_data_reg <= j2d_p_data; | |
137 | pio_dpar_reg <= j2d_p_data_par; | |
138 | end | |
139 | ||
140 | // dma: piped data path | |
141 | always @(posedge clk) | |
142 | if (~rst_l) | |
143 | begin | |
144 | dma_data_reg <= `FIRE_J2D_D_DATA_WDTH'b0; | |
145 | dma_dpar_reg <= `FIRE_J2D_D_DPAR_WDTH'b0; | |
146 | mmu_derr_reg <= 1'b0; | |
147 | end | |
148 | else begin | |
149 | dma_data_reg <= j2d_d_data; | |
150 | dma_dpar_reg <= j2d_d_data_par; | |
151 | mmu_derr_reg <= j2d_d_data_err & j2d_d_data_vld; | |
152 | end | |
153 | ||
154 | // -------------------------------------------------------- | |
155 | // Data Path Output | |
156 | // -------------------------------------------------------- | |
157 | ||
158 | // mmu tdr data path | |
159 | assign tdr_data = dma_data_reg; | |
160 | assign tdr_dpar = dma_dpar_reg; | |
161 | assign tdr_derr = mmu_derr_reg; | |
162 | ||
163 | // dou dma data path | |
164 | assign cl2do_dma_data = dma_data_reg; | |
165 | assign cl2do_dma_dpar = dma_dpar_reg; | |
166 | ||
167 | // dou pio data path | |
168 | assign cl2do_pio_data = pio_data_reg; | |
169 | assign cl2do_pio_dpar = pio_dpar_reg; | |
170 | ||
171 | endmodule // dmu_clu_crm_datapipe |